CN103700397B - SRAM memory cell, SRAM memory cell write operation method and SRAM memory - Google Patents

Abstract

The invention discloses a kind of SRAM memory cell, SRAM memory cell write operation method and SRAM memory.The SRAM memory cell includes：Data latches, selection control, the first transfer tube and the second transfer tube, the selection control are connected with the power supply of the data latches, and the power supply for controlling the data latches is connected with supply voltage or is connected with ground level.The write operation method includes：Before write operation is carried out to the SRAM memory cell, the SRAM memory cell is reset, the first memory node and the second memory node is discharged to ground level.The present invention can improve the reliability of SRAM memory cell write operation, reduce instantaneous power consumption during write operation.

Description

SRAM storage unit, SRAM storage unit write operation method and SRAM memory

technical field

The invention relates to the technical field of semiconductors, in particular to an SRAM storage unit, an SRAM storage unit writing operation method and an SRAM memory.

Background technique

According to the different ways of storing data, semiconductor memory can be divided into two categories: random access memory (RAM) and read-only memory (ROM). Random access memory (RAM) can be divided into static random access memory (SRAM) and dynamic random access memory (DRAM). Compared with DRAM, SRAM has faster read and write speeds. Moreover, SRAM does not need to periodically refresh the stored information, and its design and manufacture are relatively simple.

The storage unit is the most basic and important component of the SRAM memory, occupying most of the entire SRAM memory area. The stability of the storage unit determines the data reliability of the memory.

The mainstream SRAM memory cell is a six-transistor cell (6T). As shown in FIG. 1 , the 6T memory cell is symmetrical and consists of six MOS transistors. Among them, MOS transistors M1~M4 constitute two cross-coupled inverters, which are used to latch storage nodes signal of. The MOS transistors M5 and M6 are transmission transistors, and they play a role of connecting or disconnecting the storage unit with the bit line when performing read/write operations on the SRAM memory.

The SRAM storage unit has three states in total, namely: read, write and data hold.

When reading data, the bit line Firstly, it is charged to a high level, and then the word line WL is charged to a high level, so that the transmission tube M5/M6 is turned on, and the storage node bit/bit_ is directed to the bit line Discharge causes the voltage of one bit line to drop by ΔV while the other bit line remains high, and the sense amplifier amplifies the voltage difference ΔV to read the data.

When writing data, first precharge a certain bit line to a high level according to the data to be written, and at the same time discharge the other bit line to a ground level. Then charge the word line WL to a high level, turn on the transfer transistor M5/M6, and charge and discharge the bit line to the storage node bit/bit_. At this time, it is necessary to ensure that the charge/discharge current is greater than the current of the pull-down/pull-up path, so that the voltage of the storage node bit/bit_ is sufficient to reverse the inverter, otherwise it is a failed write (fail write).

In the prior art, through the size design of each MOS transistor, a certain strength relationship exists between each MOS transistor to ensure successful writing of data. Once the charging and discharging capability of each MOS tube changes, the data may still be wrongly written.

Contents of the invention

The technical problem to be solved by the invention is how to improve the reliability of the write operation of the SRAM storage unit.

In order to solve the above problems, the invention provides a kind of SRAM storage unit, comprising:

a data latch comprising a first storage node and a second storage node;

a selection controller, the selection controller is connected to the power supply of the data latch, and is used to control the power supply of the data latch to be connected to a power supply voltage or to a ground level;

a first transmission pipe, the first transmission pipe is located between the first bit line and the first storage node;

a second transmission pipe, the second transmission pipe is located between the second bit line and the second storage node;

Both the gate of the first transfer transistor and the gate of the second transfer transistor are connected to a word line.

Optionally, the selection controller is controlled by the write control signal of the SRAM storage unit, so that the power supply of the data latch is connected to the ground level before the write control signal is valid, and when the write control signal is valid connected to the supply voltage.

Optionally, the selection controller is controlled by a reset control signal; the reset control signal is valid, the selection controller connects the power supply of the data latch to the ground level, and the reset control signal is invalid, The selection controller connects the power supply of the data latch to a supply voltage.

Optionally, the SRAM storage unit is a standard 6T storage unit;

The data latch includes: a first inverter and a second inverter, the first inverter and the second inverter are cross-coupled;

The first inverter includes: a first PMOS transistor and a first NMOS transistor;

The second inverter includes: a second PMOS transistor and a second NMOS transistor;

The power supply of the data latch includes: the source of the first PMOS transistor and the source of the second PMOS transistor.

The present invention also provides a method for writing an SRAM storage unit, which is suitable for the above-mentioned SRAM storage unit, including:

Before performing a write operation on the SRAM storage unit, the SRAM storage unit is cleared to discharge the first storage node and the second storage node to ground level.

Optionally, the clearing the SRAM storage unit includes:

connecting the first bit line and the second bit line to a ground level;

connecting the power supply of the data latch to the ground level;

The word line is connected to a supply voltage.

Optionally, the writing operation to the SRAM storage unit includes:

connecting the power supply of the data latch to a supply voltage;

Loading the first bit line and the second bit line with data to be written.

Optionally, the clearing lasts at least 3 ns.

The present invention also provides an SRAM memory, including: the above-mentioned SRAM storage unit.

Compared with the prior art, the technical solution of the present invention has the following advantages:

Before writing the SRAM storage unit, the present invention first clears the original stored data, and lowers the voltages of the two storage nodes of the SRAM storage unit to the ground level, so that the data sent by the bit line during the write operation will not be different from the data of the original storage nodes. There is a charge-discharge conflict, thereby reducing the instantaneous power consumption during the write operation and improving the overall yield of the SRAM memory.

Description of drawings

Fig. 1 is a structural representation of a prior art SRAM storage unit;

Fig. 2 is the structural representation of an embodiment of the SRAM storage unit of the present invention;

Fig. 3 is the schematic flow chart of an embodiment of the SRAM storage unit write operation method of the present invention;

FIG. 4 is a timing diagram of an embodiment of a method for writing an SRAM storage unit according to the present invention.

detailed description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

Secondly, the present invention is described in detail by means of schematic diagrams. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention.

The inventor has analyzed and studied the failure of writing, and found that the reason for the failure of writing is that the charging and discharging conflicts of each tube may occur during the writing process.

Due to the write operation, the two bit lines are always one high and one low. The previous write operation keeps the voltages of the two storage nodes in the SRAM storage unit high and low. When the high-level bit line discharges to the low-level storage node, the transmission tube and the NMOS tube in the data latch form a path, the bit line voltage is pulled down, and the low-level storage node voltage rises but not enough to make Another NMOS tube is turned on. When the low-level bit line is charged by the high-level storage node, the PMOS transistor and the transmission tube form a path, and when the voltage of the high-level storage node drops to turn on the other PMOS transistor, the storage state of the latch switches, and the writing is completed. . In this process, for a period of time, the PMOS and NMOS transistors are turned on at the same time, and there is a quiescent current. Moreover, there are strict requirements on the strength of the six tubes, so that each tube can be turned on in sequence according to the correct current direction, otherwise errors will be written.

Therefore, the inventor provides a new writing method, which can effectively avoid the charge-discharge conflict during the writing process and improve the writing reliability.

In order to solve the technical problems in the background technology, the present invention provides an SRAM storage unit. FIG. 2 is a schematic structural diagram of an embodiment of the SRAM storage unit of the present invention. As shown in Figure 2, this embodiment is a standard 6T storage unit, including: a data latch composed of a first PMOS transistor M3, a first NMOS transistor M1, a second PMOS transistor M4, and a second NMOS transistor M2 cross-coupled device; the first transmission pipe M5; the second transmission pipe M6 and the selection controller S.

The first PMOS transistor M3 and the first NMOS transistor M1 form a first inverter. The second PMOS transistor M4 and the second NMOS transistor M2 form a second inverter.

The first storage node bit is located between the drain of the first PMOS transistor M3 and the drain of the first NMOS transistor M1, and is coupled to the gate of the second PMOS transistor M4 and the second NMOS between the gates of tube M2.

The second storage node bit_ is located between the drain of the second PMOS transistor M4 and the drain of the second NMOS transistor M2, and is simultaneously coupled to the gate of the first PMOS transistor M3 and the first NMOS transistor M3. between the gates of tube M1.

The first transfer transistor M5 is located between the first storage node bit and the first bit line BL.

The second transfer transistor M6 is located between the second storage node bit_ and the second bit line between.

Both the gate of the first transfer transistor M5 and the gate M6 of the second transfer transistor are connected to the word line WL.

The power supply latch of the data latch (that is, the source of the first PMOS transistor M3 and the source of the second PMOS transistor M4 ) is connected to the selection controller S.

The selection controller S controls the power supply latch of the data latch to be connected to the power supply voltage VDD or connected to the ground level.

In this embodiment, the selection controller S is controlled by a reset control signal RST. When the reset control signal RST is valid, the original stored data starts to be cleared. Specifically, the first bit line BL and the second bit line is sent to the ground level, the selection controller S connects the power supply latch of the data latch to the ground level, and the word line WL is sent to the power supply voltage VDD. When the reset control signal RST is invalid, the selection controller S connects the power supply latch of the data latch to the power supply voltage VDD, so that new data can be written. Those skilled in the art can understand that the SRAM storage unit of this embodiment adds a step of clearing the original stored data before the write operation, so in other embodiments, the selection controller S can also be controlled by the The write control signal of the SRAM storage unit (not shown in the figure) connects the power supply latch of the data latch to the ground level before the write control signal is valid, and connects to the power supply voltage VDD when the write control signal is valid.

The SRAM storage unit of this embodiment can clear the original stored data before the write operation, thereby effectively avoiding the charge-discharge conflict between the tubes during the write process.

It should be noted that those skilled in the art can understand that although the SRAM storage unit in this embodiment is a standard 6T unit, it should not be construed as a limitation on the SRAM storage unit. In other embodiments, other types of SRAM memory cells, such as 4T, 8T, etc., are applicable to the present invention.

Correspondingly, the present invention also provides a method for writing an SRAM storage unit. FIG. 3 is a schematic flowchart of an embodiment of a method for writing an SRAM storage unit according to the present invention. As shown in Figure 3, this embodiment includes the following steps:

Step 101 is executed to clear the SRAM storage unit, so that the first storage node and the second storage node are discharged to ground level.

Specifically, the first bit line BL and the second bit line can be connected Connect to ground level. Then connect the power supply latch of the data latch to the ground level, so that the voltage of the first storage node and the voltage of the second storage node continue to drop. Finally, the word line WL is connected to the power supply voltage VDD to turn on the first transfer transistor M5 and the second transfer transistor M6. After conduction, the ground level of the first bit line BL and the second bit line The ground levels of will be respectively written into the first storage node and the second storage node.

Specifically, the clearing lasts at least 3 ns to ensure that the voltages of the first storage node and the second storage node have dropped to ground level, and the original stored data is cleared.

Afterwards, step 102 is performed to perform a write operation on the SRAM storage unit.

Specifically, the power supply latch of the data latch may be connected to the power supply voltage VDD. Next, the first bit line BL and the second bit line are loaded with data to be written, and a write operation is started.

In this embodiment, the original stored data is cleared before the write operation, and there will be no charging and discharging conflicts during the write operation after the clearing, which reduces the instantaneous power consumption when writing, and improves the reliability of writing into the SRAM storage unit. performance, thereby improving the overall yield of the SRAM memory.

FIG. 4 is a timing diagram of an embodiment of a method for writing an SRAM storage unit according to the present invention. The working process of the embodiment shown in FIG. 2 will be described below in conjunction with FIG. 4 .

Before performing a write operation on the SRAM storage unit shown in FIG. 2 , the SRAM storage unit is first cleared.

The dotted line a in Fig. 4 is in the clearing stage of the SRAM storage unit, and the clearing includes: connecting the first bit line BL and the second bit line Connect to ground level (not shown). Ground the power supply latch of the data latch to the ground level (that is, the V (latch) waveform). Connect the word line WL to a high level (that is, V (WL) waveform).

It can be seen from the figure that the voltages of the first storage node bit and the second storage node bit_ are rapidly dropped to the ground level (that is, V(bit) waveform and V(bit_) waveform), and the original stored data is cleared.

After that, the voltages of the first storage node bit and the second storage node bit_ are maintained at the ground level for a certain period of time, and then enter the writing phase of the SRAM archive unit. Connect the power latch of the data latch to a high level, connect the word line WL to a high level, and connect the first bit line BL and the second bit line Input two voltages, one high and one low, respectively according to the written data (not shown in the figure). Finally, the data to be written is stored in the form of one high and one low voltage at the first storage node bit and the second storage node bit_. The dotted line b in FIG. 4 shows the voltages of the first storage node bit and the second storage node bit_ after writing is completed. As shown in the figure, the voltage of the first storage node bit_ is low, and the voltage of the second storage node bit_ is high.

The present invention also provides an SRAM memory (not shown in the figure), including: the above-mentioned SRAM storage unit.

It should be noted that the present invention can be used in many general-purpose or special-purpose computing system environments or configurations. Examples: personal computers, server computers, handheld or portable devices, tablet-type devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, including Distributed computing environment of any of the above systems or devices, etc.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (9)

1. A kind of SRAM storage unit, is characterized in that, comprises: a data latch including a first storage node and a second storage node storing data inversion; A selection controller, the selection controller is connected to the power supply of the data latch, and is used to control the power supply of the data latch to be connected to the power supply voltage or to the ground level, wherein the connection to the ground level is used for Before the first storage node and the second storage node write data, clear the two storage nodes; a first transmission pipe, the first transmission pipe is located between the first bit line and the first storage node; a second transmission pipe, the second transmission pipe is located between the second bit line and the second storage node; Both the gate of the first transfer transistor and the gate of the second transfer transistor are connected to a word line. 2. The SRAM storage unit according to claim 1, wherein the selection controller is controlled by the write control signal of the SRAM storage unit, so that the power supply of the data latch is controlled by the write control signal It is connected to the ground level before it is valid, and is connected to the power supply voltage when the write control signal is valid. 3. The SRAM storage unit according to claim 1, wherein the selection controller is controlled by a reset control signal; the reset control signal is effective, and the selection controller makes the power supply of the data latch connected to the ground level, the reset control signal is invalid, and the selection controller connects the power supply of the data latch to the power supply voltage. 4. The SRAM storage unit according to claim 1, wherein the SRAM storage unit is a standard 6T storage unit; The data latch includes: a first inverter and a second inverter, the first inverter and the second inverter are cross-coupled; The first inverter includes: a first PMOS transistor and a first NMOS transistor; The second inverter includes: a second PMOS transistor and a second NMOS transistor; The power supply of the data latch includes: the source of the first PMOS transistor and the source of the second PMOS transistor. 5. A method for writing an SRAM storage unit, applicable to the SRAM storage unit according to any one of claims 1 to 4, characterized in that it comprises: Before performing a write operation on the SRAM storage unit, the SRAM storage unit is cleared to discharge the first storage node and the second storage node to ground level. 6. The SRAM storage unit write operation method according to claim 5, wherein said clearing said SRAM storage unit comprises: connecting the first bit line and the second bit line to a ground level; connecting the power supply of the data latch to the ground level; The word line is connected to a supply voltage. 7. The SRAM storage unit write operation method according to claim 5, wherein said writing operation to said SRAM storage unit comprises: connecting the power supply of the data latch to a supply voltage; Loading the first bit line and the second bit line with data to be written. 8. The method for writing an SRAM storage unit according to claim 5, wherein the clearing lasts at least 3 ns. 9. An SRAM memory, characterized by comprising: the SRAM storage unit according to any one of claims 1-4.