CN102687203B - The SRAM delay circuit of trace bit element characteristics - Google Patents

Abstract

A kind of SRAM delay circuit (14) of trace bit element characteristics.Disclosing a kind of circuit, comprising the input node for receiving input signal (13); For catching the reference mode (20) from the reference current of multiple reference unit (12); There is the capacitance network (15) of the electric discharge controlled by described reference current; And exporting the output circuit with the described input signal of delay (16), wherein said delay is by the described control of discharge of described capacitance network (15).

Description

SRAM Delay Circuit Tracking Bit Cell Characteristics

technical field

The present disclosure relates to SRAM devices, and more particularly to SRAM circuits for generating delays that track bitcell characteristics and are independent of any non-cell devices.

Background technique

SRAM (Static Random Access Memory) devices are generally used for static memory storage. Each bit is typically stored in an SRAM memory cell with four transistors. Two additional access transistors are used to control access to the memory cell during read and write operations. Access to a cell is enabled by a word line controlling two access transistors which in turn control whether the cell should be connected to a bit line for transferring data for read and write operations .

One challenge that must be addressed in implementing SRAM is addressing the delay that occurs between (1) the time the word line is turned on and (2) the time data is ready to be read from the bit line using the sense amplifier. Because the delay may be relatively variable based on any number of factors, some type of circuitry for generating the delay is required to inform the sense amplifier when to fire and read the bit line. Current approaches utilize logic devices to generate delays. Unfortunately, logic devices are subject to different processing, voltage, and temperature (PVT) variations than SRAM cell devices. Using logic devices results in sub-optimal performance and is more prone to SRAM cell writeability and stability issues.

Contents of the invention

SRAM circuits are disclosed for generating delays that track bit cell characteristics and are independent of any logic device. In a first aspect, the present invention provides an SRAM device having a delay circuit for tracking the characteristics of an SRAM bit cell, wherein the delay circuit includes: an input node for receiving an input signal; for capturing a reference from a plurality of reference SRAM cells a reference node for a current; a capacitive network having a discharge rate controlled by the reference current; and an output circuit that outputs a delayed signal, wherein the delayed signal is controlled by the discharge rate of the capacitive network.

In a second aspect, the present invention provides a method of generating a delay signal in an SRAM device comprising: providing an SRAM device having a plurality of reference cells coupled to a common reference node, wherein the plurality of reference cells are configured to respond to a word line generating a reference current at the common reference node during a transition; generating a reference current at the common reference node in response to the word line transition; using the reference current to specify a discharge rate to a capacitive network on a discharge line ; activating an output circuit in response to a voltage potential on said discharge line exceeding a threshold voltage; and outputting a delay signal.

In a third aspect, the present invention provides a system for generating a delay signal in an SRAM device, comprising: a plurality of reference cells coupled to a common reference node, wherein the plurality of reference cells are configured to switch between The common reference node generates a reference current, and wherein the reference current comprises an average characteristic of the plurality of reference cells; a circuit that uses the reference current to assign a discharge rate to a capacitive network on a discharge line; responsive to the discharge line an output circuit that is activated when the voltage potential on the above threshold voltage is exceeded; and an output node that outputs a delayed signal in response to activation of a passgate transistor.

In a fourth aspect, the present invention provides an SRAM device having a delay circuit utilizing a virtual ground to track an SRAM bit cell characteristic, wherein the delay circuit includes: an input node for receiving an input signal; for capturing from a plurality of reference SRAM cells a virtual ground node for a reference current; a capacitive network having a pair of capacitors providing a discharge rate controlled by the reference current; and an output current outputting a delayed signal, wherein the delayed signal is controlled by the discharge rate of the capacitive network.

The illustrative aspects of the invention are designed to address the problems described herein and others not discussed.

Description of drawings

These and other features of the present invention will be more easily understood from the following detailed description of various aspects of the present invention in conjunction with the accompanying drawings.

FIG. 1 depicts an SRAM device with a delay circuit according to an embodiment of the present invention.

Figure 2 depicts a delay circuit according to an embodiment of the present invention.

Figure 3 depicts two additional implementations for obtaining a reference current according to an embodiment of the present invention.

Figure 4 depicts a delay circuit according to an embodiment of the present invention.

Figure 5 depicts a delay circuit according to an embodiment of the present invention.

Figure 6 depicts a delay circuit according to an embodiment of the present invention.

Figure 7 depicts a limiter coupled to a delay circuit according to an embodiment of the invention.

FIG. 8 depicts a flowchart showing a method for generating a delayed signal according to an embodiment of the present invention.

The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbers indicate like elements.

Detailed ways

FIG. 1 depicts an SRAM device 10 comprising a delay circuit 14 for generating a delayed signal 16 , which is a delayed version of an input signal 13 . Input signal 13 may, for example, include a clock transition that activates read and/or write operations on SRAM device 10 . The amount of delay in delay signal 16 is based on a reference current i obtained from a set of reference cells 20 (ie, bit cells) in cell array 12 . It should be noted that the reference cell 20 need not be in the functional cell array 12, but may reside elsewhere, such as a small separate reference array. The delay circuit 14 utilizes a capacitive network 15 having one or more capacitors to generate a discharge based on a reference current i. This discharge controls the amount of delay in delay signal 16 .

In this embodiment, the delay signal 16 is provided to the sense amplifier 18 to determine when the bit lines in the cell array 12 should be read/written. However, it should be understood that delay signal 16 may be used for any purpose, such as defining WL (word line) pulse width, BL (bit line) reactivation, etc. Thus, since the reference cell 20 can be implemented simply as an extra set of bit cells in the cell array 12 or as a separate distinct array, this approach extracts SRAM device characteristics to control timing without modifying the device itself. Construct the layout. The set of reference cells 20 may for example comprise 16 or 32 cells, from which the average or reference current i is obtained, thereby statistically eliminating variations in performance between cells. Various implementations and various delay circuits 14 for obtaining the reference current i are described.

FIG. 2 depicts an exemplary embodiment of a delay circuit 50 comprising four components including device tracking bias generator 22 , discharge network 24 , switched capacitor network 26 and threshold compensation circuit 28 . Delay circuit 50 takes reference current 30 from set of reference cells 42 and generates delayed waveform 40 (WL _END ), which is a delayed version of word line or clock signal 36 (CLK, WL _START ). Delayed waveform 40 essentially simulates the behavior of word line WL _START in the device, except for the delay. In reference cell 42, word line VDD _W and bit lines VDD _B1 and bit lines VDD _B2 are all set to VDD and current is drawn from the I _READ node on each cell. To avoid affecting the SRAM characteristics of the reference cell, the signals in the reference cell 42 can be set using existing cell signals common to the reference and functional SRAM cells without additional metal lines or vias. This allows extraction of SRAM device characteristics without modifying the fabric layout of reference SRAM cells.

Device tracking bias generator 22 includes current mirror 32 that receives reference current 30 from reference unit 42 and generates bias 34 . This bias 34 is then fed into discharge network 24 which discharges the bias signal onto discharge line (DL) node 38 in switched capacitor network 26 when clock signal 36 rises. The bias 34 determines the discharge rate for the DL node 38 through the discharge network 24 .

Threshold compensation circuit 28 operates by charging DL node 38 to the threshold of inverter 46 and self-calibrating when CLK 36 is low to counteract any threshold variations introduced by device mismatch and PVT. When CLK 36 is high, charging of DL node 38 stops, and threshold compensation circuit 28 generates a rising edge when the DL voltage discharges across the threshold of inverter 46 .

When CLK 36 transitions high, switched capacitor network 26 generates a logic-device-independent voltage increment on DL node 38 based on the DL precharge voltage generated while CLK 36 is low and the ratio of Cboost to Csignal. In effect, the switched capacitor network boosts the voltage on the DL line from the threshold voltage of the inverter 46 to a voltage higher than the threshold of the inverter 46 at a ratio between Cboost and Csignal.

The voltage increase on DL node 38 is then discharged through discharge network 24 and threshold gate 44 is opened when the voltage increase becomes high enough to exceed the voltage threshold of inverter 46 . The threshold gate 44 and inverter 46 ensure that the delay signal 40 (WL _END ) is virtually PVT independent with low sensitivity to random device variations (ie self-calibration as described above). Thus, the delay is primarily a function of the DL voltage generated by the boost, the capacitance on the DL node 38 and the reference current discharging the DL node 38 .

In the embodiment of Fig. 2, the transfer gate (PG) configuration is used to obtain the reference current, ie the current is drawn from the transfer gate transistor in each cell. More specifically, this configuration uses current-drain through a pull-down (PD) FET and a pass-gate (PG) FET (with the PGFET acting as a current limiter). Figure 3 depicts two alternative implementations 52, 54 for obtaining a reference current from a set of reference cells and supplying this current to a bias generator. In embodiment 52, a pull-up (PU) configuration is used by connecting the cell signal 56 to provide the drain current through the pull-up (PU) FET and the PGFET (with the PUFET acting as a current limiter). In embodiment 54, the pull-down configuration is achieved by connecting the cell signal 58 to provide current draw through the PD and the PGFET, where the PGFET is gated with a much higher voltage to make the PDFET a current limiter.

It should be noted that in each of these embodiments, a bias generator with a current mirror is utilized to generate the bias signal. However, as described herein, the bias generator/current mirror can be omitted.

Note also that the current mirrors in each of the illustrated bias generator embodiments can be implemented in many different ways, eg, cascaded, etc., and can be powered down when not in use. In addition, the bias generator can be used to control other SRAM auxiliary functions, such as write assist, read assist, and so on.

FIG. 4 depicts an alternative implementation 60 of a delay circuit. In this embodiment, two bias generators, PU-BIAS generator 62 and PG-BIAS generator 64, are used. The discharge network 66 is changed from the Figure 2 embodiment in order to allow proper modeling of write operations, where the PU-BIAS generator 62 controls the pull-up characteristics. AND gate 72 is used to limit the pull-up bias to write operations only. For read operations, the PG-BIAS generator 64 is used. Switched capacitor network 68 and threshold compensation circuit 70 are the same as described in FIG. 2 .

FIG. 5 depicts another embodiment 80 of a delay circuit. In this embodiment, the reference current 82 (I _Read ) flows from the pull-down (PD) FET and transfer gate (PG) FET as in FIG. 2 . However, current 82 is fed directly into delay circuit 80 as a virtual ground (V_VSS). Thus, V_VSS constitutes the power supply through which the PD/PGFET of the SRAM cell is fully discharged, thereby controlling the discharge rate of the two Csignal capacitors and thus controlling the delayed output.

FIG. 6 depicts yet another embodiment 90 of a delay circuit. This implementation is similar to that shown in Figure 2, except that the bias generator/current mirror and discharge network are effectively eliminated. Instead, the reference current 92 is directly connected to the DL node, while the clock signal (CLK) acts as the word line 94 for the reference cell.

FIG. 7 depicts a system in which a SRAM-based delay circuit 100 (as described herein) is coupled (i.e., ANDed) with a limiter 102 to set the amount of delay to be no less than the minimum pulse width (PW ). The limiter 102 may consist of, for example, a logic device that sets the minimum delay at the high voltage corner of the device.

Figure 8 depicts a flowchart of a method for implementing an embodiment of the present invention. At S1, the SRAM device is configured with a bank (ie, a plurality) of reference cells, where the reference cells are coupled to a common reference node in order to provide a reference current. At S2, a reference current is generated in response to a word line transition. At S3, this reference current is used to specify the discharge rate from the capacitive network to the discharge line. At S4, when the discharge amount exceeds the threshold voltage, the transfer gate transistor is activated. Finally, at S5, a delayed signal is generated in response to the activation of the transfer gate transistor.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will recognize that any arrangement that is believed to achieve the same purpose may be substituted for the specific embodiments shown and that the invention has the advantages described herein. other applications in other environments. This application is intended to cover any adaptations or variations of the present invention. The following claims are in no way intended to limit the scope of the invention to the specific embodiments described herein.

Claims (25)

1. A SRAM device having a delay circuit for tracking SRAM bit cell characteristics, wherein the delay circuit comprises: an input node for receiving an input signal; a reference node for capturing reference currents from multiple reference cells; having a discharge rate of a capacitive network on the discharge line controlled by said reference current; and An output circuit that outputs a delayed signal, wherein the delayed signal is controlled by said discharge rate of said capacitive network, said delayed signal being a delayed version of an input signal. 2. The SRAM device of claim 1, wherein the input signal comprises a clock transition. 3. The SRAM device of claim 1, wherein the reference current is captured from the plurality of reference cells using a configuration selected from the group consisting of: a transfer gate configuration; a pull-up configuration; and a pull-down configuration. 4. The SRAM device of claim 1, wherein the reference current is input into a bias generator having a current mirror. 5. The SRAM device of claim 4, wherein the bias generator outputs a bias to a discharge network coupled to the capacitive network, wherein the bias specifies a discharge rate of the capacitive network. 6. The SRAM device of claim 1 , wherein the capacitive network includes a boost capacitor and a signal capacitor, and generates a logic-independent voltage on a discharge line based on a ratio of the boost capacitor and the signal capacitor increment. 7. The SRAM device of claim 1, wherein the output circuit includes a transfer gate transistor that turns on in response to a voltage threshold being exceeded on the discharge line. 8. The SRAM device of claim 1, wherein the capacitive network has capacitor pairs, and the reference current is used as a virtual ground to control discharge of the capacitor pairs. 9. The SRAM device of claim 1, wherein the reference current is supplied to a pull-up bias generator for controlling a write operation and a transfer gate bias generator for controlling a read operation. 10. The SRAM device of claim 1, wherein the reference current is provided directly to a discharge line in a capacitive network. 11. A method of generating a delayed signal in an SRAM device, comprising: providing an SRAM device having a plurality of reference cells coupled to a common reference node, wherein the plurality of reference cells are configured to generate a reference current at the common reference node in response to a word line transition; generating the reference current at the common reference node in response to the word line transition; using said reference current to specify a discharge rate to a capacitive network on a discharge line; activating an output circuit in response to a voltage potential on the discharge line exceeding a threshold voltage; and A delayed signal is output that is a delayed version of the input signal. 12. The method of claim 11, further comprising capturing the reference current from the plurality of reference cells using a configuration selected from: a transfer gate configuration; a pull-up configuration; and a pull-down configuration. 13. The method of claim 11, further comprising inputting the reference current into a bias generator having a current mirror. 14. The method of claim 13, further comprising powering on and off the current mirror as needed to generate the delayed signal. 15. The method of claim 11, wherein the capacitive network includes a boost capacitor and a signal capacitor, and generates a logic-independent voltage increment. 16. The method of claim 11, the capacitive network having capacitor pairs, the method further comprising using the reference current as a virtual ground to control discharge of the capacitor pairs. 17. The method of claim 11, further comprising providing the reference current to a pull-up bias generator for controlling write operations and a transfer gate bias generator for controlling read operations. 18. The method of claim 11, further comprising providing said reference current directly to said discharge line in said capacitive network. 19. A system for generating a delayed signal in an SRAM device, the delayed signal being a delayed version of an input signal, comprising: a plurality of reference cells coupled to a common reference node, wherein the plurality of reference cells are configured to generate a reference current at the common reference node in response to a word line transition, wherein the reference current comprises the Average properties; a circuit that uses said reference current to assign a discharge rate to a capacitive network on a discharge line; a transfer gate transistor activated in response to a discharge on said discharge line exceeding a threshold voltage; and An output circuit activated in response to the voltage potential on the discharge line exceeding a threshold voltage. 20. The system of claim 19, wherein the reference current is captured from the plurality of reference cells using a configuration selected from the group consisting of: a transfer gate configuration; a pull-up configuration; and a pull-down configuration. 21. The system of claim 19, further comprising a bias generator that converts the reference current into a bias using a current mirror. 22. The system of claim 19, wherein the output circuit includes a threshold compensation circuit. 23. The system of claim 22, wherein the threshold compensation circuit references a discharge line boost from the capacitive network to a threshold that reduces pressure voltage and temperature PVT characteristics. 24. The system of claim 19, wherein the plurality of reference cells are substantially identical in architectural layout to a set of functional cells on the SRAM device. 25. A SRAM device having a delay circuit utilizing a virtual ground to track SRAM bit cell characteristics, wherein the delay circuit comprises: an input node for receiving an input signal; Virtual ground node for capturing reference current from multiple reference SRAM cells; a capacitive network having a pair of capacitors providing a discharge rate controlled by said reference current; and An output circuit that outputs a delayed signal, wherein the delayed signal is controlled by the discharge rate of the capacitive network, the delayed signal being a delayed version of the input signal.