CN105551987A - COF (Chip on Flex) packaging method - Google Patents
COF (Chip on Flex) packaging method Download PDFInfo
- Publication number
- CN105551987A CN105551987A CN201510908404.5A CN201510908404A CN105551987A CN 105551987 A CN105551987 A CN 105551987A CN 201510908404 A CN201510908404 A CN 201510908404A CN 105551987 A CN105551987 A CN 105551987A
- Authority
- CN
- China
- Prior art keywords
- salient point
- chip
- cof
- conductive post
- metal salient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000004033 plastic Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000012856 packing Methods 0.000 claims description 22
- 239000000945 filler Substances 0.000 claims description 10
- 238000003825 pressing Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract 3
- 229920005989 resin Polymers 0.000 abstract 3
- NMWSKOLWZZWHPL-UHFFFAOYSA-N 3-chlorobiphenyl Chemical compound ClC1=CC=CC(C=2C=CC=CC=2)=C1 NMWSKOLWZZWHPL-UHFFFAOYSA-N 0.000 description 7
- 101001082832 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) Pyruvate carboxylase 2 Proteins 0.000 description 7
- 230000005611 electricity Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8102—Applying permanent coating to the bump connector in the bonding apparatus, e.g. in-situ coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The invention provides a COF (Chip on Flex) packaging method based on anisotropic conducting resin. The method comprises the steps: providing a to-be-packaged chip; providing a to-be-packaged flexible circuit board, and forming a plurality of first metal convex points on a flexible circuit metal layer; coating the first metal convex points with the conducting resin; enabling the plurality of first metal convex points to be oppositely corresponding to function regions of the chip, and to be connected through anisotropic conducting resin columns; arranging plastic packaging bottom filling materials between the chip and the flexible circuit board, and forming a plastic packaging body. The method provided by the invention can solve problems that the heights of convex points in a conventional structure are difficult to control and a preparation method is more difficult, can reduce the cost, and improves the packaging efficiency.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, particularly relate to one and cover brilliant film (COF) method for packing, particularly one covers brilliant film (COF) method for packing.
Background technology
Along with the development of integrated circuit technique, electronic product is more and more to miniaturized, intelligent and high reliability future development, and integrated antenna package directly affects integrated circuit, electronic module and even overall performance, progressively reduce in integrated circuit (IC) wafer size, integrated level is when improving constantly, electronics industry terminates to propose more and more higher requirement to integrated antenna package.
Current chip is by the upside-down mounting of end embankment formula as on the flexible PCB (film) of carrier, and chip is connected by metal column with the metal level that film covers, and is electrically connected with the external world.The method flow typically covering brilliant film (COF) comprises: the glue-free FCCL of casting legal system, making fine-line, coating solder mask, pad plating Ni/Au, IC are installed, step such as passive device welding (Reflow Soldering), LCD installation etc.
But in the above-mentioned methods, when chip is prepared higher salient point (bump), there is the problem that some affect chip manufacturing yield:
(1) salient point (bump) of the Altitude control IC beneath chips of salient point (bump) is difficult to control that it is highly completely the same, is uneven and easily makes chip failure;
(2) on film, salient point (bump) its preparation method is produced more difficult.
Summary of the invention
In view of above-mentioned defect of the prior art or deficiency, the invention provides one and cover brilliant film (COF) method for packing.
The invention provides one and cover brilliant film (COF) method for packing, comprising:
One chip to be packaged is provided;
One flexible PCB to be packaged is provided, and forms multiple first metal salient point on described flexible PCB metal level;
Described first metal salient point coats aeolotropic conductive post;
Described multiple first metal salient point is also connected by described aeolotropic conductive post with described chip functions district is corresponding in opposite directions;
Between described chip and described flexible PCB with plastic packaging at the bottom of filler fill and form plastic-sealed body.
Compared with prior art, provided by the inventionly cover brilliant film (COF) method for packing, existing structure bumps height can be solved and be difficult to control and the more difficult problem of its preparation method, can reduce costs again, improve packaging efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the method flow diagram covering a kind of embodiment of brilliant film (COF) method for packing provided by the invention;
The structural representation covering a kind of embodiment of brilliant film (COF) method for packing that Fig. 2-Fig. 6 provides for Fig. 1.
Fig. 7 is the method flow diagram covering the another kind of embodiment of brilliant film (COF) method for packing provided by the invention;
The structural representation covering the another kind of embodiment of brilliant film (COF) method for packing that Fig. 8-Figure 12 provides for Fig. 7.
Reference numeral:
1-chip; 2-flexible PCB; 3-metal level; 4-conducting resinl post;
5-first metal salient point; 6-second metal salient point; 7-pad; 8-plastic-sealed body.
Embodiment
Below in conjunction with drawings and Examples, the application is described in further detail.Be understandable that, specific embodiment described herein is only for explaining related invention, but not the restriction to this invention.It also should be noted that, for convenience of description, illustrate only in accompanying drawing and invent relevant part.
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
First embodiment:
As Fig. 1, present embodiments provide one and cover brilliant film (COF) method for packing, comprising:
S10 a: chip to be packaged is provided;
S20 a: flexible PCB to be packaged is provided, and on flexible PCB metal level, form multiple first metal salient point;
S30: coat aeolotropic conductive post on the first metal salient point;
S40: multiple first metal salient point and chip functions district is corresponding in opposite directions and be connected by aeolotropic conductive post;
S50: fill with filler at the bottom of plastic packaging between chip and flexible PCB and form plastic-sealed body.
First, perform step S10, as shown in Figure 2, provide a chip 1 to be packaged;
Perform step S20, as shown in Figure 3, provide a flexible PCB 2 to be packaged, and on flexible PCB 2 metal level 3, form multiple first metal salient point 5;
Perform step S30, as Fig. 4, the first metal salient point 5 coats aeolotropic conductive post 4.Because aeolotropic conductive (ACF) can only conduct electricity in vertical direction, and can not conduct electricity in a parallel direction, prevent generation between the first metal salient point conduct electricity and cause the danger of chip short circuit.
Perform step S40, as Fig. 5, multiple first metal salient point 5 and chip 1 functional areas are corresponding in opposite directions and be connected by aeolotropic conductive post 4;
Preferably, as Fig. 5, the first metal salient point 5 that the present embodiment provides and the cylindrical body of aeolotropic conductive post 4.Convenient docking, also facilitates subsequent step chips and flexible PCB to the pressing of aeolotropic conductive post simultaneously.
Preferably, as Fig. 5, the first metal salient point 5 that the present embodiment provides and the axis of aeolotropic conductive post 4 are point-blank.
Preferably, as Fig. 5, the circular section diameter of the aeolotropic conductive post 4 that the present embodiment provides is greater than the first metal salient point 5 circular section diameter.
Perform step S50, as Fig. 6, between chip 1 and flexible PCB 2 with plastic packaging at the bottom of filler fill and form plastic-sealed body 8.
Preferably, before execution step S50, pressing chip 1 and flexible PCB 2, make the first metal salient point 5 and chip 1 pair of aeolotropic conductive post 4 apply the pressure of a vertical direction.Aeolotropic conductive post glue post is solidified, and the transmission signal of telecommunication can be carried out preferably in vertical direction.
Second embodiment
As Fig. 7, present embodiments provide another kind and cover brilliant film (COF) method for packing, comprising:
S100 a: chip to be packaged is provided, and on chip, form multiple second metal salient point;
S200 a: flexible PCB to be packaged is provided, and forms multiple pad on flexible PCB metal level;
S300: coat aeolotropic conductive post on the second metal salient point or pad;
S400: multiple second metal salient point and pad is corresponding in opposite directions one by one and be connected by aeolotropic conductive post;
S500: fill with filler at the bottom of plastic packaging between chip and flexible PCB and form plastic-sealed body.
First, perform step S100, as shown in Figure 8, provide a chip 1 to be packaged, and on chip 1, form multiple second metal salient point 6;
Perform step S200, as shown in Figure 9, a flexible PCB 2 to be packaged is provided, and forms multiple pad 7 on flexible PCB 2 metal level 3;
Perform step S300, the second metal salient point 6 or described pad 7 coat aeolotropic conductive post 4; As shown in Figure 10, in the present embodiment, the second metal salient point 6 coats aeolotropic conductive post 4.
Perform step S400, as shown in figure 11, multiple second metal salient point 6 and pad 7 is corresponding in opposite directions one by one and be connected by aeolotropic conductive post 4;
Preferably, as shown in figure 11, the second metal salient point 6 provided as figure the present embodiment and aeolotropic conductive post 4 are cylindrical, and the circular section diameter of aeolotropic conductive post 4 is greater than the circular section diameter of the second metal salient point 6.
Perform step S500, as shown in figure 12, between chip 1 and flexible PCB 2 with plastic packaging at the bottom of filler fill and form plastic-sealed body 8.
Preferably, as shown in figure 12, coated second metal salient point 5 of plastic-sealed body, pad 7 and the aeolotropic conductive post 4 that provide of the present embodiment.Coated by plastic-sealed body, make the second metal salient point, pad and conducting resinl rod structure stable, damp proof, moistureproof.
Preferably, the material of plastic-sealed body filler that the present embodiment provides is epoxy resin.The sealing property of this material is better, plastic packaging easy, is the preferred materials forming plastic-sealed body.
More than describe and be only the preferred embodiment of the application and the explanation to institute's application technology principle.Those skilled in the art are to be understood that, invention scope involved in the application, be not limited to the technical scheme of the particular combination of above-mentioned technical characteristic, also should be encompassed in when not departing from described inventive concept, other technical scheme of being carried out combination in any by above-mentioned technical characteristic or its equivalent feature and being formed simultaneously.The technical characteristic that such as, disclosed in above-mentioned feature and the application (but being not limited to) has similar functions is replaced mutually and the technical scheme formed.
Claims (10)
1. cover a method for packing of brilliant film (COF), it is characterized in that, comprising:
One chip to be packaged is provided;
One flexible PCB to be packaged is provided, and on the metal level of described flexible PCB, forms multiple first metal salient point;
Described first metal salient point coats aeolotropic conductive post;
Described multiple first metal salient point is also connected by described aeolotropic conductive post with the functional areas of described chip to be packaged are corresponding in opposite directions;
Between described chip and described flexible PCB with plastic packaging at the bottom of filler fill and form plastic-sealed body.
2. the method for packing covering brilliant film (COF) according to claim 1, it is characterized in that, also comprise chip described in pressing and described flexible PCB, make the functional areas of described first metal salient point and described chip apply the pressure of a vertical direction to described aeolotropic conductive post.
3. the method for packing covering brilliant film (COF) according to claim 1, is characterized in that, described aeolotropic conductive post and the first metal salient point are cylindrical.
4. the method for packing covering brilliant film (COF) according to claim 3, is characterized in that, described aeolotropic conductive post and the first metal salient point axis are on same straight line.
5. the method for packing covering brilliant film (COF) according to claim 4, is characterized in that, the diameter of section of described aeolotropic conductive post is greater than the diameter of section of described first metal salient point.
6. cover a method for packing of brilliant film (COF), it is characterized in that, comprising:
One chip to be packaged is provided, and forms multiple second metal salient point on the chip;
One flexible PCB to be packaged is provided, and on the metal level of described flexible PCB, forms multiple pad;
Described second metal salient point or described pad coat aeolotropic conductive post;
Also be connected corresponding in opposite directions one by one to described multiple second metal salient point and described pad by described aeolotropic conductive post;
Between described chip and described flexible PCB with plastic packaging at the bottom of filler fill and form plastic-sealed body.
7. the method for packing covering brilliant film (COF) according to claim 6, it is characterized in that, also comprise chip described in pressing and described flexible PCB, make described second metal salient point and described pad apply the pressure of a vertical direction to described aeolotropic conductive post.
8. the method for packing covering brilliant film (COF) according to claim 6, it is characterized in that, described second metal salient point and described aeolotropic conductive post are cylindrical, and the circular section diameter of described aeolotropic conductive post is greater than the circular section diameter of described second metal salient point.
9. the method for packing covering brilliant film (COF) according to claim 6, is characterized in that, coated described first metal salient point of described plastic-sealed body filler, described pad and described aeolotropic conductive post.
10., according to the arbitrary described method for packing covering brilliant film (COF) of claim 6-9, it is characterized in that, the material of described plastic-sealed body filler is epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510908404.5A CN105551987A (en) | 2015-12-09 | 2015-12-09 | COF (Chip on Flex) packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510908404.5A CN105551987A (en) | 2015-12-09 | 2015-12-09 | COF (Chip on Flex) packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105551987A true CN105551987A (en) | 2016-05-04 |
Family
ID=55831096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510908404.5A Pending CN105551987A (en) | 2015-12-09 | 2015-12-09 | COF (Chip on Flex) packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105551987A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115050658A (en) * | 2022-04-25 | 2022-09-13 | 厦门通富微电子有限公司 | Chip on film packaging method and chip on film |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09266227A (en) * | 1996-03-28 | 1997-10-07 | Matsushita Electric Ind Co Ltd | How to join electronic components |
| JPH10340906A (en) * | 1997-06-06 | 1998-12-22 | Sony Corp | Surface-mount electronic part, manufacture and mounting thereof |
| JP2001015550A (en) * | 1999-04-28 | 2001-01-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2001044606A (en) * | 1999-08-02 | 2001-02-16 | Hitachi Ltd | Semiconductor package mounting structure, mounting method thereof, and rework method thereof |
| WO2001033623A1 (en) * | 1999-10-29 | 2001-05-10 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| US20020098620A1 (en) * | 2001-01-24 | 2002-07-25 | Yi-Chuan Ding | Chip scale package and manufacturing method thereof |
| CN1763937A (en) * | 2004-10-19 | 2006-04-26 | 宏齐科技股份有限公司 | Wafer-level optoelectronic semiconductor assembly structure and manufacturing method thereof |
| CN1828854A (en) * | 2005-01-26 | 2006-09-06 | 宏齐科技股份有限公司 | Manufacturing method of wafer-level optoelectronic semiconductor assembly structure |
| JP2009099669A (en) * | 2007-10-15 | 2009-05-07 | Nec Corp | Mounting structure of electronic component, and mounting method thereof |
| US20130065361A1 (en) * | 2011-09-14 | 2013-03-14 | Chipmos Technologies Inc. | Chip package structure and method for manufacturing the same |
| CN103151323A (en) * | 2011-12-06 | 2013-06-12 | 北京大学深圳研究生院 | Flip packaging structure based on anisotropy conductive glue |
-
2015
- 2015-12-09 CN CN201510908404.5A patent/CN105551987A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09266227A (en) * | 1996-03-28 | 1997-10-07 | Matsushita Electric Ind Co Ltd | How to join electronic components |
| JPH10340906A (en) * | 1997-06-06 | 1998-12-22 | Sony Corp | Surface-mount electronic part, manufacture and mounting thereof |
| JP2001015550A (en) * | 1999-04-28 | 2001-01-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2001044606A (en) * | 1999-08-02 | 2001-02-16 | Hitachi Ltd | Semiconductor package mounting structure, mounting method thereof, and rework method thereof |
| WO2001033623A1 (en) * | 1999-10-29 | 2001-05-10 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| US20020098620A1 (en) * | 2001-01-24 | 2002-07-25 | Yi-Chuan Ding | Chip scale package and manufacturing method thereof |
| CN1763937A (en) * | 2004-10-19 | 2006-04-26 | 宏齐科技股份有限公司 | Wafer-level optoelectronic semiconductor assembly structure and manufacturing method thereof |
| CN1828854A (en) * | 2005-01-26 | 2006-09-06 | 宏齐科技股份有限公司 | Manufacturing method of wafer-level optoelectronic semiconductor assembly structure |
| JP2009099669A (en) * | 2007-10-15 | 2009-05-07 | Nec Corp | Mounting structure of electronic component, and mounting method thereof |
| US20130065361A1 (en) * | 2011-09-14 | 2013-03-14 | Chipmos Technologies Inc. | Chip package structure and method for manufacturing the same |
| CN103151323A (en) * | 2011-12-06 | 2013-06-12 | 北京大学深圳研究生院 | Flip packaging structure based on anisotropy conductive glue |
Non-Patent Citations (4)
| Title |
|---|
| Y.C. CHAN，D.Y. LUK: "Effects of bonding parameters on the reliability performance of anisotropic conductive adhesive interconnects for flip-chip-on-flex packages assembly I. Different bonding temperature", 《MICROELECTRONICS RELIABILITY》 * |
| 张军，陈旭: "各向异性导电胶粘接可靠性研究进展", 《电子元件与材料》 * |
| 李慧: "各向异性导电胶膜的导电粒子电性能研究", 《郑州大学学报(工学版)》 * |
| 王天曦，王豫明: "《现代电子工艺》", 30 November 2009 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115050658A (en) * | 2022-04-25 | 2022-09-13 | 厦门通富微电子有限公司 | Chip on film packaging method and chip on film |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102867800B (en) | Functional chip is connected to packaging part to form package on package | |
| US7791211B2 (en) | Flip chip package structure and carrier thereof | |
| US8241968B2 (en) | Printed circuit board (PCB) including a wire pattern, semiconductor package including the PCB, electrical and electronic apparatus including the semiconductor package, method of fabricating the PCB, and method of fabricating the semiconductor package | |
| JP4423285B2 (en) | Electronic component built-in substrate and method for manufacturing electronic component built-in substrate | |
| US12300638B2 (en) | Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures | |
| KR20090040841A (en) | Wiring board, manufacturing method thereof, and semiconductor device | |
| US20090310322A1 (en) | Semiconductor Package | |
| US7554197B2 (en) | High frequency IC package and method for fabricating the same | |
| CN107154385A (en) | Stacked package structure and manufacturing method thereof | |
| CN107342237B (en) | Method of manufacturing semiconductor package and method of manufacturing PoP semiconductor device | |
| US20130334684A1 (en) | Substrate structure and package structure | |
| KR20080054347A (en) | Semiconductor device and manufacturing method thereof | |
| CN103311207A (en) | Stacked package structure | |
| KR100800475B1 (en) | Multilayer semiconductor package and manufacturing method thereof | |
| US20190112185A1 (en) | Reducing vibration of a mems installation on a printed circuit board | |
| CN105551986A (en) | COF (Chip on Flex) packaging method | |
| CN103281858A (en) | Printed circuit board and manufacturing method thereof, and flip-chip packaging member and manufacturing method thereof | |
| CN105551987A (en) | COF (Chip on Flex) packaging method | |
| US20120002386A1 (en) | Method and Apparatus for Improving the Reliability of Solder Joints | |
| CN1949487A (en) | Flip-Chip-on-Film package structure that prevents sealing material from overflowing | |
| US8975758B2 (en) | Semiconductor package having interposer with openings containing conductive layer | |
| CN105405825A (en) | Chip on film package structure | |
| KR102026227B1 (en) | Package on package type semiconductor package and manufacturing method thereof | |
| JP2010080732A (en) | Semiconductor module and method of manufacturing the same | |
| JP4963890B2 (en) | Resin-sealed circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
| COR | Change of bibliographic data | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160504 |