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CN107154385A - Stacked package structure and manufacturing method thereof - Google Patents

Stacked package structure and manufacturing method thereof Download PDF

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Publication number
CN107154385A
CN107154385A CN201610128525.2A CN201610128525A CN107154385A CN 107154385 A CN107154385 A CN 107154385A CN 201610128525 A CN201610128525 A CN 201610128525A CN 107154385 A CN107154385 A CN 107154385A
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Prior art keywords
component
package
glue injection
substrate
package structure
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CN201610128525.2A
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Chinese (zh)
Inventor
杨俊�
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Shunsin Technology Zhongshan Ltd
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Shunsin Technology Zhongshan Ltd
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Priority to CN201610128525.2A priority Critical patent/CN107154385A/en
Publication of CN107154385A publication Critical patent/CN107154385A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

The invention discloses a stacked package structure and a manufacturing method thereof. The package on package structure includes a first package body and a second package body. The first packaging body comprises a substrate, a first component arranged on the substrate, a first injection molding body for coating the first component and a first packaging circuit. The second packaging body comprises a second component and a second injection body wrapping the second component. The second packaging body is attached to the first packaging body through the joint of the second glue injection body and the first glue injection body. The first packaging circuit and the second component are electrically connected through the conductive filling holes arranged on the first glue injection body and/or the second glue injection body. The invention discloses a stacked packaging structure and a manufacturing method thereof, aiming at reducing the thickness of the stacked packaging structure, simplifying the manufacturing process and reducing the processing cost.

Description

堆叠封装结构及其制造方法Stacked package structure and manufacturing method thereof

技术领域technical field

本发明涉及半导体器件封装技术领域，尤其是涉及一种堆叠封装结构及其制造方法。The invention relates to the technical field of semiconductor device packaging, in particular to a stacked packaging structure and a manufacturing method thereof.

背景技术Background technique

电子设备中电子元件的传统封装形式，一般是将多个独立封装的元件焊接到一个印刷电路板上，电子元件之间通过导线连接起来，以实现完整的功能。多个独立封装的电子元件布置在一个印刷电路板(Printed Circuit Board,PCB)上，需占用较大面积，而较大面积的PCB会增大电子设备的尺寸、提高制造成本。为使PCB上容纳更多电子元件、使电子设备具有较小的PCB却具备更多的功能，出现了堆叠封装技术。The traditional packaging form of electronic components in electronic equipment is generally to solder multiple independently packaged components to a printed circuit board, and the electronic components are connected by wires to achieve complete functions. A plurality of independently packaged electronic components are arranged on a printed circuit board (Printed Circuit Board, PCB), which needs to occupy a large area, and a PCB with a large area will increase the size of the electronic device and increase the manufacturing cost. In order to accommodate more electronic components on the PCB and enable electronic devices to have smaller PCBs but have more functions, stacked packaging technology has emerged.

现有的堆叠封装结构包括至少两个封装件，以两个为例，记为第一封装件和第二封装件，第一封装件和第二封装件分别制作好后﹐再做堆叠。然而，现有的堆叠封装结构及其制造方法主要有两个缺点：1、封装件直接堆叠﹐造成堆叠封装结构比较厚﹐不能适应电子产品轻薄化的要求；2、第一封装件和第二封装件分别制作好后﹐再做堆叠﹐工艺复杂﹐制造成本高。The existing package-on-package structure includes at least two packages, taking two as an example, which are denoted as a first package and a second package. After the first package and the second package are manufactured respectively, they are stacked. However, the existing stacked package structure and its manufacturing method mainly have two disadvantages: 1. The packages are directly stacked, resulting in a relatively thick stacked package structure, which cannot meet the requirements of light and thin electronic products; 2. The first package and the second package After the packages are fabricated separately, they are then stacked, which is complicated in process and high in manufacturing cost.

发明内容Contents of the invention

鉴于现有技术中存在的上述问题，本发明公开了一种堆叠封装结构及其制造方法，旨在减小堆叠封装结构的厚度、简化制作工艺、降低加工成本。In view of the above-mentioned problems in the prior art, the present invention discloses a package-on-package structure and a manufacturing method thereof, aiming at reducing the thickness of the package-on-package structure, simplifying the manufacturing process, and reducing processing costs.

本发明的技术方案如下：Technical scheme of the present invention is as follows:

一种堆叠封装结构，包括：A package-on-package structure, comprising:

第一封装体，其包括基板、安装于所述基板上的第一元器件、包覆所述第一元器件的第一注胶体、设于所述第一注胶体内并与所述第一元器件电连接的第一封装线路；The first package, which includes a substrate, a first component mounted on the substrate, a first injection body covering the first component, disposed in the first injection body and connected to the first The first packaging line electrically connected to the components;

第二封装体，其包括第二元器件、包覆所述第二元器件的第二注胶体；A second package, which includes a second component and a second glue that covers the second component;

所述第二封装体通过第二注胶体与所述第一注胶体的接合附着在所述第一封装体上，所述第一封装线路和第二元器件通过设于第一注胶体和/或第二注胶体上的导电填充孔电连接。The second package is attached to the first package through the joint of the second glue and the first glue, and the first package circuit and the second component are arranged on the first glue and/or Or the conductive filling hole on the second injection gel is electrically connected.

作为优选，所述基板上设有第一焊垫，所述第一元器件与所述第一焊垫电性连接；所述第一注胶体与第二注胶体接合的位置设有第二焊垫，所述第二元器件与所述第二焊垫电性连接；所述导电填充孔电性连接于所述第一焊垫与第二焊垫之间。Preferably, a first welding pad is provided on the substrate, and the first component is electrically connected to the first welding pad; pad, the second component is electrically connected to the second pad; the conductive filling hole is electrically connected between the first pad and the second pad.

作为优选，所述基板上设有用于与外部元件电性连接的第一锡球，所述第二元器件与所述第二焊垫通过第二锡球电性连接。Preferably, first solder balls for electrically connecting with external components are provided on the substrate, and the second components are electrically connected with the second pads through second solder balls.

作为优选，所述导电填充孔包括通孔本体及设于该通孔本体内的导电物质。Preferably, the conductive filling hole includes a through-hole body and a conductive substance disposed in the through-hole body.

进一步的，所述导电物质为填充于所述通孔本体内的导电糊或镀附于所述通孔本体内壁上的导电膜。Further, the conductive substance is a conductive paste filled in the through-hole body or a conductive film plated on the inner wall of the through-hole body.

作为优选，本发明的堆叠封装结构还包括附着于所述第二封装体上的至少一层第三封装体；所述第三封装体与所述第二封装体结构相同，并通过与所述第二封装体相同的附着方式与该第三封装体相邻的第二封装体或第三封装体接合并电连接。Preferably, the package-on-package structure of the present invention further includes at least one layer of third package attached to the second package; the third package has the same structure as the second package, and through the The second package body is bonded and electrically connected to the second package body or the third package body adjacent to the third package body in the same attachment manner.

作为优选，所述第一元器件、第二元器件为裸芯片、无源器件、封装芯片中的一种或多种。Preferably, the first component and the second component are one or more of a bare chip, a passive device, and a packaged chip.

本发明还公开了一种堆叠封装结构的制造方法，包括步骤：The invention also discloses a method for manufacturing a package-on-package structure, comprising the steps of:

S1、提供一基板，在基板安装第一元器件，并注胶形成包覆该第一元器件的第一注胶体；S1. Provide a substrate, install a first component on the substrate, and inject glue to form a first injection body covering the first component;

S2、在所述第一注胶体的预定位置开设导电填充孔；S2. Opening a conductive filling hole at a predetermined position of the first gel injection;

S3、在所述第一注胶体上蚀刻、电镀形成连接所述第一元器件及所述导电填充孔的第一封装线路；S3. Etching and electroplating on the first glue injection body to form a first package circuit connecting the first component and the conductive filling hole;

S4、在所述第一注胶体上安装第二元器件，将第二元器件与所述导电填充孔电连接，并注胶形成包覆该第二元器件的第二注胶体。S4. Installing a second component on the first glue, electrically connecting the second component to the conductive filling hole, and injecting glue to form a second glue covering the second component.

作为优选，所述步骤S1中还包括在所述基板上设置第一焊垫的步骤，所述第一元器件通过所述第一焊垫安装在基板上；所述步骤S4中还包括在所述第一注胶体上形成与所述导电填充孔连接的第二焊垫的步骤，所述第二元器件通过所述第二焊垫安装固定。Preferably, the step S1 further includes the step of setting a first pad on the substrate, and the first component is mounted on the substrate through the first pad; the step S4 also includes the step of The step of forming a second welding pad connected to the conductive filling hole on the first glue injection body, and the second component is installed and fixed through the second welding pad.

作为优选，还包括步骤Preferably, it also includes the step

S5、通过植球工艺在所述基板上形成用于与外部元件电性连接的第一锡球。S5. Forming first solder balls on the substrate through a ball planting process for electrically connecting with external components.

本发明公开的堆叠封装结构及其制造方法中，堆叠封装结构只需在第一封装体设置基板，堆叠在第一封装体上的第二封装体，或更多的第三封装体均可直接接合在与之相邻的封装体上，可省略单独封装用的基板和焊接部件，从而减小堆叠封装结构的厚度，也简化了制造工艺、降低了加工成本。In the package-on-package structure disclosed in the present invention and its manufacturing method, the package-on-package structure only needs to provide a substrate on the first package, and the second package or more third packages stacked on the first package can be directly Bonding on the adjacent package body can omit the substrate and soldering parts for individual packaging, thereby reducing the thickness of the stacked package structure, simplifying the manufacturing process and reducing the processing cost.

附图说明Description of drawings

图1为本发明堆叠封装结构在一较优实施例中的结构示意图；FIG. 1 is a schematic structural diagram of a stacked package structure in a preferred embodiment of the present invention;

图2为本发明堆叠封装结构在另一较优实施例中的结构示意图；FIG. 2 is a schematic structural diagram of another preferred embodiment of the stacked packaging structure of the present invention;

图3为本发明堆叠封装结构在又一较优实施例中的结构示意图；FIG. 3 is a structural schematic diagram of another preferred embodiment of the stacked packaging structure of the present invention;

图4为本发明堆叠封装制造方法在一较优实施例中的流程示意图；FIG. 4 is a schematic flow diagram of a preferred embodiment of the stacked package manufacturing method of the present invention;

图5为图4中步骤S1对应的结构示意图；FIG. 5 is a schematic structural diagram corresponding to step S1 in FIG. 4;

图6为图4中步骤S2对应的结构示意图；FIG. 6 is a schematic structural diagram corresponding to step S2 in FIG. 4;

图7为图4中步骤S3对应的结构示意图；FIG. 7 is a schematic structural diagram corresponding to step S3 in FIG. 4;

图8为图4中步骤S4对应的结构示意图；FIG. 8 is a schematic structural diagram corresponding to step S4 in FIG. 4;

图9为图4中步骤S5对应的结构示意图。FIG. 9 is a schematic structural diagram corresponding to step S5 in FIG. 4 .

主要元件符号说明Description of main component symbols

第一封装体 1First Package 1

第二封装体 2Second Package 2

第三封装体 3Third Package 3

第一锡球 1aFirst Ball 1a

基板 1bSubstrate 1b

第一芯片 1cFirst chip 1c

第一注胶体 1dFirst injection of colloid 1d

第一封装线路 1eFirst Package Line 1e

导电填充孔 1fConductive filled hole 1f

第一焊垫 1g1st pad 1g

第二锡球 2aSecond solder ball 2a

第二注胶体 2bSecond injection of gel 2b

第二芯片 2cSecond chip 2c

第二焊垫 2d2nd pad 2d

无源器件 3aPassive components 3a

第二封装线路 3bSecond Package Line 3b

第三芯片 3cThird chip 3c

第三注胶体 3dThe third colloidal 3d

贯穿孔 hThrough hole h

如下具体实施方式将结合上述附图进一步说明本发明。The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

具体实施方式detailed description

实施例一Embodiment one

参阅图1所示，是本发明的堆叠封装结构在一较优实施例中的结构示意图。Referring to FIG. 1 , it is a schematic structural diagram of a package-on-package structure in a preferred embodiment of the present invention.

本实施例的堆叠封装结构包括第一封装体1和堆叠在第一封装体1上的第二封装体2，其中：The package-on-package structure of this embodiment includes a first package 1 and a second package 2 stacked on the first package 1, wherein:

第一封装体1包括基板1b,基板1b具有相对设置的两面。基板1b的一面上安装有第一元器件并设有第一焊垫1g，该第一元器件通过第一封装线路1e与第一焊垫1g电连接。在具体实施中，该第一元器件可以为第一芯片1c。基板1b的另一面上设有第一锡球1a，用于与外部元件电性连接。第一封装体1还包括包覆第一元器件、第一焊垫1g和第一封装线路1e的第一注胶体1d。The first package body 1 includes a substrate 1b, and the substrate 1b has two opposite sides. A first component is mounted on one side of the substrate 1b and a first pad 1g is provided, and the first component is electrically connected to the first pad 1g through a first package circuit 1e. In a specific implementation, the first component may be a first chip 1c. The other surface of the substrate 1b is provided with first solder balls 1a for electrical connection with external components. The first package body 1 further includes a first glue injection body 1d covering the first component, the first solder pad 1g and the first package circuit 1e.

第二封装体2包括第二元器件、包覆该第二元器件的第二注胶体2b。在本实施例中，第二元器件可为第二芯片2c。The second package 2 includes a second component and a second glue 2b covering the second component. In this embodiment, the second component may be a second chip 2c.

第二封装体2通过第二注胶体2b与第一注胶体1d的接合附着在所述第一封装体1上，第一封装线路1e和第二元器件通过设于第一注胶体1d上的导电填充孔1f电连接。The second package body 2 is attached to the first package body 1 through the bonding of the second glue body 2b and the first glue body 1d, and the first package circuit 1e and the second components pass through the first glue body 1d. The conductive filling holes 1f are electrically connected.

具体而言，第二注胶体2b上与第一注胶体1d接合的位置设有第二焊垫2d，第二元器件通过第二锡球2a与第二焊垫2d电性连接，所述导电填充孔1f电性连接于第一焊垫1g与第二焊垫2d之间，从而使第一封装体1和第二封装体2电连接。可以理解的是，上述导电填充孔1f的作用是电连接第一封装体1和第二封装体2，因此，导电填充孔1f的一端可以与第一封装体1的任何导体(如第一封装线路1e、第一焊垫1g、第一元器件1c)连接导通，同理，导电填充孔1f的另一端可以与第二封装体2的任何导体(如第二焊垫2d、第二元器件2c)连接导通，并不限于连接在第一焊垫1g与第二焊垫2d之间。Specifically, the second bonding pad 2d is provided at the position where the second bonding body 2b is connected with the first bonding body 1d, and the second component is electrically connected to the second bonding pad 2d through the second solder ball 2a. The filling hole 1f is electrically connected between the first pad 1g and the second pad 2d, so as to electrically connect the first package 1 and the second package 2 . It can be understood that the function of the above-mentioned conductive filling hole 1f is to electrically connect the first package body 1 and the second package body 2, therefore, one end of the conductive filling hole 1f can be connected to any conductor of the first package body 1 (such as the first package body The circuit 1e, the first welding pad 1g, and the first component 1c) are connected and conducted. Similarly, the other end of the conductive filling hole 1f can be connected to any conductor of the second package body 2 (such as the second welding pad 2d, the second component The device 2c) is connected and conducted, and is not limited to be connected between the first pad 1g and the second pad 2d.

导电填充孔1f包括贯穿孔及设于贯穿孔内的导电物质，导电物质可为填充于贯穿孔内的导电糊或镀附于贯穿孔内壁上的导电膜。The conductive filling hole 1f includes a through hole and a conductive substance disposed in the through hole. The conductive substance can be a conductive paste filled in the through hole or a conductive film plated on the inner wall of the through hole.

本实施例中，堆叠封装结构只需在第一封装体1上设置基板，第二封装体2可利用自身的第二注胶体2b与第一封装体1自身的第一注胶体1d相接合，从而直接堆叠在第一封装体1上，第一注胶体1d、第二注胶体2b均为其对应封装体必备的封装结构，可省略单独封装用的基板和焊接部件，从而减小了堆叠封装结构的厚度，同时，在制作第一封装体1、第二封装体2的同时可同步完成堆叠，减少了工序，从而简化了制造工艺、降低了加工成本。In this embodiment, the stacked package structure only needs to have a substrate on the first package 1, and the second package 2 can use its own second glue 2b to bond with the first glue 1d of the first package 1 itself. Therefore, it is directly stacked on the first package body 1, the first glue injection body 1d and the second glue injection body 2b are necessary packaging structures for the corresponding package body, and the substrate and soldering parts for separate packaging can be omitted, thereby reducing the stacking At the same time, when the first package body 1 and the second package body 2 are produced, the stacking can be completed simultaneously, which reduces the process, thereby simplifying the manufacturing process and reducing the processing cost.

实施例二Embodiment two

参阅图2所示，是本发明的堆叠封装结构在另一较优实施例中的结构示意图。Referring to FIG. 2 , it is a structural schematic diagram of another preferred embodiment of the package-on-package structure of the present invention.

本实施例的堆叠封装结构包括第一封装体1和堆叠在第一封装体1上的第三封装体3，其中The package-on-package structure of this embodiment includes a first package body 1 and a third package body 3 stacked on the first package body 1, wherein

第一封装体1的结构与实施例一中相同，在此不做赘述。The structure of the first package body 1 is the same as that in the first embodiment, and will not be repeated here.

第三封装体3包括无源器件、第三芯片3c、电连接该无源器件和第三芯片3c的第二封装线路3b、包覆该无源器件、第三芯片3c及第二封装线路3b的第三注胶体3d。The third package body 3 includes a passive device, a third chip 3c, a second package circuit 3b electrically connecting the passive device and the third chip 3c, covering the passive device, the third chip 3c and the second package circuit 3b The third injection of colloidal 3d.

第三封装体3通过第三注胶体3d与第一注胶体1d的接合附着在所述第一封装体1上，第一封装线路1e和第二封装线路3b通过设于第一注胶体1d上的导电填充孔1f电连接。具体而言，第三注胶体3d上与第一注胶体1d接合的位置设有第三焊垫，上述无源器件与第三焊垫焊接，第三芯片3c粘接于第一注胶体1d上，无源器件与第三芯片3c通过连接线电连接，均接入第二封装线路3b中，导电填充孔1f电性连接于第一焊垫与第三焊垫之间，从而使第一封装体1和第三封装体3电连接。同样需要说明的是，导电填充孔1f的一端可以与第一封装体1的任何导体连接导通，另一端可以与第三封装体3的任何导体(如第三焊垫、无源器件、第三芯片3c)连接导通，并不限于连接在第一焊垫1g与第三焊垫之间。The third package 3 is attached to the first package 1 through the joint of the third glue 3d and the first glue 1d, and the first package circuit 1e and the second package circuit 3b are arranged on the first package 1d. The conductive filling hole 1f is electrically connected. Specifically, a third bonding pad is provided at the position where the third bonding body 3d is bonded to the first bonding body 1d, the above-mentioned passive components are welded to the third bonding pad, and the third chip 3c is bonded to the first bonding body 1d , the passive device and the third chip 3c are electrically connected through connecting wires, and are connected to the second package circuit 3b, and the conductive filling hole 1f is electrically connected between the first pad and the third pad, so that the first package The body 1 and the third package body 3 are electrically connected. It should also be noted that one end of the conductive filling hole 1f can be connected to any conductor of the first package 1, and the other end can be connected to any conductor of the third package 3 (such as the third pad, passive device, the first The three chips 3c) are connected and conducted, and are not limited to being connected between the first pad 1g and the third pad.

本实施例提供的堆叠封装结构可适用于不同结构的封装体之间的堆叠，只需根据具体需求对电连接结构做适应性调整，使各封装体连接导通即可。此外，本实施例的方案同样具有减小堆叠封装结构的厚度、简化制造工艺、降低加工成本的优点，理同实施例一，在此不再做分析。The stacked package structure provided in this embodiment is applicable to stacking packages with different structures, and only needs to make adaptive adjustments to the electrical connection structure according to specific requirements to make the packages conductively connected. In addition, the solution of this embodiment also has the advantages of reducing the thickness of the package-on-package structure, simplifying the manufacturing process, and reducing the processing cost, which is the same as the first embodiment, and will not be analyzed here.

实施例三Embodiment Three

参阅图3所示，是本发明的堆叠封装结构在又一较优实施例中的结构示意图。Referring to FIG. 3 , it is a structural schematic diagram of another preferred embodiment of the package-on-package structure of the present invention.

本实施例的堆叠封装结构包括第一封装体1、堆叠在第一封装体1上的第三封装体3及堆叠在第三封装体3上的第二封装体2。其中第一封装体1、第二封装体2、第三封装体3的结构与实施例一及实施例二中对应的结构相同。第三封装体3通过与实施例二相同的方式堆叠在第一封装体1上。第二封装体2通过第二注胶体2b与第三注胶体3d的接合堆叠在第三封装体3上。The package-on-package structure of this embodiment includes a first package 1 , a third package 3 stacked on the first package 1 , and a second package 2 stacked on the third package 3 . The structures of the first package body 1 , the second package body 2 , and the third package body 3 are the same as those in the first and second embodiments. The third package body 3 is stacked on the first package body 1 in the same manner as in the second embodiment. The second package body 2 is stacked on the third package body 3 through the bonding of the second glue body 2b and the third glue body 3d.

可以理解的是，在具体实施中，根据实际需求可参照实施例三的堆叠方式进行更多层堆叠封装。It can be understood that, in specific implementation, more layers of stacking and packaging can be performed with reference to the stacking manner of Embodiment 3 according to actual needs.

综合上述实施例可以看出，本发明公开的堆叠封装结构只需在第一封装体1设置基板，堆叠在第一封装体上的第二封装体2，或更多的第三封装体3均可直接接合在与之相邻的封装体上，可省略单独封装用的基板和焊接部件，从而减小堆叠封装结构的厚度，也简化了制造工艺、降低了加工成本。Based on the above-mentioned embodiments, it can be seen that the package-on-package structure disclosed in the present invention only needs to provide a substrate on the first package 1, and the second package 2 or more third packages 3 stacked on the first package It can be directly bonded to the package body adjacent to it, and the substrate and soldering parts for separate package can be omitted, thereby reducing the thickness of the stacked package structure, simplifying the manufacturing process and reducing the processing cost.

本发明还公开了一种堆叠封装结构的制造方法，现结合实施例二中的堆叠封装结构进行详细阐述。参阅图4所示，该堆叠封装结构的制造方法包括步骤：The present invention also discloses a method for manufacturing a package-on-package structure, which will now be described in detail in conjunction with the package-on-package structure in Embodiment 2. Referring to FIG. 4, the manufacturing method of the package-on-package structure includes steps:

S1、请同时参阅图4和图5，提供一基板1b，在基板1b上安装第一元器件(如第一芯片1c)，并注胶形成包覆该第一元器件的第一注胶体1d；在具体实施中，还包括在所述基板上设置第一焊垫1g的步骤，第一元器件通过第一焊垫1g安装在基板1b上；S1. Please refer to Fig. 4 and Fig. 5 at the same time, provide a substrate 1b, mount the first component (such as the first chip 1c) on the substrate 1b, and inject glue to form the first injection body 1d covering the first component ; In a specific implementation, it also includes the step of setting a first welding pad 1g on the substrate, and the first component is mounted on the substrate 1b through the first welding pad 1g;

S2、请同时参阅图4和图6，在所述第一注胶体1d的预定位置开设贯穿孔h；S2. Please refer to Fig. 4 and Fig. 6 at the same time, and open a through hole h at the predetermined position of the first injection gel 1d;

S3、请参阅图4和图7，在贯穿孔h内填充导电物质形成导电填充孔1f，导电物质可为填充于贯穿孔h内的导电糊或镀附于贯穿孔h内壁上的导电膜，并在所述第一注胶体1d上蚀刻、电镀形成连接所述第一元器件及所述导电填充孔的第一封装线路1e；S3, please refer to Fig. 4 and Fig. 7, fill the conductive substance in the through hole h to form the conductive filling hole 1f, the conductive substance can be a conductive paste filled in the through hole h or a conductive film plated on the inner wall of the through hole h, And etching and electroplating on the first glue injection body 1d to form a first packaging line 1e connecting the first component and the conductive filling hole;

S4、请同时参阅图4和图8，在所述第一注胶体1d上安装第二元器件，具体而言，可在所述第一注胶体1d上形成与所述导电填充孔连接的第二焊垫2d，将第二元器件通过第二焊垫2d安装固定；将第二元器件与所述导电填充孔1f电连接，并注胶形成包覆该第二元器件的第二注胶体2b；S4. Please refer to FIG. 4 and FIG. 8 at the same time, install the second component on the first glue injection body 1d, specifically, form a second component connected to the conductive filling hole on the first glue injection body 1d The second welding pad 2d is used to install and fix the second component through the second welding pad 2d; electrically connect the second component to the conductive filling hole 1f, and inject glue to form a second glue injection covering the second component 2b;

S5、请同时参阅图4和图9，通过植球工艺在所述基板上形成第一锡球1a，用于与外部元件电性连接。S5. Referring to FIG. 4 and FIG. 9 at the same time, a first solder ball 1a is formed on the substrate through a ball planting process for electrical connection with external components.

本实施例公开的堆叠封装结构的制造方法中，利用封装体必备的封装结构，如第一注胶体1d、第二注胶体2b的接合完成堆叠，第一注胶体1d、第二注胶体2b均为其对应封装体必备的封装结构，可省略单独封装用的基板和焊接部件，从而减小了堆叠封装结构的厚度，并且在制作封装体的同时可同步完成堆叠，减少了工序，从而简化了制造工艺、降低了加工成本。In the manufacturing method of the stacked packaging structure disclosed in this embodiment, the packaging structure necessary for the package is used, such as the bonding of the first glue injection 1d and the second glue injection 2b to complete the stacking, the first glue injection 1d, the second glue injection 2b Both are necessary packaging structures for their corresponding packages, which can omit the substrate and welding parts for individual packaging, thereby reducing the thickness of the stacked packaging structure, and can simultaneously complete the stacking while manufacturing the package, reducing the process, thereby The manufacturing process is simplified and the processing cost is reduced.

以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或等同替换，而不脱离本发明技术方案的精神和范围。The above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced. Without departing from the spirit and scope of the technical solution of the present invention.

Claims (10)

1. a kind of stack package structure, it is characterised in that including
First packaging body, it includes substrate, the of the first component for being installed on the substrate, cladding first component One glue injection body, first electrically connected in first glue injection body and with first component encapsulation circuit；
Second packaging body, it includes the second component, the second glue injection body of cladding second component；
Second packaging body is attached to first encapsulation by the engagement of second glue injection body and first glue injection body On body, the first encapsulation circuit and second component pass through located at first glue injection body and/or second injecting glue Conductive fill hole electrical connection on body.
2. stack package structure as claimed in claim 1, it is characterised in that：The substrate is provided with the first weld pad, described the One component is electrically connected with first weld pad；The position that first glue injection body is engaged with the second glue injection body is provided with the second weldering Pad, second component is electrically connected with second weld pad；The conductive fill hole is electrically connected at first weld pad Between the second weld pad.
3. stack package structure as claimed in claim 1, it is characterised in that：The substrate, which is provided with, to be used for and outer member electricity Property connection the first tin ball, second component and second weld pad are electrically connected with by the second tin ball.
4. stack package structure as claimed in claim 1 or 2, it is characterised in that：The conductive fill hole include through hole and It is filled in the conductive materials in the through hole.
5. stack package structure as claimed in claim 4, it is characterised in that：The conductive materials are to be filled in the through hole sheet Internal electroconductive paste or plating invests the conducting film in the through hole inner body wall.
6. stack package structure as claimed in claim 1, it is characterised in that：Also include being attached on second packaging body At least one layer of 3rd packaging body；3rd packaging body is identical with second package body structure, and by with second envelope Dress body identical adhering mode second packaging body adjacent with the 3rd packaging body or the 3rd packaging body are engaged and electrically connected.
7. such as stack package structure according to any one of claims 1 to 3, it is characterised in that：First component, second Component is the one or more in bare chip, passive device, encapsulation chip.
8. a kind of manufacture method of stack package structure, it is characterised in that including step：
S1, one substrate of offer, the first component is installed in substrate, and injecting glue formation coats the first injecting glue of first component Body；
S2, in the precalculated position of first glue injection body open up conductive fill hole；
S3, etch on first glue injection body, electroplate and form connect first component and the conductive fill hole the One encapsulation circuit；
S4, on first glue injection body the second component is installed, the second component is electrically connected with the conductive fill hole, and Injecting glue formation coats the second glue injection body of second component.
9. the manufacture method of stack package structure as claimed in claim 8, it is characterised in that：It is additionally included in the step S1 The step of setting the first weld pad on the substrate, first component is by first pad installation on substrate；It is described The step of the second weld pad that formation is connected with the conductive fill hole on first glue injection body is additionally included in step S4, it is described Second component is fixed by second pad installation.
10. the manufacture method of stack package structure as claimed in claim 8, it is characterised in that：Also include step
S5, by planting ball technique the first tin ball for being electrically connected with outer member is formed on the substrate.
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