CN107799424A - Method for packaging embedded circuit - Google Patents

Abstract

The invention discloses a method for encapsulating an embedded circuit, which comprises the following steps: providing a carrier plate; arranging an embedded element on the carrier plate; forming a plurality of guide posts on two sides of the embedded element; electroplating a first conductor layer on the embedded element; forming a patterned first dielectric layer to cover the guide pillar, the embedded element and the first conducting wire layer and expose a part of the first conducting wire layer and one end surface of the guide pillar; electroplating a second conducting wire layer on the first conducting wire layer exposed from the patterned first dielectric layer and the guide posts; forming a second dielectric layer to cover the second conducting wire layer and expose the end face of the second conducting wire layer; forming a third conductor layer on the end surface of the second conductor layer exposed outside the second dielectric layer; forming a third dielectric layer to cover the third conductive layer; the carrier is removed to expose another end surface of the guide pillars. Because the packaging method of the invention replaces welding connection with electroplating, the resistance value of the whole chip module is greatly reduced, thereby improving the efficiency and stability of the chip module.

Description

Embedded circuit packaging method

technical field

The invention relates to a packaging method, especially a method for packaging embedded circuits.

Background technique

IC packaging is covered with plastic/ceramic or metal substances on the outside of the IC chip to protect the chip from external environmental factors, prevent moisture from penetrating into the chip, and lead the functional signals on the chip to the outside to achieve electrical performance. The purpose and effect of connection, physical support, heat resistance and heat dissipation, and different types of terminal electronic products can choose different types of packaging technologies.

With the development of terminal electronic products becoming increasingly light, thin, small, high-speed and multi-functional, traditional lead frame packaging products and packaging technologies are increasingly unable to meet the requirements of existing IC technology and electronic products, except for the miniaturization of electronic components to reduce volume In addition, reducing the number of electronic components used is also a development strategy. However, in order to avoid affecting the function and stability of terminal electronic products due to the reduction of the number of components, integrating components into an integrated substrate has become an important development direction. Therefore , many new-generation packaging technologies have been developed one after another.

The development of integrated components still needs to rely on integration technology. Driven by market demand, System in Package (SiP) has become a development trend. The system-in-package is on a substrate, and at least one component with different functions is stacked or connected to achieve the system function required by the terminal electronic product, which means that chips with different functions are integrated in the same package module. In terms of structural appearance, system-in-package can be divided into two-dimensional and three-dimensional packages. Among them, three-dimensional system-in-package includes chip stack (Stack Die), PoP (Package on Package), PiP (Package in Package) and embedded components (Embedded component) and other technologies. At present, the development direction of system-in-package is to integrate active and passive components. Through different forms of packaging technology, active and passive components are embedded in the substrate, so that system package products can better meet the needs of downstream products. . Taking embedded passive components as an example, passive components such as resistors, inductors, and capacitors that were originally placed on the surface of the printed circuit board substrate are embedded in the substrate, that is, the conventional surface mount technology (SMD) is used to attach the surface of the substrate to the surface of the substrate. Passive components are integrated into the printed circuit board, which can reduce the area required for a single circuit board, reduce product size, reduce solder joints on the circuit board, improve electrical performance and reduce noise. Because it embeds passive components in the circuit board, it can reduce problems such as humidity and corrosion, and prolong the service life. Three-dimensional system-in-package has been favored by the industry in recent years due to its advantages of thinness, low system cost, high performance, and allowing highly heterogeneous chip integration. Level packaging technology is used.

However, the current embedded component technology mostly uses soldering to join the chip and the wire layer, or the wire layer and the guide post, etc., resulting in an increase in the resistance of the entire module. In addition, the conventional PoP packaging technology needs to solder an interposer to preserve the wiring. Space and protect components, in addition to increasing the thickness of the package, it also increases the resistance value. In view of these shortcomings, the present invention proposes a brand-new embedded circuit packaging method, which optimizes the existing problems of embedded component technology, and combines PoP packaging technology to reduce the resistance value and improve the complicated manufacturing process.

Contents of the invention

The main purpose of the present invention is to provide a method for embedded circuit packaging, which is to directly electroplate a first wire layer on an embedded component, replacing the conventional method of soldering and joining, so as to reduce the resistance value and improve performance and stability.

Another object of the present invention is to provide a method for embedded circuit packaging, which is to directly electroplate a second wire layer on several guide posts instead of soldering, so that the resistance value of the entire module can be reduced, and Improve electricity.

In order to achieve the above object, the present invention discloses a method of embedded circuit packaging, which includes: providing a carrier board, and arranging an embedded component on the carrier board, and at least one side of the embedded component forming a plurality of guide pillars; electroplating a first wire layer on the embedded element; forming a patterned first dielectric layer to cover the guide pillars, the embedded element and the first wire layer, and exposing A first end face of the guide pillars and part of the first conductor layer are exposed; then a second conductor layer is electroplated on the first conductor layer exposed from the patterned first dielectric layer and the guide pillars The first end face; forming a second dielectric layer on the patterned first dielectric layer, covering the second wire layer, and exposing part of the end face of the second wire layer; forming a third wire Layer on the end surface of the second wire layer exposed from the second dielectric layer; then form a third dielectric layer on the second dielectric layer to cover the third wire layer; finally move removing the carrier plate and exposing a second end surface of the guide pillars. Since the packaging method of the present invention uses electroplating instead of welding, the resistance value of the entire chip module is greatly reduced, thereby improving its performance and stability.

And the embedded packaging structure made by the above-mentioned embedded circuit packaging method includes a first wire layer disposed on the embedded element; a patterned first dielectric layer covering the embedded element, The first wire layer and the guide pillars, and expose a part of the first wire layer and an end surface of the guide pillars; a second wire layer, disposed on the exposed part of the patterned first dielectric layer Part of the area of the first wire layer and the end surfaces of the guide pillars; a second dielectric layer is disposed on the patterned first dielectric layer and covers the second wire layer, and exposes a part of the The end face of the second wire layer; a third wire layer disposed on the end face of the second wire layer exposed from the second dielectric layer; and a third dielectric layer covering the third wire layer .

In an embodiment of the present invention, it is also disclosed that after the step of removing the carrier board is completed, further comprising providing an external module and electrically connecting to the second end surfaces of the guide posts and/or the third interface The electrical layer exposes an end face of the third wire layer, and forms a plurality of metal balls on the end face of the third wire layer exposed from the third dielectric layer.

In an embodiment of the present invention, it is also disclosed that before the step of arranging the embedded device, further comprising electroplating a heat dissipation layer on the carrier board.

In an embodiment of the present invention, which is also disclosed in the step of arranging the embedded component, the embedded component is adhered to the carrier through an adhesive layer.

In an embodiment of the present invention, it also discloses that the adhesive layer is a joint glue or a joint film.

In an embodiment of the present invention, it is also disclosed that the guide posts include copper.

In an embodiment of the present invention, it is also disclosed that before the step of electroplating the second wiring layer, the first dielectric layer is treated with laser to expose the first wiring layer.

In an embodiment of the present invention, it also discloses that the embedded component is an active component, a passive component, a semiconductor chip or a circuit board.

Description of drawings

Fig. 1: it is the structural representation of the first embodiment of the present invention;

Fig. 2: it is the method flowchart of the first embodiment of the present invention;

3A to 3K: they are schematic diagrams of the packaging method of the first embodiment of the present invention;

Fig. 4: it is the structural representation of the second embodiment of the present invention;

Figure 5: It is a schematic structural diagram of a third embodiment of the present invention; and

Figure 6: It is a schematic diagram of a conventional Package on Package (PoP) packaging structure.

[Description of drawing number comparison]

10 carrier board

20 package structure

200 layers of adhesive

202 Embedded components

204 guide post

2042 First end face

2044 Second end face

206 First conductor layer

208 first dielectric layer

209 Patterning the first dielectric layer

210 Second conductor layer

212 Second conductor layer

214 Second dielectric layer

216 Third wiring layer

218 third dielectric layer

220 add-on modules

222 welding points

224 metal ball

226 heat dissipation layer

228 Embedded components

30 package structure

300 circuit substrate

302 Interposer

304 welding points

306 add-on modules

Detailed ways

In order to make the structural features of the present invention and the achieved effects have a further understanding and recognition, preferred embodiments and detailed descriptions are specially used, which are described as follows:

This implementation case provides a packaging method for the packaging of embedded circuits. In response to the increasingly thinner and smaller terminal electronic products, the system-level packaging technology has been developed for the purpose of reducing the volume of electronic components and achieving high performance and multi-function. It includes technologies such as embedded circuit packaging and PoP packaging. In order to make the packaged product more in line with the needs of downstream products and reduce process costs, optimization of packaging methods or the combination of different packaging technologies have also emerged accordingly. The method of embedded circuit packaging of the present invention uses electroplating bonding instead of soldering to greatly reduce the resistance value of the entire chip module, thereby improving product performance and stability. In addition, when the packaging structure of this method is applied to PoP packaging technology, no need to set The interposer can directly package the external modules. In addition to reducing the resistance value, it also simplifies the packaging process and reduces the manufacturing cost.

Please refer to FIG. 1 , which is a schematic structural diagram of a first embodiment of the present invention. As shown in the figure, a packaging structure 20 includes an embedded component 202, and an adhesive layer 200 is arranged on a surface of the embedded component 202. The adhesive layer 200 is used to bond the embedded component 202 on a carrier 10 (see FIG. 3A ) during the packaging process, as described in the subsequent process steps; several guide posts 204 are arranged on the embedded component 202 on both sides; a first wire layer 206, electroplated on the other side of the embedded element 200 and electrically connected with the embedded element 202; a patterned first dielectric layer 209, which covers the guide pillars 204, the embedded component 202, and part of the first wire layer 206 and the upper and lower end surfaces of the guide pillars 204 are exposed (that is, a first end surface 2042 and a second end surface 2044 mentioned later); a second The wire layer 210 is electroplated on the first wire layer 206 exposed from the above-mentioned patterned first dielectric layer 209 and is electrically connected with the first wire layer 206, and a second wire layer 212 is electroplated on the first wire layer 206. One end surface (the first end surface 2042) of the guide pillars 204 exposed by the patterned first dielectric layer 209 is electrically connected with the guide pillars 204; a second dielectric layer 214 is located in the pattern on the first dielectric layer 209 and cover the second wire layer 210, 212, and expose part of an end surface of the second wire layer 210, 212; a third wire layer 216 is formed on the second wire layer 216 from the second wire layer The end faces of the second wire layers 210, 212 exposed by the electrical layer 214 are electrically connected to the second wire layers 210, 212; and a third dielectric layer 218 is located on the second dielectric layer 214 and covers Covers the third wire layer 216 and exposes part of an end surface of the third wire layer 216 .

Wherein, the packaging device 20 can further solder a plurality of metal balls 224 on the end surface of the third wire layer 216 exposed from the third dielectric layer 218; On the other end surface (the second end surface 2044 ) of the guide pillars 204 exposed by the first dielectric layer 209 .

Please refer to FIG. 2 and FIG. 3, which are the method flow chart of the first embodiment of the present invention and the schematic diagram of the packaging method of the first embodiment of the present invention. The steps of the packaging method of the packaging device 20 include:

Step S200: As shown in FIG. 3A, provide a carrier board 10;

Step S202: As shown in FIG. 3B, set an embedded component 202 on the carrier 10; the embedded component 202 is pasted on the carrier 10 through an adhesive layer 200; wherein, the embedded component 202 It can be an active element, a passive element, a semiconductor chip or a functional element such as a circuit board, but this does not limit the embedded element 202 used in the present invention to the above-mentioned form. Furthermore, the above-mentioned adhesive The glue layer 200 can be selected from joint glue or joint film;

Step S204: As shown in FIG. 3C , forming a plurality of guide pillars 204 on at least one side of the embedded component 202, wherein the material of the guide pillars 204 may include copper;

Step S206 : As shown in FIG. 3D , form a first wiring layer 206 on the embedded device 202 , wherein the first wiring layer 206 includes metals such as copper with low resistance, but not limited thereto. The first wire layer 206 can be formed on the embedded component 202 by electroplating. It is known to connect the component and the wire layer by soldering. Due to the difference in purity between the soldering material and the plating material, soldering has a higher resistance value than electroplating. , here, the packaging method of the present invention replaces soldering with electroplating to reduce resistance and improve performance;

Step S208: As shown in FIG. 3E, a first dielectric layer 208 is formed to cover the guide pillars 204, the embedded element 202 and the first wiring layer 206, and the height of the first dielectric layer 208 is essentially Same as the guide pillars 204, to expose a first end surface 2042 of the guide pillar 204, and then drill the first dielectric layer 208 with a laser to form a patterned first dielectric layer 209, A part of the first wire layer 206 is exposed (as shown in FIG. 3F ). However, the processing method for forming the patterned first dielectric layer 209 is not limited to only using laser for drilling;

Step S210: As shown in FIG. 3G , forming a second wire layer 210, 212 on the first wire layer 206 exposed from the patterned first dielectric layer 209 and the first end surfaces 2042 of the guide pillars 204, And electrically connected with the first wiring layer 206 exposed from the patterned first dielectric layer 209 and the guide pillars 204, wherein the second wiring layers 210, 212 include metals such as copper with low resistance Not limited to this, in order to improve the performance of the entire module, the step S210 also replaces welding with electroplating, so as to eliminate the resistance caused by welding;

Step S212: As shown in FIG. 3H , forming a second dielectric layer 214 located on the patterned first dielectric layer 209 and covering the second wire layers 210, 212, the height of the second dielectric layer 212 is It is essentially the same as the highest one of the second wire layers 210, 212, so as to expose the end faces of the second wire layers 210, 212 to be connected with wires;

Step S214: As shown in FIG. 3I, form a third wiring layer 216 on the second wiring layers 210, 212 exposed from the second dielectric layer 214, and part of the second dielectric layer 214, and It is electrically connected with the second wiring layer 210, 212 exposed from the second dielectric layer 214, and the third wiring layer 216 is deposited and formed by electroplating; wherein, the third wiring layer 216 includes a low resistance copper and other metals, but not limited thereto;

Step S216: As shown in FIG. 3J , forming a third dielectric layer 218 on the second dielectric layer 214 and covering the third wiring layer 216, the height of the third dielectric layer 218 is essentially the same as the The highest ones of the third wire layer 216 are the same, so as to expose the end surface of the third wire layer 216 to be electrically connected; and

Step S218 : as shown in FIG. 3K , remove the carrier board 10 to expose a second end surface 2044 of the guide posts 204 .

The above-mentioned first dielectric layer 208, the second dielectric layer 214 or the third dielectric layer 218 is formed by a molding method, and the material of the molded dielectric layer can be molded compound (Molding compound) for chip packaging. Compound) such as but not limited to having Novolac-Based Resin, Epoxy-Based Resin, Silicone-Based Resin or other suitable molding compound, and molding The compounds may also contain suitable fillers, such as powdered silicon dioxide. What's more, because of the die-casting method, the dielectric layer will cover the existing components. For example, as shown in FIG. 1, the first dielectric layer 208 will cover the adhesive on the carrier 10 layer 200, the embedded element 202, the first wire layer 206, and the guide pillars 204, and then by controlling the height of the first dielectric layer 208 or patterning, the conductor part to be electrically connected in the future is exposed, for example The end surfaces of the guide pillars 204 .

Please refer to FIG. 1 and FIG. 6 again, which are schematic structural diagrams of the first embodiment of the present invention and conventional Package on Package (PoP) packaging structures. As shown in FIG. , which can be further applied to PoP encapsulation technology. As can be seen in the conventional PoP packaging structure shown in Figure 6, it needs to weld an interposer 302 to reserve the wiring space and protect a circuit substrate 300, and then solder an external module 306 on the interposer 302, however, the present invention The packaging device 20 can directly arrange an external module 220 on the guide pillars 204 without disposing the intermediary layer 302. In this way, not only the resistance value caused by soldering is reduced, but also the manufacturing process steps can be simplified and the cost can be reduced.

Please refer to FIG. 4, which is a schematic structural diagram of the second embodiment of the present invention. In the above method flow, before performing the step S202, a heat dissipation layer 226 may also be provided on the carrier board 10, and then the adhesive layer may be formed. 200 is on the heat dissipation layer 226 to optimize the heat dissipation effect of the embedded element 202. The heat dissipation layer 226 can be disposed on the carrier 10 by electroplating, but not limited thereto.

Please refer to FIG. 5 , which is a schematic structural diagram of a third embodiment of the present invention. In the above method flow, before performing step S212, an embedded element 228 may be further arranged on the second dielectric layer according to the functional requirements of the module. 210, the installation method can be surface bonding technology (SMT), but not limited thereto, wherein the embedded component 228 is a functional component such as an active component, a passive component, a semiconductor chip or a circuit board, but not here limit.

Based on the above, the embedded circuit packaging method of the present invention uses electroplating to form the first wire layer, the second wire layer, and the third wire layer connecting the embedded component and the guide post. The conventional embedded technology is connected by soldering. Components and wire layers, however, the purity of soldering materials is lower than that of electroplating materials, resulting in relatively higher resistance values. The present invention replaces soldering with electroplating, which greatly reduces the resistance value of the entire module, thereby improving electrical properties, performance and stability. . In addition, the packaging device of the present invention can be further applied to PoP packaging technology, and the interposer layer can be omitted, which simplifies the process steps and reduces the cost.

The above is only a preferred embodiment of the present invention, and is not intended to limit the implementation scope of the present invention. All equivalent changes and modifications made in accordance with the shape, structure, characteristics and spirit described in the scope of the claims of the present invention shall be included in the scope of the claims of the present invention.

Claims (10)

1. A kind of 1. method of embedded line encapsulation, it is characterised in that its step includes：

   One support plate is provided；

   One embedded element is set on the support plate；

   Several guide pillars are formed at least side of the embedded element；

   A conductor layer No.1 is formed on the embedded element；

   First dielectric layer of patterning is formed, it coats those guide pillars and the embedded element, and manifests part first wire One first end face of layer and the guide pillar；

   Form the conductor layer No.1 and those guide pillars that one second conductor layer is manifested from the dielectric layer of patterning first in this The first end face on；

   One second dielectric layer is formed, it coats second conductor layer, and manifests the end face of part second conductor layer；

   A privates layer is formed on the end face of second conductor layer manifested from second dielectric layer；

   One the 3rd dielectric layer is formed, it coats the privates layer；And

   Remove the support plate and expose a second end face of those guide pillars.
2. 2. the method for embedded line encapsulation as claimed in claim 1, it is characterised in that wherein remove the support plate in completion After step, further comprise：

   One external connection module is provided and is electrically connected in the second end face of those guide pillars；And/or

   3rd dielectric layer manifests the privates layer end face, and forms a plurality of metal balls in from the 3rd dielectric layer On the end face of the privates layer manifested.
3. 3. the method for embedded line as claimed in claim 1 encapsulation, it is characterised in that wherein in setting the embedded element Before step, further comprising one heat dissipating layer of setting on the support plate.
4. 4. the method for embedded line as claimed in claim 1 encapsulation, it is characterised in that wherein in setting the embedded element In step, the embedded element is attached on the support plate through a mucigel.
5. 5. the method for embedded line encapsulation as claimed in claim 4, it is characterised in that wherein the mucigel engages glue or connect Close film.
6. 6. the method for embedded line encapsulation as claimed in claim 1, it is characterised in that the material of wherein those guide pillars includes Copper.
7. 7. the method for embedded line encapsulation as claimed in claim 1, it is characterised in that the wherein dielectric layer of patterning first The conductor layer No.1 is manifested with Laser drill.
8. 8. the method for embedded line encapsulation as claimed in claim 1, it is characterised in that wherein the embedded element is an active Element, a passive device, semiconductor chip or a circuit board.
9. 9. the method for embedded line as claimed in claim 1 encapsulation, it is characterised in that wherein the conductor layer No.1, this Two conductor layers are formed with any of the privates layer by plating mode.
10. 10. the encapsulating structure obtained by a kind of method of the embedded line encapsulation described in usage right requirement 1, its feature exist In it includes：

    One embedded element；

    Several guide pillars, it is arranged at least side of the embedded element；

    One conductor layer No.1, it is arranged on the embedded element；

    One the first dielectric layer of patterning, coats the embedded element, the conductor layer No.1 and those guide pillars, and manifest this and first lead The subregion of line layer and the end face of those guide pillars；

    One second conductor layer, be arranged at the conductor layer No.1 manifested from the dielectric layer of the patterning first subregion and On the end face of those guide pillars；

    One second dielectric layer, it is arranged on the dielectric layer of patterning first and coats second conductor layer, and exposed portion should The end face of second conductor layer；

    One privates layer, it is arranged on the end face of second conductor layer manifested from second dielectric layer；And

    One the 3rd dielectric layer, coat the privates layer.