CN105551986A - COF (Chip on Flex) packaging method - Google Patents
COF (Chip on Flex) packaging method Download PDFInfo
- Publication number
- CN105551986A CN105551986A CN201510906810.8A CN201510906810A CN105551986A CN 105551986 A CN105551986 A CN 105551986A CN 201510906810 A CN201510906810 A CN 201510906810A CN 105551986 A CN105551986 A CN 105551986A
- Authority
- CN
- China
- Prior art keywords
- salient point
- metal salient
- cof
- metal
- conducting resinl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000000463 material Substances 0.000 claims abstract description 9
- 239000004033 plastic Substances 0.000 claims abstract description 7
- 238000012856 packing Methods 0.000 claims description 17
- 239000000945 filler Substances 0.000 claims description 9
- 238000003825 pressing Methods 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract 2
- 229920005989 resin Polymers 0.000 abstract 2
- NMWSKOLWZZWHPL-UHFFFAOYSA-N 3-chlorobiphenyl Chemical compound ClC1=CC=CC(C=2C=CC=CC=2)=C1 NMWSKOLWZZWHPL-UHFFFAOYSA-N 0.000 description 3
- 101001082832 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) Pyruvate carboxylase 2 Proteins 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8102—Applying permanent coating to the bump connector in the bonding apparatus, e.g. in-situ coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a COF (Chip on Flex) packaging method, and the method comprises the steps: forming a plurality of first metal convex points in function regions of a chip; forming a plurality of second metal convex points on a metal layer of a flexible circuit board; coating the first metal convex points or the second metal convex points with conducting resin columns; enabling the plurality of first metal convex points to be oppositely corresponding to the plurality of second metal convex points, and enabling the first and second metal convex points to be connected through the conducting resin columns; arranging plastic packaging bottom filling materials between the chip and the flexible circuit board, and forming a plastic packaging body. The method provided by the invention can solve problems that the heights of convex points in a conventional structure are difficult to control and a preparation method is more difficult, can reduce the cost, and improves the packaging efficiency.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, particularly relate to one and cover brilliant film (COF) method for packing.
Background technology
Along with the development of integrated circuit technique, electronic product is more and more to miniaturized, intelligent and high reliability future development, and integrated antenna package directly affects integrated circuit, electronic module and even overall performance, progressively reduce in integrated circuit (IC) wafer size, integrated level is when improving constantly, electronics industry terminates to propose more and more higher requirement to integrated antenna package.
Current chip is by the upside-down mounting of end embankment formula as on the flexible PCB (film) of carrier, and chip is connected by metal column with the metal level that film covers, and is electrically connected with the external world.The method flow typically covering brilliant film (COF) comprises: the glue-free FCCL of casting legal system, making fine-line, coating solder mask, pad plating Ni/Au, IC are installed, step such as passive device welding (Reflow Soldering), LCD installation etc.
But in the above-mentioned methods, when chip is prepared higher salient point (bump), there is the problem that some affect chip manufacturing yield:
(1) salient point (bump) of the Altitude control IC beneath chips of salient point (bump) is difficult to control that it is highly completely the same, is uneven and easily makes chip failure;
(2) on film, salient point (bump) its preparation method is produced more difficult.
Summary of the invention
In view of above-mentioned defect of the prior art or deficiency, the invention provides one and cover brilliant film (COF) method for packing.
The invention provides one and cover brilliant film (COF) method for packing, comprising:
Chip functions district is formed multiple first metal salient point;
Flexible PCB metal level is formed multiple second metal salient point;
Described first metal salient point or described second metal salient point coat conducting resinl post;
Also be connected corresponding in opposite directions one by one to described multiple first metal salient point and described multiple second metal dots by described conducting resinl post;
Between described chip and described flexible PCB with plastic packaging at the bottom of filler fill and form plastic-sealed body.
Compared with prior art, method for packing provided by the invention, can solve existing structure bumps height and be difficult to control and the more difficult problem of its preparation method, can reduce costs again, improve packaging efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the method flow diagram covering a kind of embodiment of brilliant film (COF) method for packing provided by the invention;
Fig. 2-Fig. 6 is the structural representation covering a kind of embodiment of brilliant film (COF) method for packing provided by the invention.
Reference numeral:
1-chip; 2-flexible PCB; 3-metal level; 4-conducting resinl post;
5-first metal salient point; 6-second metal salient point; 7-plastic-sealed body.
Embodiment
Below in conjunction with drawings and Examples, the application is described in further detail.Be understandable that, specific embodiment described herein is only for explaining related invention, but not the restriction to this invention.It also should be noted that, for convenience of description, illustrate only in accompanying drawing and invent relevant part.
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
As Fig. 1, present embodiments provide one and cover brilliant film (COF) method for packing, comprising:
S10: form multiple first metal salient point in chip functions district;
S20: form multiple second metal salient point on flexible PCB metal level;
S30: coat conducting resinl post on the first metal salient point or the second metal salient point;
S40: multiple first metal salient point and multiple second metal dots is corresponding in opposite directions one by one and be connected by conducting resinl post;
S50: fill with filler at the bottom of plastic packaging between chip and flexible PCB and form plastic-sealed body.
First, perform step S10, as shown in Figure 2, chip 1 functional areas form multiple first metal salient point 5;
Perform step S20, as shown in Figure 3, flexible PCB 2 metal level 3 forms multiple second metal salient point 6;
Optionally, the material of the first metal salient point 5 of providing of the present embodiment and the second metal salient point is metallic copper.Cost-saving, electric conductivity is good, and easily makes.
Perform step S30, described first metal salient point 5 or described second metal salient point 6 coat conducting resinl post 4.As Fig. 4, in the present embodiment, applying conductive glue post on the first metal salient point 5.
Preferably, conducting resinl post 4 material that the present embodiment provides is aeolotropic conductive (ACF), because aeolotropic conductive (ACF) can only conduct electricity in vertical direction, and can not conducting electricity in a parallel direction, so the distance reduced between the first metal salient point or the second salient point and conduction between the first metal salient point or the second metal salient point 6 can not be made and be short-circuited.
Perform step S40, as Fig. 5, described multiple first metal convex 5 and multiple second metal dots 6 is corresponding in opposite directions one by one and be connected by described conducting resinl post 4.
Preferably, as Fig. 5, the first metal salient point 5, second metal salient point 6 that the present embodiment provides and conducting resinl post 4 are circular cylinder.Convenient docking, also facilitates the pressing of the first metal salient point and the second metal salient point in subsequent step simultaneously.
Preferably, as Fig. 5, the axis of the first metal salient point 5 that the present embodiment provides, conducting resinl post 4 and the second metal salient point 6 point-blank.
Preferably, as Fig. 5, the diameter of section of the conducting resinl post 4 that the present embodiment provides is greater than the diameter of section of the first metal salient point 5 and the second metal salient point 6.
Perform step S50, as Fig. 6, between chip 1 and flexible PCB 2 with plastic packaging at the bottom of filler fill and form plastic-sealed body 7.
Preferably, before execution step S50, pressing chip 1 and flexible PCB 2, make the first metal salient point 5 and the second metal salient point 2 pairs of conducting resinl posts 4 apply the pressure of a vertical direction.Conducting resinl post is solidified, and the transmission signal of telecommunication can be carried out preferably in vertical direction.
Preferably the, coated first metal salient point 5, second metal salient point 6 and the conducting resinl post 4 of the plastic-sealed body filler that the present embodiment provides.Coated by plastic-sealed body filler, make the first metal salient point, the second metal salient point and conducting resinl rod structure stable, damp proof, moistureproof.
Preferably the, the material of the plastic-sealed body filler that the present embodiment provides is epoxy resin.The sealing property of this material is better, plastic packaging easy, is the preferred materials forming plastic-sealed body.
Five metallization wafer-level packaging methods provided by the invention, all the coat of metal is formed at the lower surface of packaging body and side, form five metallized wafer-level packaging products,, when not changing area and the volume of chip as far as possible, realize the electromagnetism interference between chip, in raising encapsulation precision, there is higher integrated level and degree of integration.
More than describe and be only the preferred embodiment of the application and the explanation to institute's application technology principle.Those skilled in the art are to be understood that, invention scope involved in the application, be not limited to the technical scheme of the particular combination of above-mentioned technical characteristic, also should be encompassed in when not departing from described inventive concept, other technical scheme of being carried out combination in any by above-mentioned technical characteristic or its equivalent feature and being formed simultaneously.The technical characteristic that such as, disclosed in above-mentioned feature and the application (but being not limited to) has similar functions is replaced mutually and the technical scheme formed.
Claims (9)
1. cover brilliant film (COF) method for packing, it is characterized in that, comprising:
Chip functions district is formed multiple first metal salient point;
Flexible PCB metal level is formed multiple second metal salient point;
Described first metal salient point or described second metal salient point coat conducting resinl post;
Also be connected corresponding in opposite directions one by one to described multiple first metal salient point and described multiple second metal dots by described conducting resinl post; And
Between described chip and described flexible PCB with plastic packaging at the bottom of filler fill and form plastic-sealed body.
2. the method for packing covering brilliant film (COF) according to claim 1, it is characterized in that, also comprise chip described in pressing and described flexible PCB, make described first metal salient point and described second metal salient point apply the pressure of a vertical direction to described conducting resinl post.
3. the method for packing covering brilliant film (COF) according to claim 1, is characterized in that, described conducting resinl column material is aeolotropic conductive.
4. the method for packing covering brilliant film (COF) according to claim 1, is characterized in that, the material of described first metal salient point and described second metal salient point is metallic copper.
5. the method for packing covering brilliant film (COF) according to claim 1, is characterized in that, described first metal salient point, the second metal salient point and conducting resinl post are circular cylinder.
6. the method for packing covering brilliant film (COF) according to claim 5, is characterized in that, the axis of described first metal salient point, described conducting resinl post and described second metal salient point point-blank.
7. the method for packing covering brilliant film (COF) according to claim 6, is characterized in that, the diameter of section of described conducting resinl post is greater than the diameter of section of described first metal salient point and described second metal salient point.
8. the method for packing covering brilliant film (COF) according to claim 1, is characterized in that, coated described first metal salient point of described plastic-sealed body filler, described second metal salient point and described conducting resinl post.
9., according to the arbitrary described method for packing covering brilliant film (COF) of claim 1-8, it is characterized in that, the material of described plastic-sealed body filler is epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510906810.8A CN105551986A (en) | 2015-12-09 | 2015-12-09 | COF (Chip on Flex) packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510906810.8A CN105551986A (en) | 2015-12-09 | 2015-12-09 | COF (Chip on Flex) packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105551986A true CN105551986A (en) | 2016-05-04 |
Family
ID=55831095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510906810.8A Pending CN105551986A (en) | 2015-12-09 | 2015-12-09 | COF (Chip on Flex) packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105551986A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018218624A1 (en) * | 2017-06-01 | 2018-12-06 | 深圳市柔宇科技有限公司 | Method for pressing flexible panel and flexible circuit board and pressing equipment |
| CN112614787A (en) * | 2020-12-31 | 2021-04-06 | 合肥矽迈微电子科技有限公司 | Packaging method for chip packaging |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09266227A (en) * | 1996-03-28 | 1997-10-07 | Matsushita Electric Ind Co Ltd | How to join electronic components |
| JPH10340906A (en) * | 1997-06-06 | 1998-12-22 | Sony Corp | Surface-mount electronic part, manufacture and mounting thereof |
| JP2001015550A (en) * | 1999-04-28 | 2001-01-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2001044606A (en) * | 1999-08-02 | 2001-02-16 | Hitachi Ltd | Semiconductor package mounting structure, mounting method thereof, and rework method thereof |
| WO2001033623A1 (en) * | 1999-10-29 | 2001-05-10 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| US20020098620A1 (en) * | 2001-01-24 | 2002-07-25 | Yi-Chuan Ding | Chip scale package and manufacturing method thereof |
| CN1588635A (en) * | 2004-08-30 | 2005-03-02 | 友达光电股份有限公司 | Method and structure for detecting deformation of conductive particles of anisotropic conductive adhesive |
| CN1763937A (en) * | 2004-10-19 | 2006-04-26 | 宏齐科技股份有限公司 | Wafer-level optoelectronic semiconductor assembly structure and manufacturing method thereof |
| CN1828854A (en) * | 2005-01-26 | 2006-09-06 | 宏齐科技股份有限公司 | Manufacturing method of wafer-level optoelectronic semiconductor assembly structure |
| JP2009099669A (en) * | 2007-10-15 | 2009-05-07 | Nec Corp | Mounting structure of electronic component, and mounting method thereof |
| CN103000538A (en) * | 2011-09-14 | 2013-03-27 | 南茂科技股份有限公司 | Method for manufacturing semiconductor package structure |
| CN103151323A (en) * | 2011-12-06 | 2013-06-12 | 北京大学深圳研究生院 | Flip packaging structure based on anisotropy conductive glue |
-
2015
- 2015-12-09 CN CN201510906810.8A patent/CN105551986A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09266227A (en) * | 1996-03-28 | 1997-10-07 | Matsushita Electric Ind Co Ltd | How to join electronic components |
| JPH10340906A (en) * | 1997-06-06 | 1998-12-22 | Sony Corp | Surface-mount electronic part, manufacture and mounting thereof |
| JP2001015550A (en) * | 1999-04-28 | 2001-01-19 | Matsushita Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2001044606A (en) * | 1999-08-02 | 2001-02-16 | Hitachi Ltd | Semiconductor package mounting structure, mounting method thereof, and rework method thereof |
| WO2001033623A1 (en) * | 1999-10-29 | 2001-05-10 | Hitachi, Ltd. | Semiconductor device and its manufacturing method |
| US20020098620A1 (en) * | 2001-01-24 | 2002-07-25 | Yi-Chuan Ding | Chip scale package and manufacturing method thereof |
| CN1588635A (en) * | 2004-08-30 | 2005-03-02 | 友达光电股份有限公司 | Method and structure for detecting deformation of conductive particles of anisotropic conductive adhesive |
| CN1763937A (en) * | 2004-10-19 | 2006-04-26 | 宏齐科技股份有限公司 | Wafer-level optoelectronic semiconductor assembly structure and manufacturing method thereof |
| CN1828854A (en) * | 2005-01-26 | 2006-09-06 | 宏齐科技股份有限公司 | Manufacturing method of wafer-level optoelectronic semiconductor assembly structure |
| JP2009099669A (en) * | 2007-10-15 | 2009-05-07 | Nec Corp | Mounting structure of electronic component, and mounting method thereof |
| CN103000538A (en) * | 2011-09-14 | 2013-03-27 | 南茂科技股份有限公司 | Method for manufacturing semiconductor package structure |
| CN103151323A (en) * | 2011-12-06 | 2013-06-12 | 北京大学深圳研究生院 | Flip packaging structure based on anisotropy conductive glue |
Non-Patent Citations (5)
| Title |
|---|
| （美）刘流诚著；冯士维等译: "《低成本倒装芯片技术：DCA，WLCSP和PBGA芯片的贴装技术》", 30 April 2006, 北京化学工业出版社 * |
| Y.C. CHAN，D.Y. LUK: "Effects of bonding parameters on the reliability performance of anisotropic conductive adhesive interconnects for flip-chip-on-flex packages assembly I. Different bonding temperature", 《MICROELECTRONICS RELIABILITY》 * |
| 张军，陈旭: "各向异性导电胶粘接可靠性研究进展", 《电子元件与材料》 * |
| 李慧: "各向异性导电胶膜的导电粒子电性能研究", 《郑州大学学报(工学版)》 * |
| 王天曦，王豫明: "《现代电子工艺》", 30 November 2009, 清华大学出版社 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018218624A1 (en) * | 2017-06-01 | 2018-12-06 | 深圳市柔宇科技有限公司 | Method for pressing flexible panel and flexible circuit board and pressing equipment |
| CN112614787A (en) * | 2020-12-31 | 2021-04-06 | 合肥矽迈微电子科技有限公司 | Packaging method for chip packaging |
| CN112614787B (en) * | 2020-12-31 | 2024-05-10 | 合肥矽迈微电子科技有限公司 | Packaging method for chip packaging |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9449941B2 (en) | Connecting function chips to a package to form package-on-package | |
| US9559043B2 (en) | Multi-level leadframe with interconnect areas for soldering conductive bumps, multi-level package assembly and method for manufacturing the same | |
| US12300638B2 (en) | Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures | |
| US20040080054A1 (en) | Wiring board, semiconductor device, and process for production of wiring board | |
| KR20140126598A (en) | semiconductor package and method for manufacturing of the same | |
| US20130181359A1 (en) | Methods and Apparatus for Thinner Package on Package Structures | |
| CN103258818B (en) | For the system and method for fine pitches POP structure | |
| KR20090040841A (en) | Wiring board, manufacturing method thereof, and semiconductor device | |
| JP2012129464A (en) | Semiconductor device and method of manufacturing the same | |
| US7554197B2 (en) | High frequency IC package and method for fabricating the same | |
| US20130334673A1 (en) | Flexible power module semiconductor packages | |
| CN107154385A (en) | Stacked package structure and manufacturing method thereof | |
| CN105551986A (en) | COF (Chip on Flex) packaging method | |
| US20170077035A1 (en) | System-level packaging structures | |
| CN103281858A (en) | Printed circuit board and manufacturing method thereof, and flip-chip packaging member and manufacturing method thereof | |
| US20120168960A1 (en) | Multi chip package | |
| US10580940B2 (en) | Flexible circuits for mounting light emitting semiconductor device | |
| US20120002386A1 (en) | Method and Apparatus for Improving the Reliability of Solder Joints | |
| CN105551987A (en) | COF (Chip on Flex) packaging method | |
| CN107622981B (en) | Electronic package and manufacturing method thereof | |
| US20220216255A1 (en) | Image sensor package having inner and outer joint members | |
| CN105405825A (en) | Chip on film package structure | |
| US8461698B1 (en) | PCB external ground plane via conductive coating | |
| US20130069226A1 (en) | Semiconductor package having interposer | |
| KR101699213B1 (en) | Low profile electronic package and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
| COR | Change of bibliographic data | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160504 |