CN104917517B - For realize low-power consumption, Wide measuring range time-to-digit converter energy-saving circuit - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, in particular to an energy-saving circuit for realizing a time-to-digital converter with low power consumption and wide measurement range. The circuit is composed of a time window generating circuit and an enabling circuit; the time window generating circuit includes two flip-flops, an inverter and an AND gate, which generate corresponding The enable signal, and then drives the enable circuit to generate a corresponding data signal to enter the time-to-digital converter. The energy-saving circuit can not only greatly reduce the power consumption of the delay chain type time-to-digital converter in the subsequent stage, but also avoid the limitation of the TDC input frequency by the traditional window energy-saving circuit, so that it can realize a wide measurement range.

Description

Energy-Saving Circuits for Realizing Low-Power, Wide-Measurement-Range Time-to-Digital Converters

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to an energy-saving circuit for realizing a time-to-digital converter with low power consumption and wide measurement range.

Background technique

In recent years, with the evolution of integrated process technology and the reduction of process feature size, the signal processing method in the traditional voltage domain has been greatly challenged, while the time domain accuracy of the circuit has been continuously improved. Time-domain processing circuits and mixed-domain systems can give full play to the advantages of advanced CMOS technology, attracting more and more researchers' attention. All Digital Phase Locked Loop (ADPLL) is a typical case. With the development of CMOS technology, the performance of the all-digital phase-locked loop has been comparable to that of the traditional analog phase-locked loop. At the same time, due to the characteristics of its digital circuit, other digital auxiliary circuits can be easily added, but how to further realize low Power consumption and broadband are still the focus of research. The time-to-digital converter (Time-to-digital Converter) is one of the key modules, and its power consumption determines the total power consumption of the all-digital phase-locked loop, especially in the time-to-digital converter of the delay chain type, the delay The unit is constantly flipped under the drive of high-frequency input, which consumes additional power consumption. In order to improve power consumption, a time window energy saving circuit can be used.

Traditional time-window power-saving circuits consist of only two simple logic gates. However, since the width of the time window enable signal is determined by the total delay of the delay chain, the output frequency of the ADPLL will also be limited. In addition, using an AND gate as an enable circuit may generate wrong rising edges, resulting in errors in quantization results.

Contents of the invention

The object of the present invention is to provide an energy-saving circuit for implementing a time-to-digital converter with low power consumption and wide measurement range.

The energy-saving circuit provided by the invention for realizing the time-to-digital converter with low power consumption and wide measurement range is composed of a time window generating circuit and an enabling circuit. Among them, the time window generation circuit generates the corresponding enable signal by simultaneously detecting the rising and falling edges of the digitally controlled oscillator (DCO) output CKV, and then drives the enabling circuit to generate the corresponding data signal to enter the time-to-digital converter.

The time window generating circuit includes two flip-flops, an inverter and an AND gate. The reference clock REF is used as the data terminal of the first-level flip-flop, and the output CKV of the DCO is used as the clock terminal of the first-level flip-flop; the positive phase output of the first-level flip-flop is used as the data terminal of the second-level flip-flop, and the output CKV of the DCO is The signal after passing through the inverter is used as the clock terminal of the second-stage flip-flop; the inverting output of REF and the second-stage flip-flop is used as the input of the AND gate; the output of the AND gate is the output enable signal of the time window generation circuit .

The principle of the time window generation circuit to generate the enable signal is as follows: the first-stage flip-flop samples REF through the rising edge of CKV to obtain the first rising edge of CKV after the rising edge of REF; then inverts CKV, and the second-stage flip-flop uses CKV The negative-phase output of the first-stage flip-flop is sampled on the falling edge to obtain the first falling edge after the first rising edge of CKV; finally, the inverting output of the second-stage flip-flop is ANDed with REF to obtain the final enable signal EN. Since the width of the enable signal is determined by the CKV waveform and is no longer a fixed value, the enable signal can at least allow one period of CKV to pass regardless of the frequency of CKV.

The obtained enable signal is further used as the input of the enable circuit. The enable circuit is composed of a flip-flop and an AND gate: the enable signal EN is used as the data terminal of the flip-flop, CKV is used as the clock terminal of the flip-flop; the positive-phase output of the flip-flop and CKV are used as the input of the AND gate; the output of the AND gate That is the final output of the energy-saving circuit. Its working principle is: CKV samples EN through the trigger, and the rising edge of CKV in the time window signal can be obtained; then, the output of the trigger is ANDed with CKV itself, and finally CKV' carrying the rising edge and period information of CKV is obtained as the time Input for digitizer measurement.

The energy-saving circuit of the invention can not only greatly reduce the power consumption of the time-to-digital converter of the delay chain type in the subsequent stage, but also avoid the limitation of the TDC input frequency by the traditional window energy-saving circuit, so that it can realize a wide measurement range.

Description of drawings

Fig. 1 Traditional time window energy-saving circuit diagram.

Fig. 2 The time window energy-saving circuit diagram in the present invention.

Fig. 3 Time waveform diagram of the energy-saving circuit. Among them, (a) Time window enable signal generation principle, (b) only use AND gate as the final output of the enable circuit, (c) use flip-flop + AND gate as the final output of the enable circuit.

Fig. 4 Simulation waveform of the energy-saving circuit module.

Figure 5. Time-to-digital converter's overall power consumption versus frequency curve.

Detailed ways

Describe below in conjunction with accompanying drawing:

As shown in Figure 1, the traditional time window energy-saving circuit uses the reference clock and its signal after total delay to construct a time window. The rising edge period in the time window can pass through, while the invalid signal outside the window cannot enter. delay chain, thereby effectively reducing the dynamic power consumption of the delay chain. It consists of only two gates, and the XOR gate is used to generate the time window as the enable terminal of the AND gate. However, since the width of the time window is determined by the total delay of the delay chain, the output frequency of the ADPLL will also be limited. In addition, using an AND gate as an enabling device may generate wrong rising edges, resulting in errors in quantization results.

As shown in FIG. 2 , it is a time window energy-saving circuit in the present invention, which generates a corresponding enable signal by simultaneously detecting the rising and falling edges of the output CKV of the DCO. It consists of a time window generating circuit and an enabling circuit. The time window generation circuit includes two flip-flops, an inverter and an AND gate. Its working principle is: after the rising edge of REF arrives, it detects the first falling edge after the first rising edge of CKV, thereby passing the AND REF phase and get the final enable signal EN. The width of the enable signal is determined by the CKV waveform and is no longer a fixed value. Therefore, regardless of the frequency of CKV, the enable signal can at least allow half a cycle of CKV to pass. On the other hand, instead of simply using an AND gate as an enable circuit, a flip-flop is added to avoid the generation of wrong rising edges.

Figure 3 shows the time waveform diagram of the energy-saving circuit. Because the EN signal will change from high level to low level at the falling edge of CKV, only CKV in one valid period enters the subsequent quantizer. When the rising edge of REF arrives, the EN signal becomes high level, and the TDC starts to measure; when the EN signal becomes low level, the TDC stops working. It can also be seen from Figure 3(b) that when only the AND gate is used, an erroneous rising edge will be generated, resulting in an error in the quantization result. After adding a flip-flop in Figure 3(c), the accurate rising edge of CKV can be obtained by using the CKV sampling enable signal EN; the function of the AND gate is to generate the cycle of CKV to ensure that the final decimal point can be obtained frequency ratio. By adopting such an energy-saving circuit, a strobe signal CKV_P including rising edge time information and CKV period information is finally obtained.

Next, take a time-to-digital converter applied to 1.2GHz~1.8GHz broadband ADPLL as an example to observe the function and performance of the energy-saving circuit.

Figure 4 is a functional simulation of the energy-saving circuit. It can be seen from the figure that the time-window energy-saving circuit filters out the redundant CKV cycle, leaving only one cycle signal that needs to participate in subsequent quantization, thereby greatly saving power consumption. The figure also shows that CKV has added path delay after passing through the energy-saving circuit. Correspondingly, the same path delay should be added to REF, which is basically consistent.

Figure 5 considers the power consumption of the entire time-to-digital converter system. In order to reflect the function of the window energy-saving circuit, the energy consumption of the time-to-digital converter with or without the energy-saving circuit is simulated respectively, and finally a comparison chart of the two results is obtained. The upper broken line in the figure indicates the power consumption without adding the window energy-saving circuit, and the lower broken line indicates the power consumption with the added window energy-saving circuit. The power consumption simulation is to sweep the working frequency of 1.2-1.8GHz at 0.05GHz, and the time interval of measurement is 400ps. It can be found from Figure 5 that the power consumption represented by the broken line above increases with the increase of frequency. This is because no window energy-saving circuit is added, and all data cycles enter the time-to-digital converter. The higher the frequency, the opposite The more times the phaser flips, the greater the total power consumed. The lower broken line with the window energy-saving circuit added, although slightly increased, the power consumption of different input frequencies is basically the same. Comparing the two broken lines, the addition of the window energy-saving circuit greatly reduces the power consumption, and the higher the frequency, the more the power consumption is saved. When the input is 1.8GHz, the power consumption is almost reduced to 50% of the original.

Claims (2)

1. a kind of be used to realize low-power consumption, the energy-saving circuit of Wide measuring range time-to-digit converter, it is characterised in that by the time Window generation circuit and enabled circuit are formed；Wherein, time window generation circuit is by detecting the output of digital controlled oscillator simultaneously CKV rise and fall along producing corresponding enable signal, and then drive enabled circuit produce corresponding data-signal enter it is fashionable Between digital quantizer；

The time window generation circuit includes two-stage trigger, a phase inverter and one and door；Reference clock REF conducts The data terminal of first order trigger, the clock end of the output CKV of digital controlled oscillator as first order trigger；First order trigger Positive export data terminal as second level trigger, the output CKV of digital controlled oscillator is used as by the signal after phase inverter The clock end of second level trigger；The reversed-phase output of reference clock REF and second level trigger is as the input with door；With door Output be time window generation circuit output enable signal；

The enabled circuit is made up of a trigger and one with door；Data terminals of the enable signal EN as trigger, numerical control Clock ends of the output CKV of oscillator as trigger；Trigger positive output and digital controlled oscillator output CKV as with The input of door；Output with door is the final output of energy-saving circuit.

2. energy-saving circuit according to claim 1, it is characterised in that：

The process that time window generation circuit produces enable signal is as follows：First order trigger samples REF by CKV rising edge Obtain the rising edge of first CKV after REF rising edges；Then anti-phase to CKV, second level trigger is sampled with CKV trailing edge The positive of first order trigger exports to obtain first trailing edge after first rising edge of CKV；Final second level trigger Reversed-phase output and REF phases and obtain final enable signal EN；

Obtained enable signal is further used as being the input for enabling circuit：CKV samples EN by trigger, obtains time window CKV rising edges in signal；Then, trigger is exported with CKV in itself mutually with finally giving and carrying CKV rising edges and cycle letter The CKV ' of breath, the input as time-to-digit converter measurement.