CN103227639B - A kind of phase detecting circuit for time-to-digit converter - Google Patents

Abstract

The invention provides a phase detection circuit for a time-to-digital converter. The phase detection circuit adds a rising edge detection circuit to the traditional phase detection circuit, and the rising edge detection circuit samples the continuous high level twice in a row to obtain a pulse with a unit clock width, so that the subsequent decoding circuit 32 Only one of the input ports is at a high level at any time, thereby reducing the design difficulty of the decoding circuit, reducing the area of the circuit, and improving the performance of the circuit and the accuracy of the time-to-digital conversion. The phase detection circuit of the invention is very simple and easy to implement, and has good application prospects.

Description

A phase detection circuit for time-to-digital converter

technical field

The invention belongs to the field of integrated circuit design, in particular to a phase detection circuit for a time-to-digital converter.

Background technique

Time Digital Converter (TimeDigitalConverter, TDC) is a commonly used circuit for time measurement. It mainly calculates the time from the reference signal to the occurrence of the event and the time interval between two pulses, and directly converts the time interval into a high-precision digital value. And realize the digital output. At present, it has been widely used in the electronic field, such as in the all-digital phase-locked loop ADPLL, to improve the time characteristics of its test devices and signals. In recent years, the most concerned TDC is the structure using high-speed CMOS digital circuits, the main reason is that the signal to be tested can achieve high time accuracy. Research on the accuracy of TDC will benefit the application and quality assurance of TDC.

Figure 1 is a traditional time-to-digital converter structure used in ADPLL, which mainly includes the following parts: 32 D flip-flops, 32 phase detection modules, two 5-bit decoders, and a 5-bit Adders, a 6-bit counter and some OR gates. The following briefly introduces the working principle of TDC:

(1) Measuring principle of pulse width

32 D flip-flops sample the phase difference pulse signal PUL, and the clock controlling the sampling of the 32 D flip-flops is provided by an external circuit ring oscillator (Free-RunningRingOscillator, FRO), and FRO provides 32 samples with a constant phase difference Clock signal, the time interval between two consecutive sampling clocks is △, if the phase difference PUL signal is at a high level at the rising edge of the sampling clock, the value collected by the corresponding D flip-flop is "1". There will be a D flip-flop to sample the PUL every time interval of △, and the number of "1" collected can be used to represent the pulse width of the PUL signal. If the input Q _N-1 Q _N Q _N+1 of the phase detection module = 011, it means that the rising edge of PUL arrives, and the corresponding phase detection module will use a signal to record the sampling clock number "n" at this time. When Q _M-1 Q _M Q _M+1 =100, it means that the falling edge of PUL arrives, then the corresponding phase detection module also uses a signal to record the "m" at this time. The logic module inside will be divided into two parts to record the number of "1"s between the two edges. The first part records the number r of "1" sampling clock signals at the rising edge of the PUL; the second part records the rising edge of the PUL. The difference between the sampling clock position and the falling edge position is (mn). The total number of "1" is the sum of the two parts, that is, the width of the PUL high level is (r+mn)△.

(2) Time-to-digital conversion principle:

First encode the start position recording signal s and the end position recording signal e generated by the phase detection module, and then use an adder to calculate the difference to complete the second part of the calculation mentioned above. And the current recording signal c is used to trigger a counter to obtain the first part of the calculation. But it should be noted that a "1" of the counter triggered by c at this time represents 32, so it is used as the upper 5 bits of the last binary number. The last two parts are combined to obtain the required binary number converted from time to number.

Figure 2 shows the structure of the traditional TDC internal phase detection circuit. When the TDC is working, when the rising edge of the phase pulse signal PUL arrives, the input signal ABC=011 of the phase detection module, and the T flip-flop 2 will be activated under the corresponding clock control signal. Generate a continuous high-level signal s, and record the rising edge of the corresponding phase pulse signal; similarly, when the falling edge of the phase pulse signal PUL arrives, the input signal ABC=100 of the phase detection module, T flip-flop 3 in the corresponding A continuous high-level signal e will be generated under the clock control signal, and the falling edge of the corresponding phase pulse will be recorded. The corresponding high level will continue until the next phase pulse signal PUL arrives and is detected again by the phase detection module, and the high level will change to low level. In this case, for the input of the subsequent decoding circuit (s[31:0] or e[31:0]), there will be multiple high levels at the same time, which will bring more complicated input situations, so It will bring design and programming difficulties to the digital decoding circuit, increase the area of the circuit, and affect the accuracy of time-to-digital conversion.

Contents of the invention

The invention aims at the deficiencies of the prior art, especially the problem that the output signal of the phase detection circuit of the existing time-to-digital converter continues to be at a high level, and proposes a phase detection circuit for the time-to-digital converter. The output signal of the circuit is a pulse with a unit clock width, thereby reducing the design difficulty of subsequent decoding circuits.

In order to solve the above technical problems, the present invention adopts the following technical solution: a phase detection circuit for a time-to-digital converter, the phase detection circuit is added with a rising edge detection circuit at the output end of the existing time-to-digital converter phase detection circuit, The rising edge detection circuit performs rising edge sampling on a continuous high level, and then generates a pulse signal with a unit clock width, so that the design of the subsequent decoding circuit becomes simpler, thereby reducing the area of the circuit, and realizing A function for time-to-number conversion.

The rising edge detection circuit includes three D flip-flops, a NOT gate and an AND gate; under the control of the clock signal, the first D flip-flop samples the input rising edge signal, and the second D flip-flop samples the first D flip-flop. The output signal of the flip-flop is sampled, the third D flip-flop samples the output signal of the second D flip-flop, the output signal of the third D flip-flop is input to the AND gate together with the output signal of the second D flip-flop after being inverted by the NOT gate, and the AND gate The output signal is a pulse with a unit clock width.

The beneficial effects of the invention are: the invention provides a phase detection circuit for a time-to-digital converter. The phase detection circuit adds a rising edge detection circuit to the traditional phase detection circuit, and the rising edge detection circuit samples the continuous high level twice in a row to obtain a pulse with a unit clock width, so that the subsequent decoding circuit 32 Only one of the input ports is at a high level at any time, thereby reducing the design difficulty of the decoding circuit, reducing the area of the circuit, and improving the performance of the circuit and the accuracy of the time-to-digital conversion. The phase detection circuit of the invention is very simple and easy to implement, and has good application prospects.

Description of drawings

Figure 1 is the structure of a traditional TDC.

Figure 2 is a phase detection circuit in a traditional TDC structure.

Figure 3 is a circuit structure in which a rising edge detection module is added to a traditional phase detection circuit.

Figure 4 is the structure of the rising edge detection module.

Figure 5 is a simulation waveform diagram of the rising edge detection module.

Fig. 6 is the simulation waveform of the time-to-digital converter with improved phase detection circuit.

Fig. 7 is the simulation waveform of the result of the whole time digital converter.

detailed description

A phase detection circuit for a time-to-digital converter of the present invention will be further specifically described below in conjunction with the accompanying drawings.

As shown in Figure 3, a phase detection circuit for a time-to-digital converter of the present invention adds a rising edge detection circuit to the traditional phase detection circuit: the input signals A, B, and C are three continuous phase sampling signals, which are passed through the traditional phase detection circuit Generate the corresponding pulse current record signal c, pulse start position record signal S, and pulse end position record signal E, but at this time the S record signal and E record signal are continuous rising edge signals, and they are sent to two identical structures The rising edge detection module of the corresponding pulse start position recording signal s and end position recording signal e of the unit clock width.

Figure 4 is the structure diagram of the rising edge detection circuit. Its working principle is: the D flip-flop 1 samples the rising edge UP signal under the control of the clock, and outputs the UP_1 signal, and the D flip-flop 2 samples the UP_1 signal, and outputs For UP_2, D flip-flop 3 samples the UP_2 signal, and the output is UP_3; UP_3 is inverted and then ANDed with UP_2, connected to an AND gate, and the output of the AND gate is Reg_UP signal, which is a pulse width of a unit clock width. Waveform simulation diagram shown in Figure 5 .

The working process of the whole new phase detection module is: when the rising edge of the phase pulse arrives, that is, the input signal ABC=011, the AND gate 1 outputs a high level "1", which is sent to T flip-flop 1 and T flip-flop 2, so that the outputs of these two T flip-flops become "1" at the next falling edge of the clock signal. This situation means that, when jumping from low level to high level, the S signal becomes a high level logic "1", and after the continuous high level S passes through the rising edge detection module, a pulse with a unit clock width will be generated The signal s represents the detection of the starting position of the phase pulse; when the falling edge of the phase pulse arrives, ABC=100, the output of the T flip-flop 3 will jump to a high level when the rising edge of the next clock signal arrives, and the E signal will also Change to high level, after the continuous high level E passes through the rising edge detection module, a pulse signal e with a unit clock width will also be generated, which means that the phase end position is detected.

Figure 6 is a waveform simulation diagram of the application of the new phase detection module in the time-to-digital converter, as shown in the figure: after the arrival of the phase pulse signal PUL, its rising edge is detected by the 26th D flip-flop (D in Figure 1 Flip-flop 25) is detected, then S will generate a continuous high level from low to high, which is sent to the rising edge detection module, so that it is sampled by three consecutive D flip-flops, and then a pulse signal s with a unit clock width is obtained , representing the starting position of the PUL to be recorded.

Figure 7 is the simulation result diagram of the whole time digital converter, PUL is the phase difference pulse signal, Out[10:0] is the output size of the whole TDC, which is the binary number representation of the phase pulse signal width. In the simulation waveform diagram, the continuous sampling clock interval △=62.5ns, the actual width of the first PUL PULs=3750ns, and the tested width PULc=60×62.5ns=3750ns, that is, PULc=PULs.

In summary, the phase detection circuit for a time-to-digital converter provided by the present invention can convert the continuous high level into a pulse signal with a unit clock width by adding a rising edge detection circuit behind the traditional phase detection circuit, which is more convenient The start position and end position of the phase pulse signal can be accurately recorded, thereby reducing the design of the subsequent decoding circuit, reducing the area of the circuit, and improving the accuracy of the time-to-digital conversion.

For those skilled in the art, other advantages and variants can be easily ascertained based on the above implementations. Therefore, the present invention is not limited to the above-mentioned specific examples, which are merely used as examples to describe in detail and exemplary one form of the present invention. Within the scope of not departing from the gist of the present invention, technical solutions obtained by those skilled in the art through various equivalent replacements based on the above specific examples shall be included in the scope of the claims of the present invention and their equivalent scope.

Claims (1)

1. A phase detection circuit for a time-to-digital converter, characterized in that, the phase detection circuit is to add a rising edge detection circuit at the output end of the existing time-to-digital converter phase detection circuit, and the rising edge detection circuit , to sample the rising edge of a continuous high level, and then generate a pulse signal with a unit clock width; The rising edge detection circuit includes three D flip-flops, a NOT gate and an AND gate; under the control of the clock signal, the first D flip-flop samples the input rising edge signal, and the second D flip-flop samples the first D flip-flop. The output signal of the flip-flop is sampled, the third D flip-flop samples the output signal of the second D flip-flop, the output signal of the third D flip-flop is input to the AND gate together with the output signal of the second D flip-flop after being inverted by the NOT gate, and the AND gate The output signal is a pulse with a unit clock width.