CN111884631A - A Digital Pulse Width Modulation Module Using Hybrid Structure - Google Patents

Abstract

The invention discloses a digital pulse width modulation module based on an ASIC design process, which belongs to the field of electronic technology and mainly includes two parts: a Sigma-Delta modulator and a Core DPWM. The Core DPWM consists of a count-compare module, a delay chain and an RS flip-flop. The Sigma-Delta modulator uses noise shaping technology to extend the effective resolution of the Core DPWM module. The delay chain consists of an adjustable delay unit and a multiplexer in series, and a calibration block controls the total delay of the delay chain to be about one clock cycle. The invention uses a variety of structures to form a mixed structure, avoids various shortcomings of a single structure when implementing a high-resolution DPWM module, has the advantages of high linearity, small area, low power consumption, easy modification, and is extremely portable. sex.

Description

A Digital Pulse Width Modulation Module Using Hybrid Structure

technical field

The invention relates to a digital pulse width modulation circuit, the generated modulation signal can be applied to switching power supply, direct current motor control, etc., and belongs to the field of electronic technology.

Background technique

Due to the inherent shortcomings of analog circuits, such as difficult design, poor portability, and device performance easily affected by process errors, operating voltage, and ambient temperature, with the development of integrated circuits, traditional analog pulse width modulation (Analog Pulse Width Modulation, APWM) Gradually move towards digital pulse width modulation (Digital Pulse Width Modulation, DPWM). However, compared with APWM, DPWM still has a certain gap in resolution, linearity and switching frequency. How to improve these three indicators is the key point to be considered when designing DPWM.

There are three basic DPWM structures: count-compare, delay chain, and ring oscillator. The count-comparison type has high linearity, but requires a very high clock frequency to achieve high resolution; the delay chain type has the same switching frequency as the input clock frequency, but consumes a lot of chip area to achieve high resolution, and the linearity is higher. Poor; the principle of the ring oscillator type is similar to that of the delay chain, no external clock input is required, and the area consumption is smaller than that of the delay chain type, but the starting frequency is difficult to control.

Due to the limitations of a single structure, it is difficult to use limited design resources to meet the requirements of design indicators. Therefore, when implementing a high-resolution DPWM module, a hybrid structure is usually used, the advantages of different basic structures are used, and a calibration module is added to reduce the influence of process deviation, operating voltage and ambient temperature. At the same time, algorithms such as digital jitter and Sigma-Delta modulation can be appropriately used to further improve the effective resolution of the DPWM module.

SUMMARY OF THE INVENTION

In order to overcome the shortcomings of low precision and poor linearity of the existing DPWM module, the present invention proposes a hybrid digital pulse width modulation circuit suitable for the ASIC process. High portability. The technical scheme adopted by the present invention is as follows: a digital pulse width modulation circuit is proposed, including: a Sigma-Delta modulator, a counting-comparison module composed of a counter and a comparator, and a delay chain composed of an adjustable delay unit and a calibration module , and RS flip-flops. Among them, the count-comparison module and the delay chain are combined into a Core DPWM module with a 9-bit resolution achieved by hardware, and then the Sigma-Delta modulator is used to increase the effective resolution to 12-bit through noise shaping technology. All modules work under the unified clock source clk.

The Sigma-Delta modulator uses second-order Sigma-Delta modulation. After receiving the externally input 12-bit control signal DPWM_duty[11:0], it is converted into a 9-bit output signal D[8] through noise shaping technology: 0], suppress the quantization noise, and pass it to the count-compare block in the Core DPWM block.

The counting-comparison module is composed of a 6-bit wide counter and a comparator, the counter counts according to the clock signal clk, and generates an internal counting signal cnt[5:0]; the high 6-bit D of the comparator and the duty cycle signal [8:3] and the count signal cnt[5:0] are connected. The count-compare module generates the set signal Set of the RS flip-flop and the input signal dlyclk of the delay chain.

The delay chain is composed of 8-stage adjustable delay units connected in series to delay the input signal dlyclk, and the ideal total delay time is the period T of the clock clk. The output of each delay unit is connected to the input of the 8-to-1 multiplexer, the selection signal of the multiplexer is connected to the lower 3 bits D[2:0] of the duty cycle signal, and the final multiplexer The output signal is sent to the RS flip-flop as the reset signal Reset. The calibration module performs phase detection on the input signal dlyclk and the output signal dlyclk_net8 of the eighth-stage delay unit, generates a calibration signal fix[5:0] according to the phase difference, and connects with all adjustable delay units to adjust the delay.

The adjustable delay unit uses the clock buffer and multiplexer of the standard cell library to form the structure of FIG. 5, and through the calibration signal fix[5:0], the path between the input signal IN and the output signal OUT can be changed, and then Select the desired delay time.

The calibration module detects the total delay time of the delay chain. When the falling edge of the input signal dlyclk arrives later than the rising edge of the input signal dlyclk_net8, it means that the delay time is less than one clock cycle, and the calibration signal fix[5:0] Increase the actual delay of the delay unit; when the falling edge of the input signal dlyclk arrives earlier than the rising edge of the input signal dly_clk_net8, the delay time is greater than one clock cycle, and the calibration is over.

The RS flip-flop generates a corresponding DPWM output signal according to the input set signal Set and reset signal Reset.

Compared with the traditional DPWM structure, the present invention has the advantages of high linearity, small area, low power consumption, easy modification and strong portability. A hybrid structure including count-compare structure and delay chain is adopted, the structure based on PLL/DLL phase shift is abandoned, and a second-order Sigma-Delta modulator is added, which is suitable for ASIC-based design flow. The delay chain is built with the devices of the standard cell library, which is easy to be transplanted when the process is replaced; the matching calibration module is designed to ensure that the total delay time of the delay chain is approximately equal to one clock cycle, which can change the process error, operating voltage and ambient temperature. The resulting delay variation is calibrated to some extent. The second-order sigma-delta modulator further improves the resolution through noise shaping technology, and only needs to adjust the bandwidth of the pre-compensator to achieve the ideal effective number of bits.

Description of drawings

Figure 1 is the overall block diagram of the DPWM module.

Figure 2 is a z-domain modeling of a second-order sigma-delta modulator.

Figure 3 is a block diagram of the Core DPWM structure composed of a count-compare module and a delay chain.

Figure 4 is a block diagram of a count-compare module.

Fig. 5 is the internal structure diagram of the adjustable delay module.

FIG. 6 is an internal structure diagram of the calibration module.

Figure 7 is a state transition diagram of the calibration state machine.

Figure 8 is the working waveform diagram of Core DPWM.

Figure 9 is a statistical graph of the delay chain delay time after calibration under different process corners.

Detailed ways

In order to explain the solution of the present patent more clearly, the following will take the 12-bit resolution hybrid DPWM module in this embodiment as an example, and describe in detail with reference to FIGS. 1 to 9 .

Referring to FIG. 1, the DPWM module of the present invention includes two parts. The external Sigma-Delta modulator converts the 12-bit original duty cycle control signal DPWM_duty[11:0] into a 9-bit control signal D[8:0] through noise shaping technology, and transmits it to the subsequent stage 9 -bit resolution Core DPWM module, the resolution of Core DPWM is completely realized by hardware. All synchronous circuits all work under the unified clock clk. In this embodiment, the frequency of the clock clk is 100 MHz.

The Sigma-Delta modulator used in this embodiment adopts second-order Sigma-Delta modulation, and its z-domain model is shown in FIG. 2 . The signal Y(z) is equivalent to superimposing a quantization noise E(z) after passing through the bit truncator. The feedback loop feeds back the output signal V(z) of the low significant number of bits to the input, which is equivalent to integrating and superimposing the quantization error. On the input signal U(z), the output signal V(z) at the next moment is generated, and the z-domain equation of this process is shown in equation (1):

V(z)=U(z)+(1-2z ^-1 +z ^-2 )E(z)

Among them, the transfer function of the input signal is 1, and the transfer function of the quantization noise is shown in formula (2):

E(z)=1-2z ^-1 +z ^-2 =(1-z ^-1 ) ^-2

When the frequency is low, the transfer function of the quantization noise is much smaller than 1, the quantization noise is suppressed, and the high-resolution input signal is hardly changed, and the output signal is approximately equal to the input signal. Although the frequency of the system cannot always be zero, quantization noise will inevitably be introduced, but the second-order Sigma-Delta modulation module has effectively suppressed the low-frequency quantization noise and can be used to increase the number of bits of resolution.

The structure of the Core DPWM module is shown in Figure 3. Among them, the high 6-bit resolution is realized by a count-comparison structure, and the low 3-bit resolution is realized by a delay chain of 8 adjustable delay units in series. The count-comparison structure is shown in Figure 4, rst_n is a global reset signal, the counter is a 6-bit binary counter, and the generated internal count signal cnt[5:0] is connected to an input port of the comparator. The other input port of the comparator is connected with the upper 6 bits D[8:3] of the duty cycle signal, and its output signal is dlyclk sent to the delay chain and Set sent to the set end of the RS flip-flop. The outputs of all adjustable delay elements in the delay chain are connected to different inputs of the 8-to-1 multiplexer with a total delay time of one clock cycle, the lower 3 bits of the duty cycle signal D[2:0] As the selection signal of the multiplexer, the input signal is 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 or 8/8 by gating different paths phase shift of clock cycles. The delay chain is equipped with a special calibration module, which changes the delay of the adjustable delay unit through the calibration signal fix[4:0] to ensure that the total delay time is close to one clock cycle.

The internal structure of the adjustable delay unit in this embodiment is shown in FIG. 5 . All devices are standard units in the SMIC 130nm process library, including 2 CLKBUFX4, 1 CLKBUFX8, 17 CLKBUFX12 and 15 multiplexers CLKMX2X4. Compared with the general buffer, the clock tree buffer has the characteristics of balanced rising edge transition time and falling edge transition time, and the large-sized device not only has low propagation delay, but also has a small change in propagation delay when the PVT changes. 15 CLKBUFX12s are used as the amount of variation during calibration; in order to make the working environment of CLKBUFX12 approximately the same, three units are inserted as buffers in the front stage, cascaded according to the driving capability from small to large, and dummy cells are added at the end to match the output load; 15 CLKMX2X4 form a 16-to-1 multiplexer, and the final output signal is buffered by CLKBUFX4 to prevent timing deterioration due to insufficient drive capability of the multiplexer. The basic delay in this structure is the total delay of 2 CLKBUFX2, 1 CLKBUFX8, 1 CLKBUFX12 and 4 CLKMX2X4, which needs to be less than one clock cycle T; at the same time, the total delay of all standard cells should be greater than one clock cycle T. All output signals of the CLKBUFX12 used for calibration are connected to the input of the 16-to-1 multiplexer, and the calibration signal fix[4:0] selects a path with a delay time closest to the ideal value among the 16 paths. In this embodiment, the propagation delay of the clock buffer CLKBUFX12 is about 0.07ns, so the minimum delay increment of the delay unit after each adjustment is 0.07ns, and the minimum increment of the total delay time of the delay chain is 0.56ns.

The structure of the calibration module in the present invention is shown in FIG. 6 , which performs phase detection on the input signals dlyclk and dlyclk_net8, including four parts: a digital phase detector, a reset module, a clock generation module and a calibration state machine. dlyclk_net8 is the output of the 8th adjustable delay unit; rst_n is the global reset signal of the system; fix_en is the externally input calibration enable signal. When the high level is high, the calibration module can work normally and perform delay calibration; fix[4:0] is The output signal of the calibration module is used to adjust the delay time of the delay unit. If the total delay time of the delay chain is less than one clock cycle, the falling edge of the signal dlyclk arrives later than the rising edge of the signal dlyclk_net8, the outputs of the registers DFF1 and DFF2 will keep 2'b01 for a period of time, and then change to 2'b11, the internal signal The flag is always kept at 0, and the reset path is gated. When the falling edge of the signal dlyclk_net8 arrives, the registers DFF1, DFF2, DFF3, and DFF4 are reset. The clock generation module can normally detect the phase difference between the falling edges of the two signals and use it as a clock signal fix_clk output, the calibration state machine performs state transition; if the total delay time of the delay chain is greater than one clock cycle, the falling edge of the signal dlyclk arrives earlier than the rising edge of the signal dlyclk_net8, and the outputs of the registers DFF1 and DFF2 will remain 2' for a period of time b10, then changed to 2'b11, the internal signal flag is set to 1, the reset path is turned off, the registers DFF1, DFF2, DFF3, DFF4 cannot be reset, and the flag signal turns off the clock generation module. The path to the calibration state machine , the fix_clk signal remains low, and the calibration state machine no longer performs state transitions.

The state transition diagram of the calibration state machine is shown in Figure 7. When the rising edge of the clock signal fix_clk arrives, the calibration state machine performs state transition. Except for reset, the rest of the state transitions are irreversible, and the calibration module only has the effect of increasing the delay time. When the system is reset, the delay time of the adjustable delay unit corresponding to the state state_0 is the smallest. At this time, the total delay of the delay chain should be less than one clock cycle; until the delay time of the delay chain is slightly greater than one clock cycle, the clock signal fix_clk starts to remain low. level, the calibration state machine remains unchanged, and the calibration ends. Theoretically, the maximum error caused by this calibration method under the Typical process angle is the minimum delay increase of the adjustable delay unit multiplied by the number of series stages of the delay chain, which is 0.56ns in this embodiment.

The working waveform of the Core DPWM module is shown in Figure 8. After the external clock signal is input, the count-comparison module starts to work. When the count signal cnt[6:0] is 0, the output port Set will maintain a high level for one clock cycle, and the output of the RS flip-flop is set to 1, resulting in The rising edge of the PWM wave; when the count signal is equal to the upper 6 bits D[8:3] of the duty cycle signal, the output port dlyclk will maintain a high level for one clock cycle, and the signal will be sent to the delay chain, by the count- The 6bit coarse adjustment realized by the comparison structure ends; after the dlyclk signal enters the delay chain, the 8-to-1 multiplexer selects the corresponding channel according to the lower 3 bits D[2:0] of the duty cycle signal, and the obtained output signal Reset It will be sent to the reset terminal of the RS flip-flop to reset it, and the falling edge of the PWM wave will be generated. The 3-bit fine adjustment realized by the delay chain structure ends, and the Core DPWM module hardware realizes 9-bit resolution. Combined with the second-order Sigma-Delta modulator to form the hybrid DPWM module shown in Figure 1, the effective resolution can be increased to 12-bit by sacrificing a small area and power consumption.

Figure 9 shows the statistics of the delay chain delay time after calibration under different process corners. It can be seen that in the typical and fast process corners, the actual delay time is not much different from the ideal delay time; in the slow process corner, due to the degradation of device performance, the minimum step of each calibration increases, resulting in the delay time after completion of calibration. more than the ideal value. However, the operating temperature is 125°C, the process makes the delay of the MOS tube increase, and the operating voltage drops to 1.08V. It is an extreme situation. Like the fast_1v32cm40 process angle, it is to test whether the chip can work normally under extreme conditions. The left and right endpoints of the (μ-3σ, μ+3σ) interval in the state distribution, in most cases, the chip still works near the typical process corner. Therefore, the delay chain can be considered to meet the expected design specifications.

The above embodiments should be understood as only for illustrating the present invention, rather than for limiting the protection scope of the present invention. After reading the content of the present invention, those skilled in the art can propose various modifications to the solution of the present invention according to the methods and technical contents disclosed above, and these equivalent changes and modifications are also included in the scope defined by the claims of the present invention .

Claims (7)

1. A digital pulse width modulation module using a hybrid architecture, comprising: and a Core DPWM module with lower resolution is realized by using a basic counting-comparing structure and a delay chain, resolution expansion is carried out by using a noise shaping technology of a Sigma-Delta modulator, and all sequential logics use the same clock source clk.

2. The Sigma-Delta modulator of claim 1, wherein: the number of bits of the input signal is larger than that of the output signal, and quantization noise is suppressed internally through first-order Sigma-Delta modulation or high-order Sigma-Delta modulation.

3. The Core DPWM module of claim 1, wherein: the internal part comprises a delay chain, a counting-comparing module and an RS trigger, and the DPWM structure is realized by using a pure hardware mode.

4. The count-compare module of claim 3, wherein: the delay chain circuit comprises a counter and a comparator, when the value of the counter is 0, the set signal of the RS trigger is output, and when the value of the counter is equal to the other input signal of the comparator, the input signal required by the delay chain is output.

5. The delay chain of claim 3, wherein: the adjustable delay unit is connected in a multi-stage series connection mode, the output ends of all the adjustable delay units are connected with the input end of the multiplexer, the multiplexer gates one path according to a control signal to output, and a reset signal of the RS trigger with a specific delay requirement is generated.

6. An adjustable delay unit as claimed in claim 5, wherein: the standard cell library can be realized by using a delay device, a clock buffer and a multiplexer of the standard cell library, but not limited to the standard cells; the standard units are connected in series, the output end of each device is connected with the input end of the multiplexer, and the calibration signal controls the actual delay of the adjustable delay unit through the path of the gating multiplexer.

7. The calibration module of claim 5, wherein: the identification of delay time is completed by detecting the jump edge of an input signal through a digital phase discrimination structure, and when the delay time is less than one clock cycle, a calibration state machine in the digital phase discrimination structure enters the next state to increase the delay; when the delay time is slightly longer than one clock cycle, the internal calibration state machine remains unchanged.

Images