CN102394643A - Digital pulse width modulator based on digital delayed-locked loop (DLL) - Google Patents

Abstract

The invention discloses a digital pulse width modulator based on a digital delay phase-locked loop, which includes a frequency dividing circuit, a DLL oscillating loop circuit, a clearing signal generating circuit and a PWM output logic circuit, and the DLL oscillating loop utilizes an input high-frequency clock signal f _s triggers the oscillating ring oscillation output 2 ^(mn) signals into the clear signal generation circuit, and the clear signal generation circuit combines the input f _s and the mbits duty ratio command signal to generate the pulse signal PWM_clr, and the PWM output logic of the subsequent stage Under the action of the circuit, a PWM signal is generated as the output of the system. Wherein the DLL oscillating ring circuit uses a programmable delay unit to track the input signal in real time, so as to achieve the effect of outputting a very good pulse width modulation waveform under different process angles and different working environments. The present invention greatly reduces the The area required by the chip saves the cost of chip development.

Description

A Digital Pulse Width Modulator Based on Digital Delay Locked Loop

technical field

The invention relates to a digital pulse width modulation circuit (DPWM) of a digitally controlled switching power supply, in particular to a digital pulse width modulator based on a digital delay-locked loop used in a digitally controlled switching power supply circuit whose output voltage can be adjusted in real time. Electronic technology field of integrated circuit design.

Background technique

The switching power supply with digital feedback control can significantly improve the performance of the system. The digital control method is flexible and changeable, and complex control algorithms can be realized, and the sensitivity to changes in external conditions is low. Therefore, more and more digital control switching power supplies are applied to SoC systems to provide high-quality power supply voltages, which in turn put forward higher requirements for power supplies.

The smaller and smaller power supply ripple means that the quantization accuracy of the quantizer in the control loop is getting higher and higher, that is, the quantizer has high resolution. And in order to eliminate the unique output limit cycle oscillation caused by the mismatch of quantization resolution in the digital control loop, the DPWM quantizer is also required to have high resolution. In addition, dynamic voltage modulation (DVS, Dynamic Voltage Scale) technology is often used in SoC systems, which can change the required power supply voltage and operating frequency value according to different load conditions, thereby reducing the total power consumption of the system. As for the switching power supply, it means that the value of the output voltage can be converted in real time according to the external control command. This also puts forward higher requirements on the instantaneous response speed of the power supply.

In the existing digital pulse width modulator scheme, the requirement of high resolution often leads to too high circuit area or clock operating frequency. Usually, DPWM with a counting comparison-delay line hybrid structure is used to trade off the circuit area and clock frequency. middle. The hybrid DPWM circuit divides the duty cycle command signal that needs to be modulated into a coarse adjustment part and a fine adjustment part, which work together on the RS flip-flop at the output end to control the size of the final duty cycle signal. However, when the process and environmental conditions change, the adjustment oscillation frequency drift and adjustment nonlinearity of the hybrid DPWM are fatal shortcomings. At this time, a delay-locked loop (DLL) DPWM is introduced. The DPWM of this structure solves the problem of output The disadvantage of frequency drift also greatly improves the linearity of PWM adjustment, which greatly improves the performance index of the system. DLL DPWM is divided into two types: analog DLL DPWM and digital DLL DPWM, the latter is used in this design. Compared with analog DLL DPWM, the biggest advantage of digital DLL DPWM is that it can be adjusted flexibly, and complex algorithms can be easily adopted to achieve better performance. In addition, it is easy to update and maintain, and has a long life. List advantages, the circuit structure adopted by the programmable logic unit in the original digital DLL DPWM will make the chip area very large, it is difficult to meet the requirements of practical applications, this design uses a simplified programmable delay unit circuit model, reducing The system area is small and the cost of system development is saved.

Contents of the invention

The invention provides a digital pulse width modulator based on a digital delay phase-locked loop. On the basis of maintaining the advantages of no frequency drift and good linearity in the original digital DLL DPWM scheme, a simplified programmable delay unit structure is adopted. , which solves the problem that the required area is too large.

The technical scheme adopted in the present invention is: a digital pulse width modulator based on a digital delay phase-locked loop, comprising a frequency division circuit, a DLL oscillation ring circuit, a clearing signal generation circuit and a PWM output logic circuit, characterized in that:

The frequency division circuit includes a counter and a comparator. The clock signal input terminal of the counter is connected to the system clock, the reset signal input terminal of the counter is connected to the system reset signal, the output of the counter is connected to one input terminal of the comparator, and the other input terminal of the comparator terminal grounding;

The clearing signal generation circuit includes a comparator, a selector and a two-input AND gate. One input terminal of the comparator is connected to the output of the counter in the frequency division circuit, and the other input terminal of the comparator is connected to the high bit of the input duty cycle command signal. The control signal input terminal of the selector is connected to the low bit of the input duty cycle command signal, the system clock is connected to one of the selection signal input terminals of the selector, and the outputs of the comparator and the selector are respectively connected to the two input terminals of the two-input AND gate;

The PWM output logic circuit includes a D flip-flop and a two-input AND gate, the clock end of the D flip-flop is connected to the output end of the comparator in the frequency division circuit, the reset end of the D flip-flop is connected to the output end of the two-input AND gate, and the D flip-flop The D input terminal of the flip-flop is connected to the power supply VDD, and the two input terminals of the two-input AND gate are respectively connected to the output terminals of the two-input AND gate in the system reset signal and clear signal generating circuit, and the output terminal of the D flip-flop is the PWM output logic circuit. Output, that is, the system's adjustable pulse width waveform output;

The DLL oscillating ring circuit includes a control circuit, an oscillating circuit and a clearing circuit, among which:

The control circuit includes a D flip-flop, an error processing circuit, a control signal output logic, a comparator, and a counter. The data input port of the D flip-flop is connected to the system clock, and the output of the D flip-flop is connected to the error input of the error processing circuit. The error processing The enable terminal of the circuit is connected with the output of the comparator and the enable terminal of the counter, the two command signal outputs of the error processing circuit are logically connected with the control signal output, the clock input terminal of the counter is connected with the system clock, and the output of the counter is connected with the system clock One input terminal of the comparator is connected, and the other input terminal of the comparator is connected to the binary code "11111";

The oscillation circuit is composed of multi-level PDUs connected end to end, that is, the output of the previous level of PDU is connected to the input of the next level of PDU, the output of the last level of PDU is connected to the clock signal input port of the D flip-flop in the control circuit, and the output of the other levels of PDU Connect the selection signal input terminals of the selector in the clearing signal generation circuit respectively, and the determination rule of the PDU series is: assuming that the width of the input duty cycle command signal is m, and the number of bits of the counter in the frequency division circuit is n, then the PDU The number of stages is 2 ^(mn) , and it is consistent with and corresponds to the number of output terminals of the control signal output logic in the control circuit. There are delay line circuits, delay signal selectors and D flip-flops in each level of PDU, and the structure is the same: delay line The multi-channel output of the circuit is correspondingly connected with the signal input port of the delay signal selector, the control signal input port of the delay signal selection circuit is connected with the corresponding output of the control signal output logic in the control circuit, and the output of the delay signal selection circuit is connected with the D flip-flop The clock port is connected, except that the input of the delay line circuit in the first-level PDU is connected with the system clock, the input of the delay line circuit in the subsequent PDUs of each level is connected with the output of the D flip-flop in the previous level of PDU, and the PDUs of all levels The output terminal of the D flip-flop in is the output terminal of the PDU of this level;

The reset circuit is provided with two-input OR gates equal to the number of PDUs in the oscillation circuit, one input terminal of all two-input OR gates is connected to the system reset signal, and the other input terminals of all two-input OR gates are respectively connected to the oscillation circuit The output ends of PDUs at all levels, and the outputs of all two-input OR gates are connected to the clearing ends of the D flip-flops in the corresponding PDUs.

Advantages and beneficial results of the present invention: the DLL oscillating ring of the present invention uses the input high-frequency clock signal f _s to trigger the oscillating ring to oscillate and output 2 ^(mn) signals into the clearing signal generating circuit, and the clearing signal generating circuit combines the input f _s The pulse signal PWM_clr is generated by the duty cycle command signal of mbits, and the PWM signal is generated as the output of the system under the action of the PWM output logic circuit of the subsequent stage. Wherein the DLL oscillating ring circuit uses a programmable delay unit to track the input signal in real time, so as to achieve the effect of outputting a very good pulse width modulation waveform under different process angles and different working environments. The present invention greatly reduces the The area required by the chip saves the cost of chip development. Compared with the conventional digital DLL DPWM circuit scheme, on the basis of solving the problem of frequency drift and PWM regulation non-linearity, at the same time, it reduces the area required by the system to a large extent.

1) The required area of the system is small;

2), no frequency drift phenomenon;

3), PWM adjustment linearity is very good;

4) The circuit structure is simple, consisting of standard gate circuits, easy to realize and simple in preparation process.

Description of drawings

Fig. 1 is an existing digital pulse width modulation circuit structure diagram based on digital delay-locked technology;

Fig. 2 is the key signal timing diagram of the existing digital pulse width modulation circuit based on the digital delay lock technology;

Fig. 3 is the schematic diagram of the programmable delay unit of the existing digital pulse width modulation circuit based on the digital delay lock technology;

Fig. 4 is a block diagram of the circuit structure of the present invention;

Fig. 5 is a key signal sequence diagram of the present invention;

Fig. 6 is a circuit diagram of a DLL oscillating ring clearing circuit of the present invention;

Fig. 7 is a circuit diagram of the programmable delay unit of the DLL oscillating ring of the present invention.

Detailed ways

Referring to Fig. 4, the present invention is based on the digital pulse width modulator of digital delay phase-locked loop, comprises frequency division circuit 1, DLL oscillation loop circuit 2, reset signal generation circuit 3 and PWM output logic circuit 4, and prior art also comprises this 4 parts.

The frequency division circuit 1 includes a counter 11 and a comparator 12, the clock signal input end of the counter 11 is connected with the system clock, the reset signal input end of the counter 11 is connected with the system reset signal, and the output of the counter 11 is connected with an input end of the comparator 12 , the other input terminal of the comparator 12 is grounded;

Clearing signal generation circuit 3 comprises comparator 31, selector 32 and a two-input AND gate 33, and an input end of comparator 31 is connected the output of counter 11 in frequency division circuit 1, and the other input end of comparator 31 is connected input The high nMSB of the duty cycle command signal, the control signal input terminal of the selector is connected to the low (m-n) LSB of the input duty cycle command signal, the system clock is connected to one of the selection signal input terminals of the selector 32, the comparator 31 and the selector The output of 32 connects two input ends of two input AND gates 33 respectively;

The PWM output logic circuit 4 includes a D flip-flop 41 and a two-input AND gate 42, the clock end of the D flip-flop 41 is connected to the output end of the comparator 12 in the frequency division circuit 1, and the reset end of the D flip-flop 41 is connected to the two-input AND gate. The output terminal of the gate 42, the D input terminal of the D flip-flop 41 is connected to the power supply VDD, and the two input terminals of the two-input AND gate 42 are respectively connected to the output terminals of the two-input AND gate 33 in the system reset signal and the reset signal generation circuit 3, The output terminal Q of the D flip-flop 41 is the output of the PWM output logic circuit 4, which is the adjustable pulse width waveform output of the system;

DLL oscillating ring circuit 2 comprises control circuit 21, oscillating circuit 22 and clearing circuit 23, wherein:

Control circuit 21 includes D flip-flop 210, error processing circuit 211, control signal output logic 212, comparator 213 and counter 214, the data input port of D flip-flop 210 is connected with system clock, the output Q of D flip-flop 210 and error processing The error input terminal of the circuit 211 is connected, the enabling terminal of the error processing circuit 211 is connected with the output of the comparator 213 and the enabling terminal of the counter 214, and the two command signal outputs L and R of the error processing circuit 211 are connected with the control signal output The logic 212 is connected, the clock input terminal of the counter 214 is connected with the system clock, the output of the counter 214 is connected with an input terminal A of the comparator 213, and the other input terminal B of the comparator is connected with the binary code "11111";

The oscillation circuit 22 is connected end to end by multi-stage (220...227) PDUs, that is, the output of the previous stage PDU is connected to the input of the latter stage PDU (such as the delay line circuit input of PDU226 is connected with the output of PDU227, and the delay line circuit input of PDU225 is connected with the output of PDU227. The output of the PDU226 is connected), the output of the last stage PDU 220 is connected to the clock signal input port of the D flip-flop 210 in the control circuit 21, and the outputs of the other PDUs at all levels are respectively connected to the selection signals of the selector 32 in the clearing signal generation circuit 3 At the input end, the rule for determining the number of stages of the PDU is: assuming that the width of the input duty cycle command signal is m, and the number of bits of the counter in the frequency division circuit is n, then the number of stages of the PDU is 2 ^(mn) , and it is the same as that in the control circuit 1 The number of output terminals of the control signal output logic 212 is consistent and corresponding. There are delay line circuits, delay signal selectors and D flip-flops in all levels of PDUs. 2271 and D flip-flop 2270: the multi-channel output of the delay line circuit 2272 is correspondingly connected to the signal input port of the delay signal selector 2271, and the control signal input port of the delay signal selection circuit 2271 is connected to the control signal output logic 212 of the control circuit 1 The corresponding outputs are connected, and the output of the delay signal selection circuit 2271 is connected with the clock port of the D flip-flop 2270. Except that the input of the delay line circuit 2272 in the first-level PDU227 is connected with the system clock, the input of the delay line circuits in the subsequent PDUs at all levels All are connected to the output of the D flip-flop in the PDU of the previous stage, and the output end of the D flip-flop in the PDU of each level is the output end of the PDU of the current stage.

The reset circuit 23 is provided with two-input OR gates 230...237 equal to the number of PDUs in the oscillation circuit 22, one input end of all two-input OR gates is connected to the system reset signal, and the other input end of all two-input OR gates is Correspondingly connect the output terminals of PDUs of all levels in the oscillation circuit 22 respectively, and the output of all two-input OR gates is connected to the clearing end of the D flip-flop in the corresponding PDU (as the output of the two-input OR gate 237 is connected to the corresponding PDU 227 Clear terminal of D flip-flop 2270).

The circuit structure, working principle and process of the present invention will be further described below in conjunction with the accompanying drawings and examples.

FIG. 1 is a functional block diagram of an existing digital pulse width modulator based on digital delay-locked technology. It can be seen that the existing design circuit also includes four logic parts: frequency division circuit, DLL oscillation circuit, clear signal generation circuit and output logic circuit.

Figure 2 is a timing diagram of an existing digital pulse width modulator based on digital delay-locked technology. It can be seen from the figure that the timing of the existing design is the same as that of most DPWMs, which are divided into two types: coarse adjustment and fine adjustment. In the part, the fine adjustment is realized by the counter, and the coarse adjustment is realized by the delay line.

Fig. 4 is a system block diagram of the present invention. Here, DPWM with 9bits resolution and switching frequency of 100KHZ is taken as an example. The specific parameter distribution is shown in Table 1. According to the distribution of this parameter, it can be concluded that the counter 11 in the frequency division circuit 1 uses a 6-bits counter and the comparator 12 uses 6bits comparator, the frequency of the system clock is 6.4MHZ; the comparator 31 in the clearing signal generating circuit 3 adopts a 6bits comparator, and the selector 32 adopts an 8-to-1 selector; the DLL oscillator circuit 2 needs 8 PDUs.

Table 1 System Index Allocation

On-off level 100KHZ System input clock 32MHZ Resolution 9bits counter digits 6bits Oscillation ring output 3bits counting clock 6.4MHZ Number of programmable delay units 8

The system clock is used as the counting clock of the 6bits counter. The 6bits digital quantity output by the counter 11 is compared with the high 6bits of the duty cycle command. If they are equal, a high level pulse signal is output; the DLL oscillation ring outputs 7 oscillation signals, and the 7 The channel signal and the system clock are used together as the selection signal input of the 8-to-1 selector 32 in the clearing signal generating circuit, and a signal is selected according to the low 3 bits of the duty cycle command signal, and this signal is ANDed with the above-mentioned high-level pulse signal, The clearing signal PWM_clr of the PWM is obtained, and the PWM_clr and the reset signal reset are phase-ANDed as the reset signal of the D flip-flop in the PWM output logic circuit, thus realizing the adjustment function of the PWM duty cycle. As mentioned above, the system is divided into two parts: fine adjustment and coarse adjustment of resolution, fine adjustment is realized by counter 11, and coarse adjustment is realized by digital DLL oscillation ring circuit, the sequence of the present invention is as shown in Figure 5 . The biggest innovation of the present invention lies in the design of the structure of the programmable delay unit (Programmable Delay Unit, PDU) (ie PDU 220...227) in the oscillator circuit in the all-digital DLL oscillator circuit.

The DLL oscillating ring is implemented based on delay-locked technology. The working principle is: the system clock signal is used as the start-up signal of the oscillating circuit in the DLL oscillating ring. The rising edge of the system clock makes the first programmable delay unit output Q1 high. After a period of After a time delay, Q1 causes the output Q2 of the second programmable delay unit to be high, and Q2 in turn acts as a clear signal to make Q1 low, and Q2 causes the output Q3 of the third programmable delay unit to be high after a period of delay. Q3 in turn makes Q2 low, so the pipeline works until the output Q8 of the eighth programmable delay unit is high, and this high level is maintained until the next oscillation cycle Q1 becomes high again. After the above steps, the oscillation The circuit completes one oscillation. The realization of the output of the latter stage in turn clearing the output of the previous stage is realized through a series of two-input OR gates, one input port of the two-input OR gate is connected to the system reset signal reset, and the other input port is connected to the corresponding The output of the programmable delay unit is connected, and the clearing circuit is shown in Fig. 6 .

The above-mentioned oscillating ring structure can work under certain circumstances. In this case, the working environment, manufacturing process, and process corners under the same process all meet the simulation requirements at the beginning of the design, but this ideal situation is in practice. It is impossible to realize it, which leads to the failure of the oscillation ring to work normally. There are two cases of failure to work normally: 1. The oscillation ring can oscillate, but it cannot achieve good linearity. 2. The oscillating ring cannot oscillate. The following is a detailed analysis of these two working conditions: 1. When the oscillation ring can oscillate, when the chip's manufacturing process and ambient operating temperature make the delay time of the chip's programmable delay unit smaller, the rising edge of Q8 is not delayed until The next oscillation cycle, so that the next oscillation cycle can start to oscillate smoothly, but the output of the oscillation loop is very bad. The bad performance is the output of 7 oscillation pulses including the system clock. Among the 8 signals The nonlinearity of the phase difference is serious, and the consequence is that the ideal PWM duty cycle will be greatly different from the actual duty cycle, which seriously affects the performance of the system. 2. If the oscillation ring cannot oscillate, if the rising edge of the Q8 signal is delayed to the next oscillation cycle, the consequence is that Q1 in the next oscillation cycle cannot be pulled high normally, interrupting the work of the oscillation ring.

To sum up, two issues need to be considered when designing the oscillation ring: 1. It must be ensured that the oscillation ring can start to vibrate. 2. It is necessary to adjust the delay of each programmable delay unit in real time, so that the oscillation ring can adapt to changes in factors such as process and environment, and finally output an oscillation signal close to the ideal. In order to meet the above two requirements, the following method is adopted: In the initial situation, under the full consideration of the influence of the environment and the process, the sum of the delay values of the eight programmable delay units will not exceed one system cycle. In this example design, the system The clock is 6.4MHZ, so it must be guaranteed that the sum of the delay values of the eight delay units will not exceed 156.25ns (1000/6.4) in the initial case. In this way, the start-up of the oscillation ring is guaranteed, and then the feedback control method is used to quickly and finely adjust the total delay value of the programmable delay unit, and the required state is achieved in the shortest time and with the best accuracy. The required state is that the rising edge of Q8 coincides with the rising edge of the next system clock.

The problem to be solved now is how to realize the function of digital phase lock (DLL) with the fastest speed and the best precision. Before explaining the detailed method, it is necessary to clarify a concept: programmable delay unit, the programmable delay unit in this design Programming delay unit as shown in Figure 7, input signal passes through a delay line circuit, the determination of the minimum delay and the maximum delay of the delay line circuit is determined under the premise of considering different processes and fully considering environmental factors, the verification of the present invention is Based on charter 180nm CMOS process, the number of delay units in the delay line is 59 (the number of delay units in 2272 is an example), and 16 output ports are drawn in the middle of this delay line (referring to the output port of 2272, 16 output ports port is a necessary condition), the 16 ports are delayed by 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57 and 59 delays relative to the input signal unit (the data here is an example, there are 16 in total), these 16 outputs are the input of the 16-to-1 selector 2271, and the corresponding delayed signal output is selected according to the digital quantity sel[3..0] at the selection end, In this design, the control circuit outputs a control signal to control the selection signal of the 16-to-1 selector 2271 to adjust the delay time of the programmable delay unit. The programmable delay unit in the prior art is realized by a series of NOR gates as shown in Figure 3, and each channel is independent at the same time. The problem caused by this is that when the delay is required to be large, this type of programmable The delay unit requires a large number of logic gates. As far as this design is concerned, the number of two-input NOR gates required by the programmable delay unit of the prior art is: 2*(15+14+13+...+1)+16 =136, the number of 4-input NOR gates is 16, and a 16-input NOR gate is also required, so as the delay time or the range of selectable signals increases, the number of logic gates will increase rapidly. The programmable delay unit of this design is realized by a delay line, and the maximum delay of the delay line is equivalent to the maximum delay in the programmable delay unit in the existing invention, and other delay value selections except the maximum delay value can be selected from In this way, the number of delay units is greatly reduced. The number of logic units required in this design is only 32, and a 16-to-1 selector 2271 can realize the function. , the number of logic gates (230...237) is reduced by 80%.

The DLL control algorithm is as follows: the rising edge of Q8 is used as a sampling signal, and the level of the system clock signal is sampled. If the sampling is low, it means that the total delay time of the programmable delay unit is not enough, and the total delay needs to be increased. Ping, indicating that the total delay time of the programmable delay unit is too large, and the total delay needs to be reduced. In this design, there are 8 programmable delay units (220...227), and there are 16 inputs to the delay signal selector in each programmable delay unit. Therefore, the delay time control port of each PDU needs 4 bits, then the control The module needs to output a 32bits (8*4bits) control word, and the connection between the delay control terminals of the eight programmable delay units and the 32bits control word is shown in Table 3, where Table 3 is a special case of Table 2.

Table 2 Connection mode of programmable delay unit delay control terminal and control_reg

Table 38 Programmable delay unit delay control terminal and connection mode of control word

sel1 control_reg[0, 15, 16, 31] sel2 control_reg[1, 14, 17, 30] sel3 control1_reg[2, 13, 18, 29] sel4 control1_reg[3, 12, 19, 28] sel5 control1_reg[4, 11, 20, 27] sel6 control1_reg[5, 10, 21, 26] sel7 control1_reg[6, 9, 22, 25] sel8 control1_reg[7, 8, 23, 24]

In this design, the method of shift register is used to achieve the required control. The specific method is: the initial value of control_reg is 32'b1000_0000_0000_0000_0000_0000_0000_0000. When the delay needs to be increased, the arithmetic of control_reg is shifted one bit to the right, which increases the control word' The number of 1' increases the total delay of the programmable delay unit accordingly; when the delay needs to be reduced, the control_reg arithmetic shifts one bit to the left, which reduces the number of '1' in the control_reg, correspondingly reduces the overall delay of the programmable delay unit.

Claims (1)

1. A digital pulse width modulator based on a digital delay phase-locked loop, comprising a frequency division circuit, a DLL oscillating ring circuit, a clearing signal generation circuit and a PWM output logic circuit, is characterized in that: The frequency division circuit includes a counter and a comparator. The clock signal input terminal of the counter is connected to the system clock, the reset signal input terminal of the counter is connected to the system reset signal, the output of the counter is connected to one input terminal of the comparator, and the other input terminal of the comparator terminal grounding; The clearing signal generation circuit includes a comparator, a selector and a two-input AND gate. One input terminal of the comparator is connected to the output of the counter in the frequency division circuit, and the other input terminal of the comparator is connected to the high bit of the input duty cycle command signal. The control signal input terminal of the selector is connected to the low bit of the input duty cycle command signal, the system clock is connected to one of the selection signal input terminals of the selector, and the outputs of the comparator and the selector are respectively connected to the two input terminals of the two-input AND gate; The PWM output logic circuit includes a D flip-flop and a two-input AND gate, the clock end of the D flip-flop is connected to the output end of the comparator in the frequency division circuit, the reset end of the D flip-flop is connected to the output end of the two-input AND gate, and the D flip-flop The D input terminal of the flip-flop is connected to the power supply VDD, and the two input terminals of the two-input AND gate are respectively connected to the output terminals of the two-input AND gate in the system reset signal and clear signal generating circuit, and the output terminal of the D flip-flop is the PWM output logic circuit. Output, that is, the system's adjustable pulse width waveform output; The DLL oscillating ring circuit includes a control circuit, an oscillating circuit and a clearing circuit, among which: The control circuit includes a D flip-flop, an error processing circuit, a control signal output logic, a comparator, and a counter. The data input port of the D flip-flop is connected to the system clock, and the output of the D flip-flop is connected to the error input of the error processing circuit. The error processing The enable terminal of the circuit is connected with the output of the comparator and the enable terminal of the counter, the two command signal outputs of the error processing circuit are logically connected with the control signal output, the clock input terminal of the counter is connected with the system clock, and the output of the counter is connected with the system clock One input terminal of the comparator is connected, and the other input terminal of the comparator is connected to the binary code "11111"; The oscillation circuit is composed of multi-level PDUs connected end to end, that is, the output of the previous level of PDU is connected to the input of the next level of PDU, the output of the last level of PDU is connected to the clock signal input port of the D flip-flop in the control circuit, and the output of the other levels of PDU Connect the selection signal input terminals of the selector in the clearing signal generating circuit respectively, and the determination rule of the PDU series is: assuming that the width of the input duty cycle command signal is m, and the number of bits of the counter in the frequency division circuit is n, then the PDU The number of stages is 2 ^(mn) and is consistent with and corresponds to the number of output terminals of the control signal output logic in the control circuit. There are delay line circuits, delay signal selectors and D flip-flops in all levels of PDUs, and the structure is the same: delay line circuit The multi-channel output of the delay signal selector is correspondingly connected with the signal input port of the delay signal selector, the control signal input port of the delay signal selection circuit is connected with the corresponding output of the control signal output logic in the control circuit, and the output of the delay signal selection circuit is connected with the clock of the D flip-flop The ports are connected, except that the input of the delay line circuit in the first-level PDU is connected to the system clock, the input of the delay line circuit in the subsequent PDUs of each level is connected with the output of the D flip-flop in the previous level of PDU, and the output of the D flip-flop in the PDU of each level is connected. The output terminal of the D flip-flop is the output terminal of the PDU of this level; The reset circuit is provided with two-input OR gates equal to the number of PDUs in the oscillation circuit, one input terminal of all two-input OR gates is connected to the system reset signal, and the other input terminals of all two-input OR gates are respectively connected to the oscillation circuit The output ends of PDUs at all levels, and the outputs of all two-input OR gates are connected to the clearing ends of the D flip-flops in the corresponding PDUs.

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