CN102025276B - Clock domain crossing controller of digital control switch power supply and control method thereof - Google Patents

Abstract

A digitally controlled switching power supply cross-clock domain controller and its control method, the controller includes a voltage divider network, an analog-to-digital converter, a digital compensator, a digital pulse modulation circuit, a drive circuit and a clock logic circuit, and the data at the output end of the switching power supply is After the acquisition, the voltage control signal of the switching power supply is output through the sequential processing of each module, and the clock logic circuit provides the working clock of the controller. On the basis of maintaining the advantages of ordinary digital control, the data processing part of the system is optimized, thereby reducing the control signal lag in the system, realizing a real-time data control system, and cutting off the front-end module after the synchronous clock pulse ends work, saving system power consumption.

Description

A digitally controlled switching power supply cross-clock domain controller and its control method

technical field

The invention belongs to the field of electronic technology, relates to the design of an integrated circuit, and is used for a switching power supply of digital control technology, in particular to a cross-clock domain controller of a digital control switching power supply and a control method thereof.

Background technique

The switching power supply using digital control technology can significantly improve the performance of the power system, because the digital control method is flexible, can realize complex control algorithms, and is less sensitive to external influences, such as being less affected by device changes.

The control loop of a digital power supply is formed by cascading multiple functional modules, and how to ensure the synchronous collection of data collection points of each module is a very important issue in digital technology. When data is transmitted across the clock domain, the input data and the sampling clock are edged, and the circuit cannot enter a stable state within the specified time. At this time, it is a metastable state, and the voltage output by the circuit is between illegal logic levels. Specifically The value of the voltage is unpredictable and the output may oscillate. Therefore, when designing a cross-clock domain system, it is necessary to first define the clock of the system so that the clocks are synchronized.

The control loop of the basic digital control switching power supply includes four sub-modules including the analog-to-digital converter ADC, digital compensator, digital pulse width modulation circuit DPWM and driving circuit, as shown in Figure 1. If the input and output of these sub-modules are simply connected to form a closed-loop system, although the function of feedback adjustment can be realized in theory, but the circuit design is carried out according to this architecture, and there is only data transmission between the sub-modules in the system, and there is no timing constraint , the correctness of the timing relationship of the transmitted data cannot be guaranteed, so the architecture in which the functional modules are directly stacked cannot guarantee the correctness of the system work. Moreover, the data processing speed of the two stages of ADC and digital compensator is controlled by their respective working clocks, which can have a relatively fast processing speed, while the output processing speed of the DPWM circuit is synchronized with the switching frequency, which is relatively slow, resulting in data accumulation forming a bottleneck. In order to solve the above problems, it is necessary to determine the appropriate timing relationship for each sub-module, which can be realized by a synchronous clock. Among the existing digital control switching power supply solutions, one is to use multiple shift registers to hold data in front of the digital pulse width modulation circuit. The advantage is that all the data generated by the previous stage can be processed, but the current processing control The signal is the value corresponding to the data several switching cycles ago, which cannot realize real-time control of the system; another method is to perform "cold" processing on the accumulated data, that is, do not do anything to the data that the digital pulse width modulation circuit has no time to process. Processing, DPWM only processes the data at the current input end. This scheme has a simple circuit structure, but part of the data will be lost, and the processed data still has a delay. It is not the latest data, and the cycle corresponding to the data being processed cannot be known.

Contents of the invention

The problem to be solved by the present invention is to carry out reasonable timing control on the digitally controlled switching power supply to ensure the correctness and immediacy of the timing relationship of data transmission.

The technical solution of the present invention is: a digitally controlled switching power supply cross-clock domain controller connected to the switching power supply power stage, the controller includes a voltage divider network H _sense , an analog-to-digital converter ADC, an error voltage signal processing module, and a duty cycle Control signal processing module, digital pulse width modulation circuit DPWM, clock logic circuit and drive circuit, the duty ratio control signal processing module includes a register composed of a digital compensator and a D flip-flop, and the output signal V _out (t) of the switching power supply is divided into After the pressure network H _sense is divided, it is collected and quantized by the analog-to-digital converter ADC to obtain the digital signal V _o [n], and the digital signal V _o [n] and the preset discrete reference voltage V _ref [n] are input to the error voltage signal processing module. The two are subtracted in the error voltage signal processing module to obtain the error voltage signal e[n], the error voltage signal e[n] is input into the digital compensator for data processing, and the output d _c [n] is then passed through the digital pulse width modulation circuit DPWM modulation, and amplified by the driving circuit to generate the voltage control signal d(t) of the switching power supply, in which the clock logic circuit provides the synchronous clock signal syn(t) of each part of the controller.

The clock logic circuit is composed of several D flip-flops, AND gates and NOT gates. The clock pulse generation circuit is obtained by multiplexing the DPWM counter. The output signal of the counter is fed back to the input terminal of the counter after being delayed by the first D flip-flop, and the counter outputs After the signal is inverted, it is sent to the second D flip-flop, and the signal at the inverting end of the second D flip-flop is connected to the input of the third D flip-flop, where the non-inverting output of the second D flip-flop and the third D flip-flop are sent to A two-input AND gate, the output of the two-input AND gate is a synchronous clock signal.

The control method of the digitally controlled switching power supply cross-clock domain controller is: the controller adjusts the size of the duty cycle once in each switching cycle of the switching power supply, and at the same time completes the update of the error voltage signal and the duty cycle control signal: the controller is controlled by The same clock signal syn(t) performs timing control. When the rising edge of the clock signal arrives, the ADC starts to work, performs data acquisition and processing, and updates the data of the error signal processing module at the same time. When the falling edge of the clock signal arrives, the trigger duty The data of the control signal processing module is updated, and the latest duty cycle control signal d[n] is passed to the DPWM for real-time processing, in which the synchronous clock signal syn(t) is set as a narrow pulse signal with a small duty cycle , the size of the narrow pulse signal is related to the working clock of the analog-to-digital converter ADC and the digital compensator, which is the sum of the processing time of the ADC and the calculation time of the digital compensator. In one switching cycle, the syn (t) signal is used As the selection signal, the actual output of DPWM and the power supply voltage V _DD are used as the selected signal of the one-of-two selector. When the syn(t) signal is high, the DPWM output is connected to the power supply voltage, that is, the output PWM is forced to The signal is at a high level, and after the falling edge of the synchronous clock signal syn(t), the duty cycle control signal d[n] actually generated by the switching cycle is used to control the duty cycle of the DPWM output signal dpwm(t), ensuring that the DPWM The PWM signal output in each switching cycle is to adjust the system error voltage signal of the switching cycle.

Based on the analysis of the internal circuit structure and data transmission timing of the digital control switching power supply, the present invention proposes a system construction using a synchronous clock double-edge trigger, and uses the rising and falling edges of the internally generated synchronous clock signal to perform double-edge trigger processing on data , this method makes the data flow across the clock domain work under the unified clock control, overcomes the data delay stability introduced by the single-edge trigger of the clock, and can globally plan the working time of the system modules, and can turn off the front-end modules when necessary. reduce system power loss. The invention also forces the output control signal to be high during the pulse duration of the synchronous clock signal, so as to reduce the data delay in the system, ensure real-time control, and overcome the shortcomings of the prior art.

On the basis of maintaining the advantages of ordinary digital control, the present invention optimizes the data processing part of the controller, thereby reducing the lag of the control signal, realizing a real-time data control system, and cutting off the front-stage module after the synchronous clock pulse ends. work and save system power consumption. Advantages and beneficial effects of the present invention include:

(1), the circuit structure is simple, composed of standard gate circuits, easy to realize and simple preparation process;

(2) The internal synchronous clock double-edge trigger circuit used in the system can process system data in real time, ensuring the real-time performance of control signals;

(3) The design idea of the initial high level of the output duty cycle signal adopted in the system can maintain the adjustment function in the system data processing stage and improve the response speed of the system;

(4) The working time of each module in the system is controllable, which reduces the power loss of the circuit.

Description of drawings

Figure 1 is a block diagram of the system architecture using an external synchronous clock in a digitally controlled switching power supply.

Figure 2 is a diagram of the data change law of the system architecture using an external synchronous clock in a digitally controlled switching power supply.

FIG. 3 is a block diagram of an internal synchronous clock double-edge trigger system architecture of a digitally controlled switching power supply cross-clock domain controller of the present invention.

Fig. 4 shows the data change law of the synchronous clock double-edge trigger system architecture of the digitally controlled switching power supply cross-clock domain controller of the present invention.

Fig. 5 is a circuit diagram of a counter and a synchronous clock generator of a digitally controlled switching power supply cross-clock domain controller of the present invention.

Fig. 6 is the working waveform of the counter and synchronous clock generator circuit of the digitally controlled switching power supply cross-clock domain controller of the present invention.

Fig. 7 is a synchronous clock signal and a duty cycle signal of the cross-clock domain controller of the digitally controlled switching power supply of the present invention.

Fig. 8 is a schematic diagram of the connection between the present invention and the switching power supply.

Detailed ways

As shown in Fig. 3 and Fig. 8, the controller of the present invention includes a voltage divider network H _sence , an analog-to-digital converter, an error voltage signal processing module, a digital compensator, a PWM signal output module, a driving circuit and a clock logic circuit. The output data V _out (t) of the switching power supply is divided by the voltage divider network and then collected and quantified by the ADC to obtain V _o [n], which is subtracted from the preset discrete reference voltage V _ref [n] to obtain the error voltage signal e[n] Send it to the digital compensator for data processing, and then generate the voltage control signal of the switching power supply through the digital pulse width modulation circuit DPWM modulation, and control the opening and closing of the power tube of the switching power supply after the driving circuit increases the driving capacity. The controller adjusts the duty ratio once in each switching cycle of the switching power supply, which is controlled by the synchronous clock signal syn(t) generated by the clock logic, and completes ADC sampling quantization, error generation, compensator output, and duty cycle within one switching cycle. Update of the air ratio control signal. The clock logic circuit is composed of several D flip-flops, AND gates, and NOT gates. The clock pulse generation circuit is obtained by multiplexing the DPWM counter to obtain the synchronous clock signal syn(t). When the rising edge of the clock signal syn(t) arrives, the ADC Start the work, perform data sampling and quantification, update the output data of the error signal processing module and the digital compensator; when the falling edge of the clock signal arrives, it will trigger the data update at the input end of the DPWM duty cycle modulation module, that is, the current duty cycle control signal d _c [ n] read into DPWM for real-time processing. The high-level maintenance time of the synchronous clock signal syn(t) is related to the working clock of the analog-to-digital converter ADC and the digital compensator, which is the sum of the processing time of the ADC and the calculation time of the digital compensator. During the time when syn(t) maintains a high level, the front-end module is processing data, and the DPWM input signal has no data update, and the DPWM input signal is updated only after the falling edge of syn(t) comes. In order to make the duty ratio output signal dpwm(t) of each cycle process the sampling value in the current switching cycle, the DPWM output signal will be forced to be high level during the high level time of syn(t), syn (t) After the falling edge, use the current actual duty cycle control signal to control the DPWM output dpwm(t) high-level maintenance time, that is, the output dpwm(t) high-level maintenance time consists of two parts: forced high power The flat time and precise high level time ensure that the PWM signal output by the DPWM in each switching cycle is to adjust the current system state of the switching cycle. In order to make the adjustment accurate, the high-level time is forced to be as short as possible, that is, syn(t) needs to be a narrow pulse signal, and the high-level maintenance time is short, so the ADC, error processing module and digital compensator are required to have high-speed processing speed . And in order to solve the problem of increased power consumption caused by the high-speed clock of ADC, error processing module and digital compensator, the synchronous clock syn(t) is used as the clock control signal. When the falling edge of syn(t) comes, it means that the three modules process End, cut off its working clock, and turn it on again when it needs to be processed next time, so as to reduce system power consumption.

The control method of the present invention will be described in detail below.

In the digital power supply, the size of the duty cycle is adjusted every switching cycle, and the adjustment process is completed by the two modules of the digital compensator and DPWM. On the one hand, the digital compensator is required to calculate the size of the current required duty ratio control signal d _c [n] according to the magnitude of the error voltage e[n] quantified by the ADC and the working state of the system at the previous moment; on the other hand, the DPWM is required to This duty cycle control signal d _c [n] produces a duty cycle value dpwm(t) of the output PWM waveform within one switching cycle. Assuming a typical digital PID compensation is used, the relationship between the duty cycle control signal and the error voltage is

_dc [n]= _dc [n-1]+ae[n]-be[n-1]+ce[n-2] (1)

Wherein, a, b, and c are the compensation coefficients of PID respectively, and the values of the coefficients can be determined according to the frequency stability design method of the switching power supply system, which are well known to those skilled in the art and will not be described in detail. Therefore, to calculate the duty cycle control signal size d _c [n] of the current switching cycle, the duty cycle size d _c [n-1] of the previous switching cycle, the error voltage e[n] of the current switching cycle, and the previous two switching cycle error voltages e[n-1], e[n-2], so it is also necessary to use a synchronous clock to update each of the above data once in each switching cycle. In the error signal processing module, a series D flip-flop can be used to save relevant data, and a synchronous clock syn(t) can be used to control each switching cycle to complete a data update. Since the D flip-flop inside the error signal processing module and the duty cycle control signal processing module uses the same synchronous clock signal, and there is a unidirectional data flow between the two, the data of the nth switching cycle is in this cycle It is updated by the error processing module and delivered to the digital compensator to calculate the duty cycle, but the calculated duty cycle d _c [n] must be the n+1th switching cycle before it can be controlled by the duty cycle signal The D flip-flop in the processing module updates and controls the DPWM to adjust the duty cycle of the output signal dpwm(t). Using this method can avoid the accumulation and loss of data, but it still causes a switching cycle lag. The output control signal of DPWM cannot control the current system state in time, which will inevitably bring adverse effects to the system.

In order to avoid the real-time control of the power supply system due to the above-mentioned data lag, it is hoped that the update of the error voltage signal and the duty ratio control signal can be completed simultaneously within one switching cycle. Because both are controlled by the same clock signal syn(t), the present invention proposes a processing method in which the rising edge of the clock triggers the error signal processing module to update the data, and the falling edge of the clock triggers the data update of the duty ratio control signal. However, because the duty cycle control signal d _c [n] is still not updated during the period between the rising edge and the falling edge of the synchronous clock signal, its value is still the error voltage e[n] of the last switching cycle and the circuit The data related to other states in the computer is the result calculated by the digital compensator. Considering that the duty cycle in an actual switching power supply system is usually not very small, that is, the PWM signal will not change to a low level within a short time after a switching cycle starts. Based on this feature, the synchronous clock syn(t) is set as a narrow pulse signal with a small duty cycle, and the PWM output signal is forced to be high during the period between the rising edge and the falling edge of the pulse. After the falling edge of the synchronous clock signal, use the duty cycle control signal d _c [n] generated by the switching cycle to control the duty cycle of the PWM signal dpwm(t), so as to ensure that the PWM signal output in each switching cycle is right The switching cycle is regulated by the system error voltage signal. The size of the narrow pulse signal is related to the operating clock of the analog-to-digital converter ADC and the digital compensator, which is the sum of the processing time of the ADC and the calculation time of the digital compensator, within the pulse time of a clock signal, using syn (t ) signal as the selection signal, use the actual output of DPWM and the power supply voltage V _DD as the selected signal of the two-choice selector, when the syn(t) signal is high, the DPWM output is connected to the power supply voltage, that is, the DPWM is forced to The output signal is high level.

The circuit structure, working principle and working process of the present invention will be further described below in conjunction with the accompanying drawings and examples.

Referring to Fig. 2 and Fig. 3, digital compensator is brought into the category of duty ratio control signal processing module in the cross-clock domain controller of the digitally controlled switching power supply optimized in the present invention, and syn(t ) signal to replace the original external clock signal. The rising edge of the synchronous clock syn(t) means the start of a switching cycle, and the rising edge will trigger data update in the D flip-flop in the error voltage signal processing module in the figure. After the rising edge of the synchronous clock, it is high level. During the high level period, the duty cycle control signal has not been updated, and its value is still the data of the previous switching cycle. However, in this case, the synchronous clock controls the multiplexer to force The output of DPWM is high level, and the duty cycle control signal of the previous switching cycle is not allowed to control the duty cycle of the PWM signal in the current switching cycle. During this period, the digital compensator completes the digital compensation according to the compensation algorithm shown in formula (1). The falling edge of the synchronous clock signal triggers the duty cycle control signal of the current switching cycle to be updated through the D flip-flop, and the updated data is handed over to the DPWM to control the duty cycle of the PWM signal, and the synchronous clock signal jumps to a low level, At this time, the multiplexer outputs the actual duty ratio signal of the current switching period of the DPWM. Figure 4 shows how the data changes with the synchronous clock signal.

The relationship between the output value dpwm(t) of DPWM and the synchronous clock syn(t) can be seen that during the time period when the synchronous clock signal syn(t) is high, the PWM output is forced to be high, and when syn(t) becomes low , PWM will output the actual duty cycle value. Therefore, in this circuit structure, the size of the minimum duty cycle signal that the system can output is limited by the clock synchronization signal, and the ideal zero duty cycle cannot be achieved. However, judging from the actual working conditions of the switching power supply, the system basically does not require the duty cycle signal to be zero within one switching cycle in the PWM working mode, so the limit of the minimum duty cycle signal that can be output has no effect on the actual circuit work. Influence. The synchronous clock signal and duty ratio signal of the controller of the present invention are shown in Figure 7, wherein 1 is the duty ratio signal, and 2 is the synchronous clock signal.

In the present invention, the synchronous clock generation circuit is realized by multiplexing the counter design pulse generating circuit of the DPWM part in the digital power supply. Referring to Fig. 5, the clock logic circuit is composed of several D flip-flops, AND gates and NOT gates. The counter gets the clock pulse generation circuit, and the output signal of the counter is fed back to the input terminal of the counter after being delayed by the first D flip-flop. At the same time, the output signal of the counter is reversed and sent to the second D flip-flop, and the signal at the inverting terminal of the second D flip-flop The input terminal of the third D flip-flop is connected, wherein the non-inverting output terminals of the second D flip-flop and the third D flip-flop are sent to a two-input AND gate, and the output of the two-input AND gate is a synchronous clock signal. In this circuit, the rising edge of the input clock signal clk_in will trigger the first D flip-flop DFF to update data, causing the counter output signal N[n-1:0] to be increased by one. Within (2 ⁿ -1) counting cycles after the counting starts, the highest bit N[n-1] of the counter output is always '0'; after 2 ⁿ cycles, the counter is full, and N[n-1] is '1'', while the synchronous clock signal syn(t) remains low during this period. After (2 ⁿ +1) cycles, N[n-1] jumps from '1' to '0' again. At this time, the Q terminal of the second D flip-flop DFF0 outputs a high level, and the NQ terminal outputs a low level; while the output of the third D flip-flop DFF1 still maintains the previous '1', and the outputs of the two D flip-flops pass through the AND logic Afterwards, the synchronous signal transitions to a high level, and after one cycle of the clk_in signal, the output of the third D flip-flop DFF1 transitions to a low level, and the synchronous signal also transitions to a low level. When the counter output value becomes zero again, the synchronization signal will jump again, so the period of the synchronization signal is exactly the switching period, and the duty ratio is 1/32. Figure 6 shows the working waveform of the counter and synchronous clock generator circuit of the digitally controlled switching power supply cross-clock domain controller. In addition, since the positive transition of the synchronization signal occurs at the moment when the counter outputs a zero value, the PWM signal will also undergo a positive transition at this time, so the positive transition of the synchronization signal means the beginning of a switching cycle, and the synchronization signal can fully satisfy the system data synchronization. needs.

Claims (2)

1. a digital control Switching Power Supply cross clock domain controller is connected with Switching Power Supply, it is characterized in that controller comprises potential-divider network H _Sense, analog to digital converter ADC, error voltage signal processing module, duty cycle control signal processing module, digital pulse width modulation circuit DPWM, logical circuit of clock and drive circuit, the duty cycle control signal processing module comprises the register that digital compensator and d type flip flop are formed, Switching Power Supply output end signal V _Out(t) through potential-divider network H _SenseGathered by analog to digital converter ADC after the dividing potential drop and quantize to obtain digital signal V _o[n], digital signal V _o[n] and default discrete reference voltage V _Ref[n] input error voltage signal processing module, both in the error voltage signal processing module, subtract each other obtain error voltage signal e[n], error voltage signal e[n] carry out data processing, the output d of duty cycle control signal processing module in the input digit compensator _c[n] is again through digital pulse width modulation circuit DPWM modulation, and by the voltage control signal d (t) that produces Switching Power Supply after the drive circuit amplification, wherein logical circuit of clock provides the synchronizing clock signals syn (t) of controller each several part;

Controller is regulated the size of a duty ratio in each switch periods of Switching Power Supply, and finish the renewal of error voltage signal and duty cycle control signal simultaneously: controller carries out sequencing control by a synchronizing clock signals syn (t), when rising edge of clock signal arrives, analog to digital converter ADC starts work, carry out data acquisition process, upgrade the data of error voltage signal processing module simultaneously, when the trailing edge of clock signal arrives, trigger the Data Update of duty cycle control signal processing module, and with up-to-date duty cycle control signal d[n] pass to digital pulse width modulation circuit DPWM and handle in real time, wherein synchronizing clock signals syn (t) is set to a narrow pulse signal that duty ratio is very little, the size of described narrow pulse signal is relevant with the work clock of analog to digital converter ADC and digital compensator, be the processing time of analog to digital converter ADC and sum computing time of digital compensator, in a switch periods, utilize synchronizing clock signals syn (t) as selecting signal, with digital pulse width actual output of modulation circuit DPWM and supply voltage V _DDSelected signal as the alternative selector, when synchronizing clock signals syn (t) is high level, make digital pulse width modulation circuit DPWM output and supply voltage connect, promptly force to make that the pwm signal of output is a high level, re-use the duty cycle control signal d[n of actual generations of this switch periods after synchronizing clock signals syn (t) trailing edge] the duty ratio size of the output signal dpwm (t) of control figure pulse-width modulation circuit DPWM, the pwm signal that assurance digital pulse width modulation circuit DPWM exports in each switch periods is that the systematic error voltage signal of this switch periods is regulated.

2. digital control Switching Power Supply cross clock domain controller according to claim 1, it is characterized in that logical circuit of clock is by some d type flip flops, two inputs are formed with door and not gate, counter by digital multiplexing pulse-width modulation circuit DPWM obtains clock circuit, counter output signal feeds back to the counter input after delaying time through first d type flip flop again, send into second d type flip flop after the negate of unison counter output signal process not gate, the second d type flip flop end of oppisite phase signal inserts the input of 3d flip-flop, wherein the in-phase output end of second d type flip flop and 3d flip-flop is sent into one two input and door, and described two inputs are synchronizing clock signals with the output of door.

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