CN104333365A - Three-segment time digital converter (TDC) circuit - Google Patents

Abstract

The invention discloses a three-segment time digital converter (TDC) circuit. Time interval measurement is completed through high-segment quantization, middle-segment quantization and low-segment quantization. A high-segment TDC adopts a linear feedback shift register (LFSR) structure to realize wide-range measurement. A middle-segment TDC adopts a ring oscillator structure, searches the position of the rising edge of a high-frequency clock through uniform phase resolution, triggers a latch signal and a middle-segment counting signal, and completes middle-segment measurement with a synchronous counter. A low-segment ring oscillator TDC completes finer measurement of quantization error, adopts the same structure as the middle segment, and adopts a mode of decoding before transmission. All data is output sequentially and serially in binary form through a logic control circuit. Compared with a traditional three-segment TDC, the TDCs of the invention can realize delay unit multiplexing to obtain a better architecture design and a smaller layout area. Under the same detection accuracy, the system power consumption generated is reduced significantly. Therefore, the three-segment time digital converter (TDC) circuit can be applied to a high-speed and high-precision time measurement system.

Description

A three-stage time-to-digital conversion circuit

technical field

The invention relates to a three-stage time-to-digital conversion circuit, which can be used in a high-speed and high-precision time measurement system.

Background technique

Time Digital Converter (Time Digital Converter, TDC) is a commonly used circuit for time measurement. It directly converts time intervals into high-precision digital values and realizes digital output. At present, it has been widely used in the electronic field, such as in the all-digital phase-locked loop ADPLL, to improve the time characteristics of its test devices and signals. In recent years, the most concerned TDC is the structure using high-speed CMOS digital circuits, the main reason is that the signal to be tested can achieve high time accuracy. Research on the accuracy of TDC will benefit the application and quality assurance of TDC.

With the vertical development of high-precision time quantization technology, a number of high-performance analog devices with time-to-digital converters as the core have emerged in the field of analog ICs, such as high-speed and low-power analog-to-digital converters and all-digital phase-locked loops. , Overcome a series of design problems of analog circuits that cannot be solved due to the limitation of process size, and open up a new design approach for the design of analog ICs. Therefore, the time-to-digital converter will become a bridge connecting the analog continuous-time semaphore and the digital discrete semaphore, and become a new field of digital-analog hybrid integrated circuit design.

Contents of the invention

Purpose of the invention: Aiming at the above-mentioned prior art, a three-stage time-to-digital conversion circuit is proposed. Compared with the traditional three-stage TDC structure, it simplifies the circuit structure and reduces the system cost while realizing wide-range and high-precision measurement. area and power consumption.

Summary of the invention: A three-stage time-to-digital conversion circuit, including a high-stage linear feedback shift register, an initial phase adjustment circuit, a delay matching circuit, a middle-stage time-to-digital conversion circuit, an adjacent signal extraction unit, and a low-stage time-to-digital conversion circuit , a two-bit binary synchronous counter, a decoding unit, a direct decoding latch circuit and a serial data output circuit; where:

The high-frequency clock CLK_H and the time-quantized start signal EN are input to the initial phase adjustment circuit. When the start signal EN is at a high level, the initial phase adjustment circuit generates the EN0 signal at the next rising edge of the high-frequency clock CLK_H And sent to the high segment linear feedback shift register;

At the end moment, the Stop signal is input into the high-segment linear feedback shift register, and the high-segment linear feedback shift register is used to perform the time interval between the EN0 signal and the rising edge of the high-frequency clock CLK_H immediately after the rising edge of the Stop signal. Quantize to obtain the high-segment quantization value k T _clk , where T _clk is the cycle of the high-frequency clock CLK_H, and k is the count value of the high-segment linear feedback shift register; the high-segment linear feedback shift register converts the high-segment quantization value input to the serial data output circuit;

The delay matching circuit is used to delay the high-frequency clock CLK_H according to the Stop signal, so that the high-frequency clock CLK_H lags behind the Stop signal by _tDFF+AND time on the rising edge immediately after the rising edge of the Stop signal, and obtains the delayed CLK_M signal, wherein tDFF _+AND is the inherent delay of the high-frequency clock CLK_H signal behind the EN0 signal generated by the initial phase adjustment circuit;

The CLK_M signal is respectively input to the middle bit time digital conversion circuit and the low bit time digital conversion circuit; the middle bit time digital conversion circuit is a ring TDC, including a first voltage-controlled ring vibration unit composed of a four-stage delay unit, The first voltage-controlled ring vibration unit generates a periodic signal whose rising edge is aligned with the Stop signal and whose period is t _M =t _clk /4 according to the external voltage-controlled signal, and inputs it to the adjacent signal extraction unit; the adjacent The signal extraction unit scans the interval where the rising edge of the CLK_M signal is located in the periodic signal whose period is t _M =t _clk /4, thereby generating a latch signal LOCK;

The two-bit binary synchronous counter is used to quantify and measure the time interval between the Stop signal and the rising edge of the latch signal LOCK to obtain the mid-level quantized value T _Counter =n·t _M , wherein n is a two-bit binary synchronous The count value of the counter; the binary synchronous counter inputs the quantized value of the mid-stage bit into the direct decoding latch circuit;

The low-level time-to-digital conversion circuit is a ring TDC, including a second voltage-controlled ring vibration unit composed of a four-stage delay unit, and an external voltage control signal controls the ring vibration period of the second voltage-controlled ring vibration unit to be t _L , The rising edge of the CLK_M signal is used as a low-level quantization gating signal. After the eight phase node states formed by the second voltage-controlled ring oscillation unit are decoded by the decoding unit, when the rising edge of the latch signal LOCK arrives , the direct decoding latch circuit is used to latch the decoding value m output by the decoding unit at this time to obtain a low-level quantization value (m/8)·t _L ;

The direct decoding latch circuit includes a D flip-flop and an alternative switch, which is used to latch the mid-level quantized value and the low-level quantized value in the D flip-flop, and after directly decoding into a corresponding decimal value, the One-of-two switch controls to latch the data into the serial data output circuit;

The serial data output circuit is used to sequentially serially output the input high-level quantization value, middle-level quantization value and low-level quantization value to obtain the time interval between the initial phase-adjusted start signal EN0 and the stop signal at the end moment The global expression is T=k·T _clk −n·t _M +(m/8)·t _L .

Further, the first voltage-controlled ring oscillation unit of the middle bit-time digital conversion circuit and the second voltage-controlled ring oscillation unit of the low-level bit time digital conversion circuit multiplex the delay unit composed of a current-starved voltage-controlled inverter. delay chain.

Further, the decoding unit is an exclusive OR gate circuit adopting a Gray code decoding method.

Beneficial effects: the three-segment time-to-digital conversion circuit of the present invention is divided into high-segment, middle-segment and low-segment counting, wherein the high-segment TDC adopts a linear feedback shift register (LFSR), and adopts counting quantization to realize a wide range of time Measurement; the middle section TDC adopts the ring vibration structure, the ring oscillation circuit is composed of four-stage voltage-controlled delay unit, the end signal Stop is used as the gating signal, and the generated frequency provides the counting clock signal for the binary synchronous counter; the low section TDC adopts and the middle section In the same ring oscillator structure, the delayed and shaped high-frequency clock signal CLK_M is used as the gating signal, and the state of the internal phase node of the ring oscillator is decoded and output as low-level data.

Both the middle and low segments adopt ring TDC, and its closed-loop delay line adopts the delay unit of current-hungry voltage-controlled inverter, which is controlled by an externally set voltage-controlled signal with a fixed voltage value, so that the two voltage-controlled loops The output frequency of the vibration unit has high stability. At the same time, the first voltage-controlled ring oscillation unit of the middle bit-time digital conversion circuit and the second voltage-controlled ring oscillator unit of the low-level bit time digital conversion circuit multiplex the delay chain formed by the delay unit of the current-hungry voltage-controlled inverter, The two TDCs are controlled by different gating signals to realize the quantization function of the middle and low stages, and reduce the area and power consumption of the circuit at the same time.

Since the EN0 signal in the initial phase adjustment circuit lags behind the high-frequency clock CLK_H at the rising edge t _DFF+AND time immediately after the rising edge of the Stop signal, the t _DFF+AND time is inherent in the D flip-flop and the AND gate in the initial phase adjustment circuit sum of delays. A delay matching circuit is used before the mid-level TDC. The delay matching circuit is composed of a D flip-flop, an AND gate and an inverter. The high-frequency clock CLK_H is delayed according to the Stop signal, so that the high-frequency clock CLK_H is immediately adjacent to the rising edge of the Stop signal. The rising edge of the stop signal lags behind the Stop signal by t _DFF+AND time, and the delayed CLK_M signal is obtained, so that the overall measurement time interval remains unchanged, and the delay matching between the high segment and the middle segment is realized.

The decoding unit connected to the low-level TDC is an exclusive OR gate circuit using Gray code decoding, which greatly reduces logic confusion, reduces the output frequency of the lowest weight bit, and greatly reduces the bit error rate. The same decoding circuit structure is used to decode the eight phase node states of the voltage-controlled ring oscillator unit in the low-level TDC, and the delay matching and structural symmetry are realized.

The three-stage time-to-digital conversion circuit can work in two modes of counting and data transmission. These two modes are controlled by high-frequency counting clock and low-frequency transmission clock respectively, and the counting data is serially output in the form of binary data.

Compared with the traditional two-stage time-to-digital converter, the three-stage time-to-digital conversion circuit in the present invention can well balance the performance requirements of measurement accuracy and dynamic range, and realize more accurate time measurement. Inter-segment adjacent signal extraction technology uses different measurement methods to measure the time interval of adjacent segments, so that the delay chain can be reused in each segment of TDC, reducing the area and simplifying the circuit structure.

Description of drawings

Fig. 1 is the structural representation of three-stage time-to-digital conversion circuit;

Fig. 2 is a sequence diagram of the middle and low stage TDC time measurement principle of the three-stage time-to-digital conversion circuit;

Fig. 3 is a structure diagram of a middle and low stage TDC circuit of a three-stage time-to-digital conversion circuit;

Fig. 4 is the LFSR structure of the high-segment bit counting/transmission dual mode of the three-segment time-to-digital conversion circuit;

Fig. 5 is a structure diagram of the middle and low section TDC 5-bit data latch and transmission of the three-section time-to-digital conversion circuit;

Fig. 6 is a structural diagram of the voltage-controlled delay unit of the middle and low stage TDC of the three-stage time-to-digital conversion circuit;

FIG. 7 is a timing diagram of a three-stage time-to-digital conversion circuit.

Detailed ways

The present invention will be further described in conjunction with the accompanying drawings.

As shown in Figure 1, a three-segment time-to-digital conversion circuit includes a high-segment linear feedback shift register, an initial phase adjustment circuit, a delay matching circuit, a middle-segment time-to-digital conversion circuit, an adjacent signal extraction unit, and a low-segment time A digital conversion circuit, a two-bit binary synchronous counter, a decoding unit, a direct decoding latch circuit and a serial data output circuit.

Among them, the high-frequency clock CLK_H and the time-quantized start signal EN are input to the initial phase adjustment circuit. When the initial signal EN is at a high level, the initial phase adjustment circuit generates the EN0 signal at the next rising edge of the high-frequency clock CLK_H and sends it to Highest segment linear feedback shift register.

At the end moment, the Stop signal is input to the high-level linear feedback shift register, and the high-level linear feedback shift register quantizes the time interval between the EN0 signal and the high-frequency clock CLK_H rising edge immediately after the rising edge of the Stop signal to obtain the high-level quantization value k · T _clk , where T _clk is the period of the high-frequency clock CLK_H, and k is the count value of the high-level linear feedback shift register. The high-segment linear feedback shift register inputs the high-segment quantization value to the serial data output circuit.

Since the EN0 signal lags behind the high-frequency clock CLK_H signal with a fixed delay of t _DFF+AND , the time interval between the EN0 signal and the Stop signal is relatively reduced. The delay matching circuit delays the high-frequency clock CLK_H according to the Stop signal, so that the high-frequency clock CLK_H lags behind the Stop signal t _DFF+AND time on the rising edge immediately after the rising edge of the Stop signal, and obtains the delayed CLK_M signal, where t _{DFF+ AND} is the inherent delay of the EN0 signal generated by the initial phase adjustment circuit lagging behind the CLK_H signal. As shown in Figure 2, the timing diagram of the middle and low stage TDC time measurement principle of the three-stage TDC, CLK_M is a high-frequency clock signal after the delay matching and after the rising edge of the Stop signal at the end time. In the absence of any delay, CLK_M should be aligned with the rising edge of the Stop signal. Due to the delay t _DFF+AND , the arrival time of the rising edge of the CLK_M signal is delayed, and the maximum delay between CLK_M and the Stop signal should not exceed one high frequency clock cycle T _clk . A delay matching circuit is added to make the CLK_M signal also lag behind the Stop signal by a fixed delay of t _DFF+AND , so as to realize delay matching and keep the overall measurement time interval unchanged.

The CLK_M signal is respectively input to the middle bit time digital conversion circuit and the low bit time digital conversion circuit. The middle bit time digital conversion circuit is a ring TDC, including a first voltage-controlled ring oscillator unit composed of four-stage delay units. The first voltage-controlled ring vibration unit generates periodic signals S0-S3 whose rising edges are aligned with the Stop signal and whose period is t _M =t _clk /4 according to the external voltage-controlled signal, and input to the adjacent signal extraction unit. The adjacent signal extracting unit scans the interval where the rising edge of the CLK_M signal is located in the periodic signal whose period is t _M =t _clk /4, so as to generate the latch signal LOCK. Since the period of the scanning signal is t _M =t _clk /4, and the time interval between the rising edge of the Stop signal and the CLK_M signal is less than T _clk , the rising edge of the CLK_M signal must be within the signal range of S0-S3. If the rising edge of the CLK_M signal is between the rising edges of two adjacent signals within the S0-S3 signal range, the latch signal LOCK is triggered by the rising edge of the latter signal. The time interval from the rising edge of the Stop signal to the rising edge of the latch signal LOCK is the mid-level TDC quantization value T _Counter , and T _Counter must not exceed 4t _M , so the value of the count signal Count generated by the mid-level must not be greater than 4, then it can be Counting is accomplished with a two-bit binary synchronous counter. Quantify and measure the time interval between the Stop signal and the rising edge of the latch signal LOCK through the synchronous counter, and obtain the quantized value of the mid-level bit T _Counter = n·t _M , where n is the count value of the two-bit binary synchronous counter. Then, the binary synchronous counter inputs the quantized value of the middle bit into the direct decoding latch circuit.

The time interval from the rising edge of CLK_M to the rising edge of LOCK is the time margin t _R for low-level ring oscillation TDC measurement. The low-level bit time digital conversion circuit is a ring TDC, including a second voltage-controlled ring vibration unit composed of four-stage delay units. The external voltage control signal controls the ring vibration period of the second voltage-controlled ring vibration unit to be t _L , and the rising edge of the CLK_M signal As a low-level quantization trigger signal, after the eight phase node states formed by the second voltage-controlled ring oscillator unit are decoded by the decoding unit, when the rising edge of the latch signal LOCK arrives, the direct decoding latch circuit latches these The decimal decoding value m output by the time decoding unit is used to obtain the low-rank quantization value t _R =(m/8)·t _L . Then the expression of middle and low time measurement is:

T _M ＝T _Counter -t _R ＝n t _M -t _R ＝n t _M -(m/8) t _L (1)

The direct decoding latch circuit includes a D flip-flop and a two-choice switch, which is used to latch the mid-level quantization value and the low-level quantization value in the D flip-flop, and directly decode it into the corresponding decimal value. A switch controls latching data into the serial data output circuit.

The serial data output circuit is used to serially output the input high-level quantization value, middle-level quantization value and low-level quantization value in sequence to obtain the global expression of the time interval between the initial phase adjusted start signal EN0 and the stop signal at the end time The formula is:

T＝k·T _clk T _M ＝k·T _clk n·t _M +(m/8·)t _L (2)

In the above-mentioned three-stage time-to-digital conversion circuit, the first voltage-controlled ring oscillator of the middle-stage time-to-digital conversion circuit and the second voltage-controlled ring oscillator of the low-stage time-to-digital conversion circuit are multiplexed by a current-hungry voltage-controlled inversion The delay chain formed by the delay unit of the device.

As shown in Figure 3, it is a structure diagram of the low-end TDC circuit. The logic circuit on the left is composed of D flip-flops, AND gates and inverters, which is a delay matching circuit. The mid-level ring oscillator circuit with Stop as the gating signal generates a periodic signal with a period of t _M =t _clk /4, that is, the S0, S1, S2, and S3 signals in Figure 2, which are used to scan the interval where the rising edge of the CLK_M signal is located . If the rising edge of CLK_M is between the rising edges of two adjacent signals, the D flip-flop is triggered by the rising edge of the latter signal to generate the latch signal LOCK, and at the same time record the ring oscillation period signal between the Stop signal and the LOCK signal. Count, trigger the Count counting signal. The state information of eight phase nodes generated by the low-level ring oscillator circuit with CLK_M as the gate signal is sampled by the LOCK signal, and the low-level three-bit data Q0, Q1, and Q2 are generated through the decoding circuit composed of exclusive OR gates. The delays of the one-of-two switches and the inverters in the ring oscillator circuit match the delays of the three delay units, thereby avoiding edge error problems caused by delay mismatches in the paths. The decoding circuit adopts the Gray code decoding method to decode the eight phase node states into three-bit data output, so that the frequency of the lowest weight bit data of the low-level TDC is greatly reduced, and the ordinary binary decoding circuit is avoided. D flip-flop bit error caused by too high frequency. The Gray code decoding table of the low-level ring oscillator TDC phase state is shown in Table 1. The expressions of the decoding output bits of Q0, Q1, and Q2 are respectively:

Table 1

${\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; \&CirclePlus;</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

The high-level TDC adopts a 7-bit LFSR structure with counting/transmitting dual modes, and the circuit is shown in Figure 4. EN0 is the control signal after the initial phase adjustment. When EN and EN0 are both at high level, the two-selection switch selects port 1, and the CLK_H clock signal controls the counting and latches. When EN and EN0 are both at low level, it enters the serial output stage controlled by the low-frequency transmission clock CLK_L signal, and the 7-bit data Q5-Q11 of the high-level TDC is sequentially output serially from the Q11 port. The low 5-bit data of the middle and low segment TDC flows from the left to the right of the circuit through the one-two switch, followed by the serial output of the high segment data. In this embodiment, the CLK_H clock signal input to the 7bit LFSR structure is preprocessed first, and the high frequency signal H_CK and the signal SH are input to the input end of the clock signal of the 7bit LFSR structure through the AND gate, wherein the high frequency signal H_CK is the period The clock signal of T _clk , as shown in Figure 3, the signal SH is an inverted signal generated by the CLK_M signal, and this structure functions to turn off the CLK_H signal. Since it is necessary to measure the time interval between the rising edge of the Stop signal and the next rising edge of CLK_H, the high-frequency counting clock must be turned off after taking the time interval to avoid counting errors in the high-segment TDC. The timing diagram is shown in Figure 7.

As shown in Figure 5, the lower 5-bit data latch circuit of the middle and low segment TDC is composed of a two-bit binary synchronous counter, five two-to-one switches and a low segment data latch D flip-flop. The first two select one switches control the counting and transmission of the middle rank respectively by selecting the count count signal of the middle rank and the low-frequency transmission signal CLK_L, and the last three select one of two switches and the D flip-flop latch and transmit the low rank data. When EN is at high level, the one-of-two switch strobes port 1, allowing the latch signal LOCK to directly latch the three-bit data of the lower segment, and at the same time, the counting signal Count of the middle segment triggers the two-bit binary synchronous counter to start counting to generate the middle segment Data Q3, Q4. When EN is low level, latching and counting are stopped, and the serial transmission mode is started. Finally, the 5-bit data of the middle and low ranks are serially output from the far right to the high-rank TDC transmission circuit to form a 12-bit serial output binary code.

The middle and low segment TDC adopts a voltage-controlled reverse delay unit, as shown in Figure 6, it connects a pair of voltage-controlled current sources in series between the inverters, and through the control of complementary voltages, it can effectively control the propagation from input to output Delay. As the control voltage OE increases, the on-resistance of the controlled MOS transistor decreases, the discharge current of the inverter increases, and the delay time decreases. At the same time, when the input of the delay unit is at a high level, the digital tube forms a negative feedback at the source of the control tube, which reduces the sensitivity of the current to the control voltage and enhances the stability of the transmission time of the delay unit.

The three-stage time-to-digital conversion circuit of the present invention realizes high detection accuracy and wide-range time measurement, occupies a small area, consumes low power consumption, and can be applied to a high-speed and high-precision time measurement system.

The above is only a preferred embodiment of the present invention, it should be pointed out that, for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (3)

1. a syllogic time-to-digital conversion circuit, is characterized in that: comprise high section linear feedback shift register, first phase adjustment circuit, delay matching circuit, stage casing bit time digital conversion circuit, adjacent signals extraction unit, low section time-to-digital conversion circuit, two binary synchronous counters, decoding unit, direct decoding latch cicuit and serial data output circuits; Wherein:

The initial signal EN input just phase adjustment circuit of high frequency clock CLK_H and time quantization, when described initial signal EN is high level, described just phase adjustment circuit produces EN0 signal at the next rising edge place of high frequency clock CLK_H and is sent to high section linear feedback shift register;

The described high section linear feedback shift register of finish time Stop signal input, described high section linear feedback shift register is used for quantizing the time interval of the rising edge that described EN0 signal and high frequency clock CLK_H are close to after Stop signal rising edge, obtains high section quantized value kT _clk, wherein T _clkfor the cycle of high frequency clock CLK_H, k is the count value of high section linear feedback shift register; High section quantized value is input to serial data output circuit by described high section linear feedback shift register;

Described delay matching circuit is used for carrying out delay disposal according to described Stop signal to described high frequency clock CLK_H, the rising edge delayed Stop signal t that high frequency clock CLK_H is close to after Stop signal rising edge _dFF+ANDtime, obtain the CLK_M signal after postponing, wherein t _dFF+ANDfor the inherent delay of the described EN0 signal backward high frequency clock CLK_H signal that described just phase adjustment circuit generates;

Described CLK_M signal is input to respectively stage casing bit time digital conversion circuit and low section time-to-digital conversion circuit; Described stage casing bit time digital conversion circuit is annular TDC, comprises the first voltage-controlled ring be made up of level Four delay cell and to shake unit, and the described first voltage-controlled ring unit that shakes produces rising edge and described Stop signal alignment according to outside voltage control signal and the cycle is t _m=t _clkthe periodic signal of/4, and be input to adjacent signals extraction unit; It is t in the cycle that described adjacent signals extraction unit scans described CLK_M signal rising edge _m=t _clkthe interval at place in the periodic signal of/4, thus produce latch signal LOCK;

Described two binary synchronous counters are used for carrying out measures of quantization to the time interval between described Stop signal and latch signal LOCK rising edge, obtain middle section quantized value T _counter=nt _m, wherein n is the count value of two binary synchronous counters; Middle section quantized value is inputted direct decoding latch cicuit by described binary synchronous counter;

Described low section time-to-digital conversion circuit is annular TDC, comprises the second voltage-controlled ring be made up of level Four delay cell and to shake unit, and it is t that outside voltage control signal controls shake ring cycle of shaking of unit of described second voltage-controlled ring _ldescribed CLK_M signal rising edge quantizes gate-control signal as low section, described second voltage-controlled ring shake unit form eight phase node states carry out after decoding through described decoding unit, when arriving when latch signal LOCK rising edge, the decoding value m that described direct decoding latch cicuit exports for latching now described decoding unit, obtains low section quantized value (m/8) tL;

Described direct decoding latch cicuit comprises d type flip flop and either-or switch, for middle section quantized value and low section quantized value are latched in d type flip flop, and after being directly decoded into corresponding decimal value, controlled latches data in serial data output circuit by either-or switch;

Described serial data output circuit is used for the high section quantized value to input, middle section quantized value and low section quantized value Serial output successively, and the overall expression formula obtaining the time interval of the initial signal EN0 after first phase adjustment and finish time Stop signal is T=kT _clk-nt _m+ (m/8) t _l.

2. a kind of syllogic time-to-digital conversion circuit according to claim 1, is characterized in that: shake the second voltage-controlled ring of unit and low section time-to-digital conversion circuit of the first voltage-controlled ring of described stage casing bit time digital conversion circuit shakes the unit multiplexed delay chain be made up of the delay cell of the voltage-controlled inverter of current-steering.

3. a kind of syllogic time-to-digital conversion circuit according to claim 1, is characterized in that: described decoding unit is the NOR gate circuit adopting Gray code decoded mode.