CN104882483B - Field-effect transistor with Γ grid and recess buffer layer and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of field effect transistors, and aims to provide a field effect transistor with a Γ gate and a recessed buffer layer, which has a wide channel and a deep recess, can increase output current and breakdown voltage, and improve frequency characteristics, and a preparation method thereof; The technical scheme adopted is: a 4H-SiC semi-insulating substrate, a P-type buffer layer, and an N-type channel layer are arranged from top to bottom, and a source cap layer and a drain cap are respectively arranged on both sides of the N-type channel layer Layer, the surface of the source cap layer and the drain cap layer are respectively provided with a source electrode and a drain electrode, the middle part of the N-type channel layer and the side close to the source cap layer is provided with a stepped gate electrode, the gate electrode and The left channel and the right channel are formed on both sides of the N-type channel layer, the lower gate surface of the gate electrode is flush with the surface of the N-type channel layer, and the P-type buffer layer directly below the lower gate surface of the gate electrode is provided with a concave groove.

Description

Field effect transistor with Γ gate and recessed buffer layer and its preparation method

technical field

The invention belongs to the technical field of field effect transistors, in particular to a field effect transistor with a Γ gate and a recessed buffer layer and a preparation method thereof.

Background technique

SiC materials have outstanding material and electrical properties such as wide band gap, high breakdown electric field, high saturated electron migration velocity, and high thermal conductivity, making them suitable for high-frequency and high-power device applications, especially high temperature, high voltage, aerospace, satellite, etc. It has great potential in high-frequency high-power device applications in harsh environments. In SiC allomorphs, the electron mobility of 4H-SiC with hexagonal close-packed wurtzite structure is nearly three times that of 6H-SiC, so 4H-SiC materials are used in high-frequency and high-power devices, especially in metal-semiconductor fields. Effect transistor (MESFET) occupies a major position in the application.

At present, most of the literature is devoted to the research on the structure of the double recessed 4H-SiC MESFET and the improvement on the basis of this structure. The structure is stacked from bottom to top by 4H-SiC semi-insulating substrate, P-type buffer layer, N-type channel layer and N+ cap layer. Based on this stack layer, the N+ cap layer is etched to form a concave N-type In the channel layer, half the length of the source side of the gate is recessed into the N-type channel layer to form a concave gate structure, and the recessed N-type channel layer can be completed by reactive ion etching (RIE) technology.

Although the breakdown voltage of the double-recessed 4H-SiC MESFET is increased due to the fact that half the length of the source side of the gate is recessed into the N-type channel layer, the saturation leakage current has not been substantially improved. And in practice, the process of reactive ion etching (RIE) will form lattice damage on the surface of the drift region of the device, resulting in a decrease in the effective mobility of carriers in the N-type channel layer, thereby reducing the drain current. In terms of current output characteristics Appears as a degradation in saturation current.

Contents of the invention

The present invention overcomes the deficiencies of the prior art, solves the problems of the prior art, and aims to provide a wide channel with deep recesses, which can increase output current and breakdown voltage, and improve frequency characteristics. Field effect transistor with recessed buffer layer and its preparation method.

In order to solve the above-mentioned technical problems, the technical scheme adopted in the present invention is: a field effect transistor with a Γ gate and a recessed buffer layer, which is provided with a 4H-SiC semi-insulating substrate, a P-type buffer layer, and an N-type channel layer from bottom to top , both sides of the N-type channel layer are respectively provided with a source cap layer and a drain cap layer, and the surfaces of the source cap layer and the drain cap layer are respectively provided with a source electrode and a drain electrode, and the middle part of the N-type channel layer And the side close to the source cap layer is provided with a stepped gate electrode, and the left side channel and the right side channel are formed on both sides of the gate electrode and the N-type channel layer, and the lower gate surface of the gate electrode and the N-type channel layer The surface is even, and grooves are arranged on the P-type buffer layer directly below the lower gate surface of the gate electrode.

Further, the gate electrode is a two-layer ladder composed of a low gate and a high gate, and the height difference between the low gate and the high gate is 0.05 μm.

Further, the length of the groove on the P-type buffer layer is 0.3 μm-0.4 μm, and the height is 0.05 μm.

A field-effect transistor with a Γ gate and a recessed buffer layer and a preparation method thereof, are carried out according to the following steps:

Step 1) cleaning the 4H-SiC semi-insulating substrate to remove dirt on the surface of the substrate;

Step 2) epitaxially grow a 0.5 μm thick SiC layer on the 4H-SiC semi-insulating substrate (1), and at the same time dope in situ with diborane B ₂ H ₆ to form P with a concentration of 1.4×10 ¹⁵ cm ^-3 type buffer layer(2);

Step 3) epitaxially growing a 0.3 μm thick SiC layer on the P-type buffer layer (2), and at the same time doping in situ with N ₂ to form an N-type channel layer (3) with a concentration of 3×10 ¹⁷ cm ⁻³ ;

Step 4) epitaxially growing a 0.2 μm thick SiC layer on the N-type channel layer (3), and at the same time doping in situ with N ₂ to form an N ⁺ -type cap layer with a concentration of 1.0×10 ²⁰ cm ^-3 ;

Step 5) sequentially performing photolithography and isolation implantation on the N+ type cap layer to form an isolation region and an active region;

Step 6) Perform source-drain lithography, magnetron sputtering, metal lift-off and superalloy sequentially on the active region to form a source electrode and a drain electrode with a length of 0.5 μm;

Step 7) Perform photolithography and etching twice on the N ⁺ type cap layer between the source electrode and the drain electrode, the thickness of the first etching is 0.2 μm, and the etching depth and length are respectively 0.2 μm and 2.2 μm. Concave channel; the thickness of the second etching is 0.05 μm, and the etching length is 0.85 μm and 1 μm starting from the inside of the source cap layer and the drain cap layer respectively, forming a channel with a length of 0.85 μm and a height of 0.05 μm The left channel depression area and the right channel depression area with a length of 1 μm and a height of 0.05 μm;

Step 8) Perform photolithography and ion implantation on the N-type channel layer to form a recessed buffer layer with a thickness of 0.05 μm, starting at 0.5 μm inside the source cap layer, and a length of 0.35 μm;

Step 9) Perform photolithography, magnetron sputtering and metal lift-off on the concave channel above the channel and close to the side of the source cap layer to form a 0.7 μm long gate electrode;

Step 10) Passivating and back-etching the surface of the formed 4H-SiC metal-semiconductor field-effect transistor, forming electrode pads, and completing the fabrication of the device.

Further, the preparation process of the gate electrode in step 9) is:

a. Use positive photoresist, coating speed: 3000R/min, glue thickness > 2μm to ensure the etching masking effect of the glue during subsequent etching;

b. After gluing, pre-bake in a 90°C oven for 90 seconds, use a concave groove photolithography plate for about 35 seconds of ultraviolet exposure, and then develop in a special developer for 60 seconds. The formula of the special developer: tetramethylammonium hydroxide: Water = 1:3, then post-bake in an oven at 100°C for 3 minutes;

c. Use an ICP inductively coupled plasma etching system for N+ etching. The etching conditions are etching power 375W, bias power 60W, working pressure 9Pa, and the flow rate of the etching gas is 32sccm of CF ₄ and 8sccm of Ar. After etching, a concave channel region with a length of 2.2 μm and a height of 0.2 μm is formed, and the etching masking glue is removed with acetone and ultrasound after etching;

d. Repeat steps a, b, and c by photolithography and etching to form a left channel depression with a length of 0.85 μm and a height of 0.05 μm and a right channel depression with a length of 1 μm and a height of 0.05 μm.

Further, the preparation process of the groove is:

a. Positive photoresist is used, the coating speed is 3000R/min, and the thickness of the glue is >2μm to ensure that it can play a good blocking role in the subsequent isolation injection;

b. After the gluing is completed, pre-bake in an oven at 90°C for 90 seconds, use a sunken buffer layer photolithography plate for about 35 seconds of ultraviolet exposure, and then develop in a special developer for 60 seconds. The formula of the special developer: tetramethylammonium hydroxide: Water = 1:3, then post-bake in an oven at 100°C for 3 minutes;

c. Carry out boron ion implantation, the implantation conditions are 300keV/2×10 ¹² cm ^-2 , and the temperature is 400°C. After the implantation is completed, use acetone and ultrasonic to remove the glue, and then use plasma to remove the glue for 3 minutes; the formation has a thickness of 0.05μm, A groove (11) with a length of 0.3 μm-0.4 μm starting at 0.5 μm inside the source cap layer;

d. Place the above 4H-SiC epitaxial wafer in an induction heating furnace at 1600° C. for 10 minutes to anneal to activate impurities, and the Ar gas flow rate is 20 ml/min to complete the groove ( 11 ).

Compared with the prior art, the present invention has the following beneficial effects.

First, the drain current increases. The maximum output power density of 4H-SiC MESFE devices is proportional to drain saturation current, breakdown voltage and knee voltage. By raising the position of the gate relative to the channel surface, the thickness of the channel under the gate is increased, the depletion region is reduced in the channel, the total charge of the channel flowing through the source and drain regions will increase, and the thickness of the channel under the gate has a significant impact on the channel. The drain current has an important influence, so the saturation leakage current of the device is greatly improved.

Second, the breakdown voltage increases. The breakdown of the MESFET device occurs at the edge of the drain side of the gate, and by raising the position of the gate relative to the channel surface, the concentration of the electric field intensity at the edge of the drain side of the gate is alleviated, and the electric field distribution on the channel surface is adjusted to make the breakdown The voltage increases.

Third, frequency characteristics are improved. By introducing grooves, the thickness of the channel under the low gate remains unchanged, ensuring that the leakage current can be effectively controlled by the gate voltage, and preventing the depletion region from expanding to the source/drain region, making the depletion region under the gate smaller, thereby Reduce gate-source and gate-drain capacitance. The reduced gate-source capacitance improves the frequency characteristics of MESFET devices.

Description of drawings

Below in conjunction with accompanying drawing, the present invention will be described in further detail

Fig. 1 is a structural schematic diagram of the present invention.

In the figure: 1 is the 4H-SiC semi-insulating substrate, 2 is the P-type buffer layer, 3 is the N-type channel layer, 4 is the source cap layer, 5 is the drain cap layer, 6 is the source electrode, and 7 is the leakage current 8 is the left channel, 9 is the right channel, 10 is the gate electrode, and 11 is the groove.

Detailed ways

As shown in Figure 1, a field effect transistor with a Γ gate and a recessed buffer layer is provided with a 4H-SiC semi-insulating substrate 1, a P-type buffer layer 2, an N-type channel layer 3, and an N-type channel layer from bottom to top. Both sides of the layer 3 are provided with a source cap layer 4 and a drain cap layer 5 respectively, and the surfaces of the source cap layer 4 and the drain cap layer 5 are respectively provided with a source electrode 6 and a drain electrode 7, which are characterized in that: The middle part of the N-type channel layer 3 and the side close to the source cap layer 4 are provided with a stepped gate electrode 10, and the left side channel 8 and the right side channel 9 are formed on both sides of the gate electrode 10 and the N-type channel layer 3 , the lower gate surface of the gate electrode 10 is flush with the surface of the N-type channel layer 3 , and the P-type buffer layer 2 directly below the lower gate surface of the gate electrode 10 is provided with a groove 11 . The gate electrode 10 is a two-layer ladder composed of a low gate and a high gate, and the height difference between the low gate and the high gate is 0.05 μm. The groove 11 on the P-type buffer layer 2 has a length of 0.3 μm-0.4 μm and a height of 0.05 μm.

Embodiment one

A field effect transistor with a Γ gate and a recessed buffer layer having a groove 11 with a height and a length of 0.05 μm and 0.35 μm was prepared. Follow the steps below:

Step 1) cleaning the 4H-SiC semi-insulating substrate 1 to remove dirt on the surface of the substrate;

a. Carefully clean the substrate two or three times with a cotton ball dipped in methanol to remove SiC particles of various sizes on the surface;

b. Sonicate the 4H-SiC semi-insulating substrate 1 in H ₂ SO ₄ :HNO ₃ =1:1 for 5 minutes;

c. Boil the 4H-SiC semi-insulating substrate 1 in 1# cleaning solution (NaOH:H ₂ O ₂ :H ₂ O=1:2:5) for 5 minutes, then rinse with deionized water for 5 minutes before putting it into Boil in 2# cleaning solution (HCl:H ₂ O ₂ :H ₂ O=1:2:7) for 5 minutes, rinse with deionized water and dry with N2 for later use.

Step 2) epitaxially grow a 0.5 μm thick SiC layer on the 4H-SiC semi-insulating substrate 1, and at the same time dope in-situ with diborane B ₂ H ₆ to form a P-type buffer with a concentration of 1.4×10 ¹⁵ cm ^-3 Layer 2;

The specific operation process is: put the 4H-SiC semi-insulating substrate 1 into the growth chamber, then feed silane with a flow rate of 20ml/min, propane with a flow rate of 10ml/min, and high-purity hydrogen with a flow rate of 80l/min into the growth chamber, and at the same time 2ml/min of B ₂ H ₆ (diluted to 5% in H ₂ ), the growth temperature is 1550°C, the pressure is 105Pa, lasts 6min, and the doping concentration and thickness are 1.4×10 ¹⁵ cm ^-3 and 0.4 The p-type buffer layer 2 of μm-0.5μm is fabricated.

Step 3) Epitaxially grow a 0.3 μm thick SiC layer on the P-type buffer layer 2, and at the same time do in-situ doping with N ₂ to form an N-type channel layer 3 with a concentration of 3×10 ¹⁷ cm ⁻³ ;

The specific operation process is: put the 4H-SiC epitaxial wafer into the growth chamber, feed silane at a flow rate of 20ml/min, propane at 10ml/min and high-purity hydrogen at 80l/min into the growth chamber, and simultaneously feed 2ml/min N ₂ , the growth temperature is 1550° C., the pressure is 105 Pa, and lasts for 3 minutes to complete the fabrication of N-type channel layer 3 with doping concentration and thickness of 3×10 ¹⁷ cm ⁻³ and 0.3 μm, respectively.

Step 4) Epitaxially grow a 0.2 μm thick SiC layer on the N-type channel layer 3, and at the same time do in-situ N2 doping to form an N+-type cap layer with a concentration of 1.0×10 ²⁰ cm ^-3 ;

The specific operation process is: put the 4H-SiC epitaxial wafer into the growth chamber, feed silane at a flow rate of 20ml/min, propane at 10ml/min and high-purity hydrogen at 80l/min into the growth chamber, and simultaneously feed 20ml/min N ₂ , the growth temperature is 1550°C, the pressure is 105Pa, and lasts for 2min to form an N+ cap layer with a doping concentration and thickness of 1.0×10 ²⁰ cm ^-3 and 0.2μm, respectively.

Step 5) Perform photolithography and isolation implantation sequentially on the N+ type cap layer to form an isolation region and an active region; the specific operation process is:

a. Positive photoresist is used, the coating speed is 3000R/min, and the thickness of the glue is >2μm to ensure that it can play a good blocking role in the subsequent isolation injection;

b. After the coating is completed, pre-bake in a 90°C oven for 90 seconds, use an isolation injection photoresist for about 35 seconds of UV exposure, and then develop in a special developer for 60 seconds to expose 4H-SiC, and then post-bake in a 100°C oven 3 minutes, the formula ratio of described special developing solution is tetramethyl ammonium hydroxide: water=1:3;

c. Perform boron ion implantation twice. The implantation conditions are 130keV/6×10 ¹² cm ^-2 and 50keV/2×10 ¹² cm ^-2 . After the implantation is completed, use acetone + ultrasonic to remove the glue, and then use plasma to remove the glue for 3 minutes. Complete the isolation implant outside the active area;

d. Place the above-mentioned 4H-SiC epitaxial wafer in an induction heating furnace at 1600° C. for 10 minutes to anneal to activate impurities, and the Ar gas flow rate is 20 ml/min.

Step 6) Perform source-drain lithography, magnetron sputtering, metal lift-off and superalloy sequentially on the active area to form 0.5 μm long source electrode 6 and drain electrode 7; the specific operation process is: a. PMMA+AZ1400 double-layer glue, the glue thickness should be > 1.2μm. After the film is cleaned, apply PMMA glue first. The speed is 4000R/min, and the glue thickness is about 0.5μm. The thickness of AZ1400 glue is about 0.8μm;

b. Pre-bake in an oven at 90°C for 90 seconds, use a source-drain photolithography plate for 15 seconds of UV exposure, develop with a special developer for 50 seconds to remove the AZ1400 glue, then perform pan exposure on the PMMA glue, and develop with toluene for 3 minutes, then Post-bake in an oven at 100°C for 3 minutes to complete the metallization window of the source and drain regions, and the formula ratio of the special developer is tetramethylammonium hydroxide: water = 1:4;

c. Using a multi-target magnetron sputtering table, sequentially sputter Ni, 150nm Ti and 300nm Au multi-layer metals with a thickness of 150nm at room temperature as the source-drain ohmic contact metal, where the working vacuum is 2.5×10-3Pa, and the Ar flow rate is 40sccm ;

d. After the sputtering is completed, put the chip into the Buty special stripping solution at 150°C, and then move it into the Buty stripping solution at 130°C after the metal falls off. When the temperature drops below 80°C, put the chip into acetone, take out the chip and use it Blow dry with nitrogen, and finally plasma degumming for 2 minutes;

e. Put the sheet into a fast alloy furnace, and rapidly raise the temperature (970/1min) to the alloy temperature for 10 minutes under the protection of a nitrogen-hydrogen atmosphere (N ₂ :H ₂ =9:1) to form the source electrode 6 and the drain electrode 7 .

Step 7) Perform photolithography and etching twice on the N ⁺ type cap layer between the source electrode 6 and the drain electrode 7, the thickness of the first etching is 0.2 μm, and the etching depth and length are respectively 0.2 μm and 2.2 μm. μm concave channel; the thickness of the second etching is 0.05 μm, and the etching length is 0.85 μm and 1 μm starting from the inside of the source cap layer 4 and the drain cap layer 5 respectively, forming a channel with a length of 0.85 μm and a height of 0.05 μm left side channel 8 depressions and 1 μm length and 0.05 μm right side channel 9 depressions;

a. Use positive photoresist, coating speed: 3000R/min, glue thickness > 2μm to ensure the etching masking effect of the glue during subsequent etching;

b. After gluing, pre-bake in a 90°C oven for 90 seconds, use a concave groove photolithography plate for about 35 seconds of ultraviolet exposure, and then develop in a special developer for 60 seconds. The formula of the special developer: tetramethylammonium hydroxide: Water = 1:3, then post-bake in an oven at 100°C for 3 minutes;

c. Using ICP inductively coupled plasma etching system for N ⁺ etching, the etching conditions are etching power 375W, bias power 60W, working pressure 9Pa, and the flow rate of etching gas is 32sccm CF ₄ and 8sccm Ar, After etching, a concave channel region with a length of 2.2 μm and a height of 0.2 μm is formed, and after etching, the etching masking glue is removed with acetone and ultrasound.

d. Repeat steps a, b, and c for photolithography and etching to form the left channel 8 depressions with a length of 0.85 μm and a height of 0.05 μm and the right channel 9 depressions with a length of 1 μm and a height of 0.05 μm Area.

Step 8) Perform photolithography and ion implantation on the N-type channel layer (3) to form a concave buffer with a thickness of 0.05 μm, starting from the inner side of the source cap layer (4) at 0.5 μm, and a length of 0.35 μm Floor;

a. Positive photoresist is used, the coating speed is 3000R/min, and the thickness of the glue is >2μm to ensure that it can play a good blocking role in the subsequent isolation injection;

b. After the gluing is completed, pre-bake in an oven at 90°C for 90 seconds, use a sunken buffer layer photolithography plate for about 35 seconds of ultraviolet exposure, and then develop in a special developer for 60 seconds. The formula of the special developer: tetramethylammonium hydroxide: Water = 1:3, then post-bake in an oven at 100°C for 3 minutes;

c. Performing boron ion implantation, the implantation condition is 300keV/2×10 ¹² cm ^-2 , and the temperature is 400°C. After the injection is completed, use acetone and ultrasonic to remove the glue, and then use plasma to remove the glue for 3 minutes; form a groove with a thickness of 0.05 μm, starting at the inner side of the source cap layer at 0.5 μm, and a length of 0.35 μm;

d. Place the above-mentioned 4H-SiC epitaxial wafer in an induction heating furnace at 1600° C. for 10 minutes to anneal to activate the impurities, and the Ar gas flow rate is 20 ml/min to complete the fabrication of the groove 11 .

Step 9) Perform photolithography, magnetron sputtering and metal lift-off on the concave channel above the channel and close to the side of the source cap layer 4 to form a 0.7 μm long gate electrode 10;

The specific operation process is as follows: a. PMMA+AZ1400 double-layer glue is used for photolithography masking glue, and the glue thickness is required to be >1.2 μm. After the sheet is cleaned, apply PMMA glue at a speed of 4000R/min, the thickness of the glue is about 0.5μm, and then pre-bake it in an oven at 200°C for 120 seconds, and then apply AZ1400 glue with a thickness of about 0.8μm after taking it out;

b. Pre-bake in an oven at 90°C for 90 seconds, use a grid photolithography plate for 15 seconds of UV exposure, and develop with a special developer (tetramethylammonium hydroxide: water = 1:4) for 50 seconds to remove the AZ1400 glue, and then apply PMMA The glue was flood-exposed, developed with toluene for 3 minutes, and then post-baked in an oven at 100°C for 3 minutes;

c. Using a multi-target magnetron sputtering table, sequentially sputter Ni, 150nm Ti and 300nm Au multilayer metals at room temperature as source-drain ohmic contact metals, where the working vacuum is 2.5×10 ^-3 Pa, Ar flow rate 40sccm, the chip is heated to 150°C during the sputtering process;

d. After the sputtering is completed, put the chip into the 150°C Buty special stripping solution, and then move it into the 130°C Buty stripping solution after the metal falls off. When the temperature drops below 80°C, then move the chip into acetone, and finally take out the chip Slowly blow dry with nitrogen gas at a small flow rate, and finally use plasma to remove glue for 3 minutes to complete the fabrication of the gate electrode 10 .

Step 10) Passivating and back-etching the surface of the formed field effect transistor to form electrode pads to complete the fabrication of the device.

The specific operation process is:

a. At 300°C, SiH4 with a flow rate of 300 sccm, NH _{3 with} 323 sccm and N ₂ with 330 sccm are simultaneously fed into the reaction chamber, and Si ₃ with a thickness of 0.5 μm is deposited on the surface through a plasma-enhanced chemical vapor deposition process The N ₄ layer is used as a passivation medium layer;

b. Positive photoresist is used for passivation lithography, the glue coating speed is 3000R/mins, and the thickness of the glue is required to be > 2μm. After the glue coating is completed, it is pre-baked in an oven at 90°C for 90 seconds, and then the anti-etching photolithography plate is used for 35 seconds. Expose, develop for 60 seconds with a special developer, and finally post-bake in an oven at 100°C for 3 minutes. The formula ratio of the special developer is tetramethylammonium hydroxide: water = 1:3;

c. Si ₃ N ₄ is etched using the RIE process. The etching gas flow rate is 50 sccm CHF ₃ and the flow rate is 5 sccm Ar. After completion, perform plasma deglue for 3 minutes to expose the metal and form source, drain and gate electrodes 6, 7 , 10 pressure solder joints to complete the production of the entire device.

Embodiment two

Field effect transistors with a Γ gate and a recessed buffer layer were fabricated with groove heights and lengths of 0.05 μm and 0.3 μm. The difference between this embodiment and Embodiment 1 lies in step 8)

a. Positive photoresist is used, the coating speed is 3000R/min, and the thickness of the glue is >2μm to ensure that it can play a good blocking role in the subsequent isolation injection;

b. After the gluing is completed, pre-bake in an oven at 90°C for 90 seconds, use a sunken buffer layer photolithography plate for about 35 seconds of ultraviolet exposure, and then develop in a special developer for 60 seconds. The formula of the special developer: tetramethylammonium hydroxide: Water = 1:3, then post-bake in an oven at 100°C for 3 minutes;

c. Performing boron ion implantation, the implantation condition is 300keV/2×10 ¹² cm ^-2 , and the temperature is 400°C. After the injection is completed, use acetone and ultrasonic to remove the glue, and then use plasma to remove the glue for 3 minutes; form a groove with a thickness of 0.05 μm, starting at the inner side of the source cap layer at 0.5 μm, and a length of 0.3 μm;

d. Place the above-mentioned 4H-SiC epitaxial wafer in an induction heating furnace at 1600° C. for 10 minutes to anneal to activate the impurities, and the Ar gas flow rate is 20 ml/min to complete the fabrication of the groove 11 .

Embodiment Three

A field effect transistor with a Γ gate and a recessed buffer layer with a groove height and length of 0.05 μm and 0.4 μm was prepared. The difference between this embodiment and Embodiment 1 lies in step 8).

a. Positive photoresist is used, the coating speed is 3000R/min, and the thickness of the glue is >2μm to ensure that it can play a good blocking role in the subsequent isolation injection;

b. After the gluing is completed, pre-bake in an oven at 90°C for 90 seconds, use a sunken buffer layer photolithography plate for about 35 seconds of ultraviolet exposure, and then develop in a special developer for 60 seconds. The formula of the special developer: tetramethylammonium hydroxide: Water = 1:3, then post-bake in an oven at 100°C for 3 minutes;

c. Performing boron ion implantation, the implantation condition is 300keV/2×10 ¹² cm ^-2 , and the temperature is 400°C. After the injection is completed, use acetone and ultrasonic to remove the glue, and then use plasma to remove the glue for 3 minutes; form a groove with a thickness of 0.05 μm, starting at the inner side of the source cap layer at 0.5 μm, and a length of 0.4 μm;

d. Place the above-mentioned 4H-SiC epitaxial wafer in an induction heating furnace at 1600° C. for 10 minutes to anneal to activate the impurities, and the Ar gas flow rate is 20 ml/min to complete the fabrication of the groove 11 . In summary, the 4H-SiC metal-semiconductor field effect transistor of the present invention has the effects of increased drain current and breakdown voltage, and improved frequency characteristics.

The above content has been described in detail for specific embodiments of the present invention in combination with the accompanying drawings of the embodiments. Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other. The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Within the scope of knowledge of those of ordinary skill in the art, various modifications can be made without departing from the gist of the present invention. kind of change.

Claims (4)

1. the field-effect transistor with Γ grid and the buffer layer that is recessed, is provided with 4H-SiC semi-insulating substrate (1), P from bottom to top Type buffer layer (2), N-type channel layer (3), the both sides of N-type channel layer (3) are respectively arranged with source electrode cap layers (4) and drain electrode cap layers (5), the surface of the source electrode cap layers (4) and drain electrode cap layers (5) is respectively arranged with source electrode (6) and drain electrode (7), and feature exists In：Stair-stepping gate electrode (10), gate electrode (10) are provided in the middle part of N-type channel layer (3) and close to the side of source electrode cap layers (4) Left side raceway groove (8) and right side channel (9), low grid face and the N-type channel layer of gate electrode (10) are formed with N-type channel layer (3) both sides (3) flush is set fluted (11) on the p-type buffer layer (2) immediately below the low grid face of gate electrode (10)；The gate electrode (10) it is made of for two layers of ladder low grid and high grid, the difference in height of the low grid and high grid is 0.05 μm；On p-type buffer layer (2) The length of groove (11) is 0.3 μm -0.4 μm, is highly 0.05 μm.

2. field-effect transistor according to claim 1 with Γ grid and the buffer layer that is recessed and preparation method thereof, special Sign is：It follows the steps below：

Step 1) cleans 4H-SiC semi-insulating substrate (1), to remove substrate surface dirt；

The SiC layer of step 2) 0.5 μ m-thick of epitaxial growth in 4H-SiC semi-insulating substrate (1), while through diborane B₂H₆It mixes original position It is miscellaneous, form a concentration of 1.4 × 10¹⁵cm^-3P-type buffer layer (2)；

The SiC layer of step 3) 0.3 μ m-thick of epitaxial growth on p-type buffer layer (2), while through N₂Doping in situ, forms a concentration of 3 ×10¹⁷cm^-3N-type channel layer (3)；

The SiC layer of step 4) 0.2 μ m-thick of epitaxial growth on N-type channel layer (3), while through N₂Doping in situ, forms a concentration of 1.0×10²⁰cm^-3N⁺Type cap layers；

Step 5) is in N⁺Photoetching is carried out in type cap layers successively and isolation is injected, forms isolated area and active area；

Step 6) carries out active area source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy successively, forms 0.5 μm long Source electrode (6) and drain electrode (7)；

N of the step 7) between source electrode (6) and drain electrode (7)⁺Type cap layers and N-type channel layer (3) carry out Twi-lithography, etching, First time etch thicknesses are 0.2 μm, and formation etching depth and length are respectively 0.2 μm and 2.2 μm of chase road；Second of etching Thickness is 0.05 μm, etching length with source electrode cap layers (4) and drain electrode cap layers (5) it is inboard be starting point be respectively 0.85 μm and 1 μm, shape Into being 0.85 μm with length, it is 1 μm highly for 0.05 μm of left side raceway groove (8) depressed area and length, is highly 0.05 μm of right side Lateral sulcus road (9) depressed area；

Step 8) carries out a photoetching and ion implanting to N-type channel layer (3), and it is 0.05 μm that being formed, which has thickness, with source electrode cap It is starting point at layer (4) is 0.5 μm inboard, length is 0.35 μm of recess buffer layer；

Step 9) carries out photoetching, magnetron sputtering and metal-stripping above raceway groove and close to the chase road of source electrode cap layers (4) side, Form 0.7 μm of long gate electrode (10)；

Step 10) is passivated the 4H-SiC metal-semiconductor field effect transistors surface formed, anti-carves, and forms electrode pressure Solder joint completes the making of device.

3. field-effect transistor according to claim 2 with Γ grid and the buffer layer that is recessed and preparation method thereof, special Sign is：Specifically preparation process is the step 9)：

A, using positive photoresist, application rate：3000R/min, the etching masking that 2 μm of glue thickness ＞ ensures the glue in subsequent etching Effect；

B, after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, carried out after about 35 seconds uv-exposures special using chase road photolithography plate Developed 60 seconds in developer solution, the formula of special developer solution：Tetramethyl aqua ammonia:Water=1:3, then in 100 DEG C of baking ovens It dries 3 minutes afterwards；

C, N+ etchings are carried out using ICP sense couplings system, etching condition is etching power 375W, biasing work( Rate 60W, operating pressure 9Pa, etching gas select CF of the flow for 32sccm₄With the Ar of 8sccm, formation length is after etching 2.2 μm, be highly 0.2 μm of recessed channel region, with acetone and ultrasound removal etching masking glue after etching；

D, it is 0.85 μm to repeat a, b, step c photoetching, etching formation with length, and the highly left side raceway groove (8) for 0.05 μm is recessed It falls into area and is 1 μm with length, be highly 0.05 μm right side channel (9) depressed area.

4. field-effect transistor according to claim 1 with Γ grid and the buffer layer that is recessed and preparation method thereof, special Sign is：The preparation process of groove (11) is：

A, using positive photoresist, application rate：3000R/min, 2 μm of glue thickness ＞ ensure to play in follow-up isolation injection Good barrier effect；

B, after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, after carrying out about 35 seconds uv-exposures using recess buffer layer photolithography plate Develop 60 seconds in special developer solution, the formula of special developer solution：Tetramethyl aqua ammonia:Water=1:3, then in 100 DEG C of baking ovens In after dry 3 minutes；

C, boron ion injection is carried out, injection condition is 300keV/2 × 10¹²cm^-2, temperature is 400 DEG C, and acetone is used after the completion of injection And ultrasonic depolymerization, then with the removing of photoresist by plasma 3 minutes；It is 0.05 μm that being formed, which has thickness, to be at inboard 0.5 μm of source electrode cap layers Point, length are 0.3 μm -0.4 μm of groove (11)；

D, above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar throughputs are 20ml/min completes the making of groove (11).