CN102637726A - MS (Metal-Semiconductor)-grid GaN-based enhanced transistor with high electron mobility and manufacture method thereof - Google Patents

Abstract

The invention discloses a metal-semiconductor MS gate GaN-based enhanced high electron mobility transistor and a manufacturing method, which mainly solve the problems of low threshold voltage, poor controllability and low reliability of the existing GaN-based enhanced device. The device includes: a substrate (1), a transition layer (2), a GaN main buffer layer (3), an N-type AlGaN main barrier layer (4), and both sides of the top of the N-type AlGaN main barrier layer (4) are sources pole (9) and drain (10), a groove (5) is etched in the middle of the GaN main buffer layer (3), and the inner wall of the groove (5) is successively provided with a GaN sub-buffer layer (6), an AlGaN A dielectric (8) is provided outside the source and drain above the N-type AlGaN main barrier layer (4) on both sides of the sub-potential barrier layer (7) and the grid (13). The invention has the advantages of high threshold voltage, good controllability, high current density, excellent pinch-off characteristics, mature technology, good repeatability and high reliability, and can be used in high-power switches and digital circuits.

Description

MS gate GaN-based enhancement-type high electron mobility transistor and manufacturing method

technical field

The invention belongs to the technical field of microelectronics and relates to semiconductor devices, specifically a metal semiconductor MS gate GaN-based enhanced high electron mobility transistor and its manufacture, which can be used to make high-temperature and high-power devices and as the basic unit of digital integrated circuits.

Background technique

With the development of modern weaponry and aerospace, nuclear energy, communication technology, automotive electronics, and switching power supplies, higher requirements are placed on the performance of semiconductor devices. As a typical representative of wide bandgap semiconductor materials, GaN-based materials have the characteristics of large bandgap width, high electron saturation drift velocity, high critical breakdown field strength, high thermal conductivity, good stability, corrosion resistance, and radiation resistance. Used in the production of high temperature, high frequency and high power electronic devices. In addition, GaN also has excellent electronic properties, and can form a modulation-doped AlGaN/GaN heterostructure with AlGaN. This structure can obtain an electron mobility higher than 1500 cm ² /Vs at room temperature, and a maximum of 3×10 ⁷ cm /s peak electron velocity and 2×10 ⁷ cm/s saturation electron velocity, and obtained a two-dimensional electron gas density higher than that of the second-generation compound semiconductor heterostructure, known as an ideal material for the development of microwave power devices . Therefore, the high electron mobility transistor HEMT based on AlGaN/GaN heterojunction has a very good application prospect in microwave high-power devices.

Due to the unique advantages of AlGaN/GaN heterojunction, the growth of AlGaN/GaN heterojunction materials and the development of AlGaN/GaN HEMT devices have always occupied the main position in the research of GaN electronic devices. However, most of the research work on GaN-based electronic devices in the past decade has focused on depletion-mode AlGaN/GaN HEMT devices. Type devices become very difficult, so the study of high-performance AlGaN/GaN enhancement-mode HEMTs is of great significance.

AlGaN/GaN enhanced HEMT has broad application prospects. First of all, GaN-based materials are known as ideal materials for the development of microwave power devices, and enhanced devices can greatly reduce the complexity and cost of circuits due to the reduction of negative voltage sources in circuits such as microwave power amplifiers and low-noise amplifiers. And the AlGaN/GaN enhanced HEMT device has good circuit compatibility in microwave high-power devices and circuits. At the same time, the development of enhanced devices makes it possible to monolithically integrate digital circuits of depletion-mode/enhanced devices. Moreover, in terms of power switching applications, AlGaN/GaN enhanced HEMTs also have great application prospects. Therefore, research on high-performance AlGaN/GaN enhancement-mode HEMT devices has received great attention.

At present, there are many reports on AlGaN/GaN enhanced HEMTs both domestically and internationally. Due to the immature P-type Mg doping process technology, the Mg activation energy in GaN-based materials is high and the ionization rate is low, resulting in low hole concentration and high mobility in the device. Therefore, the current international research on AlGaN/GaN enhanced HEMT It is not based on the method of P-type Mg doping, but other new technologies are used. Currently, the following technologies are mainly reported:

1. F ion implantation technology, that is, plasma implantation technology based on fluoride CF4. Yong Cai et al. of Hong Kong University of Science and Technology successfully developed an enhanced HEMT device based on F ion implantation technology. The device passes through the AlGaN/GaN HEMT gate F ions are implanted into the AlGaN barrier layer. Due to the strong negative charge of F ions, the F ions in the barrier layer can provide stable negative charges, and thus can effectively deplete the strong two-dimensional electron gas in the channel region. When AlGaN When the number of F ions in the barrier layer reaches a certain amount, the two-dimensional electron gas in the channel under the gate is completely exhausted, thereby realizing an enhanced HEMT device. However, the F-implantation technology will inevitably introduce material damage, and the controllability of the device threshold voltage is not high. The thin layer carrier concentration of the device is as high as 1.3×10 ¹³ cm ^-2 at room temperature, the mobility is 1000cm ² /Vs, the threshold voltage reaches 0.9V, and the maximum drain current reaches 310mA/mm. See Yong Cai, Yugang Zhou, Kevin J. Chen and Kei May Lau, "High-performanceenhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment", IEEE Electron Device Lett, Vol.26, No.7, JULY 2005.

蓝宝石上的a面

n-AlGaN/GaNHEMT实现了器件的增强，由于非极性或半极性材料由于缺少极化效应，因此其二维电子气浓度很小甚至没有，所以基于非极性或半极性材料的AlGaN/GaN HEMT器件具有增强特性。其报道的阈值电压为-0.5V，通过降低参杂浓度可进一步增大器件阈值电压，但其器件特性并不好，其电子迁移率只有5.14cm²/Vs，室温下方块电阻很大。且其栅漏电大小在Vgs＝-10V时达到了1.1×10^-5A/mm。参见文献Masayuki Kuroda，Hidetoshi Ishida，Tetsuzo Ueda，and Tsuyoshi Tanaka，“Nonpolar(11-20)plane AlGaN/GaN heterojunction field effecttransistors on(1-102)plane sapphire”，Journal of Aplied Phisics，Vol.102，No.9，November2007。2. Non-polar or semi-polar GaN materials realize enhancement devices, and Masayuki Kuroda et al. successfully used r-plane

side a on sapphire

n-AlGaN/GaNHEMT realizes the enhancement of the device. Due to the lack of polarization effect of non-polar or semi-polar materials, its two-dimensional electron gas concentration is small or even non-existent. Therefore, AlGaN based on non-polar or semi-polar materials /GaN HEMT devices have enhanced characteristics. The reported threshold voltage is -0.5V, and the threshold voltage of the device can be further increased by reducing the dopant concentration, but the device characteristics are not good, the electron mobility is only 5.14cm ² /Vs, and the sheet resistance at room temperature is very large. And its gate leakage reaches 1.1×10 ^-5 A/mm when Vgs=-10V. See literature Masayuki Kuroda, Hidetoshi Ishida, Tetsuzo Ueda, and Tsuyoshi Tanaka, "Nonpolar (11-20) plane AlGaN/GaN heterojunction field effect transistors on (1-102) plane sapphire", Journal of Aplied Phisics, Vol.102, No. 9, November 2007.

3. Thin barrier layer technology. In 1996, M.Asif Khan and others first realized the AlGaN/GaN enhanced HEMT device with 10nm AlGaN thin barrier layer technology. The thin barrier layer AlGaN/GaN enhanced HEMT device is due to the potential The thickness of the barrier layer is thinned, its polarization effect is weakened, and the concentration of two-dimensional electron gas in the channel caused by the polarization effect is reduced, so that the threshold voltage of the device is shifted to the right. But the results they obtained are not ideal, the peak transconductance is only 23mS/mm. See M.Asif Khan, Q.Chen, C.J.Sun, J.W.Yang, and M.Blasingame, "Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors", Appl.Phys.Lett, Vol.68, No.4, January 1996.

4. Groove gate technology, W.B.Lanford et al. used groove gate technology to make an enhanced device with a threshold voltage of 0.47V through MOCVD. The device structure includes from bottom to top: SiC substrate, nucleation layer, 2um thick GaN, 3nm thick AlGaN, 10nm thick n-AlGaN, 10nm thick AlGaN. After ohmic annealing, instead of directly evaporating the gate metal electrode, a groove is etched in the pre-grown gate area by dry ICP-RIE method, and then rapid thermal annealing is performed in a nitrogen atmosphere at 700 °C, and then the groove is etched. A Ni/Au Schottky contact gate electrode is made on the gate window. The trench gate technology makes the barrier layer under the gate thinner by etching the barrier layer under the gate to a certain depth, thereby reducing the concentration of 2DEG under the gate, while the carrier concentration in the source and drain regions remains unchanged at a relatively large value. It can not only realize the enhanced characteristics of the device, but also ensure a certain current density. The epitaxial growth of enhancement-mode devices realized by trench gate technology is easy to control, but its controllability is poor, and the etching process will cause damage. See W.B.Lanford, T.Tanaka, Y.Otoki and I.Adesida, "Recessed-gate enhancement-mode GaN HEMT with highthreshold voltage", Electronics Letrers, Vol.41, No.7, March 2005.

5. AlGaN/GaN grooved MIS gate HFET structure, Tohru Oka et al. used the grooved MIS gate HFET structure to achieve a threshold voltage up to 5.2V. The epitaxial layer structure is from bottom to top: Si substrate, buffer layer, after 800nm Al _0.05 Ga _0.95 N buffer layer, 40nm thick GaN channel layer, 34nm thick Al _0.25 Ga _0.75 N, 1nm thick AlN barrier layer, 1nm thick GaN cap layer. During the manufacturing process of the device, the barrier layer under the gate window is completely etched by the inductively coupled plasma ICP based on SiCl ₄ /Cl ₂ , and after five minutes of annealing in the N ₂ atmosphere at 500 ° C, the plasma-enhanced chemical vapor phase is used to Deposit PECVD to etch a layer of SiN with a thickness of 20nm as the gate dielectric, which is also a passivation layer, and then deposit W-based metal as the gate metal. In this way, the MIS gate device is formed, because there is no heterojunction structure in the region under the gate, so there is no two-dimensional electron gas, so a high threshold enhancement type can be realized, but this structure also has certain problems, because the heterojunction under the gate is completely covered Etched away, resulting in low device mobility, low current density, and high on-resistance. References Tohru Oka, To mohiro Nozawa, "AlGaN/GaN Recessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications", IEEE Electron Device Lett, VOL.29, NO.7, JULY2008.

To sum up, at present, AlGaN/GaN HEMT enhancement devices in the world are mainly formed based on trench gate technology and fluorine ion implantation technology, which have the following shortcomings:

(1) Due to the trade-off relationship between threshold voltage and current density, it is difficult to achieve coexistence of high threshold voltage and high current density, and the regulation of threshold voltage is poor;

(2) Both etching to form trench gates and fluorine ion implantation will cause damage to the material. Although a certain amount of damage can be eliminated after annealing, the remaining damage will still affect the performance and reliability of the device. At the same time, the current repeatability of this process not high;

(3) When forming short-channel devices for microwave applications, it is necessary to use high-end process equipment such as electron beam direct writing to produce short gate lengths, and the process is relatively difficult.

Contents of the invention

The purpose of the present invention is to overcome the defects of the above-mentioned prior art, and propose an MS-gate GaN-based enhanced high electron mobility transistor and its manufacturing method from the perspective of optimizing the vertical structure of the device, so as to reduce the difficulty of the process and avoid the damage, increase the threshold voltage of the device, enhance the controllability of the threshold voltage of the device, and improve the reliability of the device.

In order to achieve the above object, the high electron mobility transistor of the present invention includes: comprising: a substrate, a transition layer, a GaN main buffer layer, an N-type AlGaN main barrier layer, a source and a drain; the transition layer is located above the substrate; the GaN The main buffer layer is located above the transition layer; the two sides above the GaN main buffer layer are N-type AlGaN main barrier layers; the top sides of the N-type AlGaN main barrier layer are respectively source and drain; it is characterized in that the GaN main buffer layer A groove is etched in the middle of the groove, and the inner wall of the groove is successively epitaxial with a GaN sub-buffer layer and an AlGaN sub-barrier layer; the gate electrode is deposited on the AlGaN sub-barrier layer and covers the entire groove area; both sides of the groove A dielectric is provided outside the source and drain above the N-type AlGaN main barrier layer.

The bottom surface of the groove is a 0001 polar surface, and the side surface of the groove is a non-0001 surface.

The main two-dimensional electron gas 2DEG channel is formed at the interface between the GaN main buffer layer and the AlGaN main barrier layer, and the channel is located on both sides of the groove; the GaN sub-buffer layer and the AlGaN sub-barrier layer in the groove The interface forms an auxiliary two-dimensional electron gas 2DEG channel.

The horizontal position of the auxiliary two-dimensional electron gas 2DEG channel is lower than the horizontal position of the main two-dimensional electron gas 2DEG channel.

The main barrier layer is N-type doped with a doping concentration of 5×10 ¹⁹ cm ⁻³ .

In order to achieve the above object, the fabrication method of the metal-semiconductor MS gate GaN-based enhanced high electron mobility transistor of the present invention comprises the following steps:

1) Pretreating the surface of the substrate in the metal organic chemical vapor deposition MOCVD reaction chamber;

2) Epitaxial growth of AlGaN/GaN epitaxial layer on the substrate, in which the thickness of GaN is 1um-4um, the thickness of N-type doped Al _x Ga _1-x N barrier layer is 16nm-36nm, and the molar content of Al element x 20%-30%;

3) Deposit a mask dielectric layer on the epitaxial layer, then perform photolithography, and etch the dielectric layer on the epitaxial layer by wet etching, and form a groove with a length of 0.5um on the epitaxial layer ;

4) Photoetching out the groove area, and using the reactive ion etching RIE method to etch the AlGaN/GaN epitaxial layer in the groove area, the etching depth is 40nm-150nm;

5) Keep the mask dielectric layer outside the groove, pass the etched epitaxial layer through the metal organic chemical vapor deposition MOCVD reaction chamber, and grow a 20nm-110nm thick GaN layer and a 16nm thick GaN layer in the direction vertically upward along the bottom of the groove. ～36nm thick AlGaN layer, grow 10nm～55nm thick GaN layer and 8nm～18nm thick AlGaN layer along the groove side direction;

6) removing the mask dielectric layer;

7) On the epitaxial layer from which the mask dielectric layer has been removed, a dielectric layer with a thickness of 10 nm to 60 nm is deposited by chemical vapor deposition CVD or physical vapor deposition PVD;

8) On the dielectric layer, the source, drain, and gate regions are first photoetched, and then the source, drain, and gate windows are etched;

9) Lithograph the source and drain regions, and then on the epitaxial layer after photolithography, use Ti/Al/Ni/Au four-layer metal with an electron beam evaporation thickness of 30nm/180nm/40nm/60nm as the ohmic contact metal. Form source and drain contact electrodes after stripping and annealing;

10) Photoetching out the gate area, and using electron beam evaporation of Ni/Au two-layer metal with a thickness of 30nm/200nm on the epitaxial layer after photolithography as the gate metal, and forming the gate of the metal semiconductor MS after stripping;

11) Photolithography has formed the device surface of source, drain and gate, obtained thickened electrode pattern, and used electron beam evaporation technology to thicken the electrode to complete the device production.

The process conditions for the electron beam evaporation in step 9) and step 10) are: the degree of vacuum is less than 2.0×10 ^-6 Pa, the power is 200W, and the evaporation rate is less than or equal to angstroms/second.

The process conditions of step 4) etching the AlGaN/GaN epitaxial layer are: the flow rate of chlorine Cl ₂ is 15 sccm, the power is 200W, and the pressure is 10mT.

The present invention has the following advantages:

(1) It has good enhancement characteristics and high threshold voltage.

Since the AlGaN/GaN heterojunction interface in the device structure adopted by the present invention is a non-planar structure, the bottom surface of the groove is a 0001 polar surface, and the side surface of the groove is a non-0001 surface, and the non-0001 surface AlGaN epitaxial along the groove side direction /GaN heterojunction reduces or even eliminates the polarization effect, so that the concentration of two-dimensional electron gas formed at the interface of the heterojunction is very low, or even no two-dimensional electron gas, so only a sufficiently high positive voltage is applied to the gate. Sufficient two-dimensional electron gas is induced in the non-0001-plane heterojunction channel epitaxial in the direction of the groove side, and the applied higher gate voltage can form a higher horizontal drift in the sub-GaN buffer layer on the side of the groove The electric field enables electrons to conduct electricity through the main 2DEG channel layer on both sides of the groove, the two-dimensional electron gas channel on the side of the groove, and the auxiliary 2DEG channel layer on the bottom surface of the groove, realizing the enhanced working mode of the device, and obtain a high threshold voltage.

(2) The threshold voltage has good controllability.

The device of the present invention can use different process conditions to epitaxially GaN sub-buffer layers with different thicknesses in the groove side direction during the realization of the process, and the electric field strength in the buffer layer caused by different GaN sub-buffer layer thicknesses The difference of the difference determines the threshold voltage of the device to a large extent, so the threshold voltage of the device can be adjusted by changing the thickness of the GaN sub-buffer layer in the design, such as increasing the thickness of the GaN sub-buffer layer, so that under the same gate voltage, The electric field strength in the GaN subbuffer layer is reduced, thereby increasing the device threshold voltage.

(3) Has a high current density.

Since the AlGaN barrier layer on the inner wall of the groove of the device of the present invention and the AlGaN barrier layer outside the groove are not grown at the same time, the AlGaN barrier layer outside the groove is doped with N-type or even N+ type, which can not only greatly reduce the ohmic resistance of the device Contact resistance, and can greatly reduce the series resistance of the source and drain, thus increasing the current density of the device.

(4) It has good pinch-off characteristics.

Because the GaN sub-buffer layer on the side of the groove can block the flow of electrons in the channel when the gate voltage is zero, the device of the present invention can realize extremely low off-state current.

(5) The process is simple and mature, the repeatability is good, and the reliability of the device is high.

The process steps in the device manufacturing method of the present invention are relatively mature at home and abroad, and the process flow is relatively simple, low in cost, and fully compatible with the mature depletion-type AlGaN/GaN HEMT device manufacturing process. In addition, the present invention adopts a dry etching method for groove gate etching, and in the subsequent high-temperature secondary growth, the surface damage caused by etching can be repaired to a certain extent, so as to reduce the impact of etching damage on device performance. and reliability effects. Compared with the currently commonly used groove gate etching method at home and abroad, the invention can more effectively avoid material damage caused by etching, and the reliability of the device is higher.

Description of drawings

Fig. 1 is the structural diagram of MS gate AlGaN/GaN enhanced HEMT device of the present invention;

Fig. 2 is a flow chart of the process for preparing MS gate enhanced HEMT devices according to the present invention.

Detailed ways

Referring to Fig. 1, the MS gate GaN-based enhanced high electron mobility transistor of the present invention includes: a substrate 1, a transition layer 2, a GaN main buffer layer 3, an N-type AlGaN main barrier layer 4, a groove 5, and a GaN secondary Buffer layer 6, Al _x Ga _1-x N sub-barrier layer 7, dielectric 8, source 9, drain 10 and gate electrode 13; transition layer 2 is located above substrate 1; GaN main buffer layer 3 is located in transition layer 2, the GaN main buffer layer 3 has a thickness of 1um to 4um; the two sides above the GaN main buffer layer 3 are N-type AlGaN main barrier layers 4, and the N-type _{AlxGa1 -xN} main barrier layer The thickness of 4 is 16nm-36nm, and 0.2≤x≤0.3, and the doping concentration is 5×10 ¹⁹ cm ^-3 ; the two sides of the top of the N-type Al _x Ga _1-x N main barrier layer 4 are the source 9 and the The drain 10, the source 9 and the drain 10 are made of Ti, Al, Ni, and Au four-layer metal, and the thicknesses of Ti, Al, Ni, and Au are 30nm, 180nm, 40nm, and 60nm respectively; the groove 5 is etched In the middle of the GaN main buffer layer 3, the depth of the groove is 40nm-150nm, and the bottom surface of the etched groove is the GaN main buffer layer 3, which is a 0001 polar plane, and the side of the groove is a non-0001 plane; the GaN sub-buffer layer 6 is located on the groove 5; the Al _x Ga _1-x N sub-barrier layer 7 is located above the GaN sub-buffer layer 6, and 0.2≤x≤0.3; the thickness of the GaN sub-buffer layer 6 is different in different directions, that is, in the concave The groove 5 has a thickness of 20 nm to 110 nm in the upward direction of the bottom surface, and a thickness of 10 nm to 55 nm in the horizontal direction of the side wall of the groove 5; the thickness of the _{AlxGa1 -xN} sub-barrier layer 7 is also different in different directions, That is, the thickness in the upward direction of the bottom of the groove 5 is 16 nm to 36 nm, and the thickness in the horizontal direction of the side wall of the groove 5 is 8 nm to 18 nm; the gate electrode 13 is deposited on the AlGaN sub-barrier layer 7 and covers the entire concave In the region of the groove 5, the gate electrode 13 uses two layers of metal, Ni and Au, and the thicknesses of Ni and Au are 30nm and 200nm respectively; the medium 8 is distributed on the source of the N-type AlGaN main barrier layer 4 on both sides of the groove 5 , Except for the drain electrode, its thickness is 10nm-60nm. The main two-dimensional electron gas 2DEG channel 11 is formed at the interface between the GaN main buffer layer 3 and the _{AlxGa1 -xN} main barrier layer 4, and the channel 11 is located on both sides of the groove 5; the GaN epitaxial inside the groove The interface between the sub-buffer layer 6 and the Al _x Ga _1-x N sub-barrier layer 7 forms an auxiliary two-dimensional electron gas 2DEG channel 12, and the horizontal position of the auxiliary two-dimensional electron gas 2DEG channel 12 is lower than the main two-dimensional electron gas 2DEG The horizontal position of channel 11.

Referring to FIG. 2 , the method for manufacturing MS-gate GaN-based enhancement-type high electron mobility transistors according to the present invention provides the following three embodiments.

Example 1

The transition layer is made of AlN, the thickness of the GaN main buffer layer is 1um, the thickness of the Al _0.3 Ga _0.7 N main barrier layer is 16nm, the groove etching depth is 40nm, and the thickness of the GaN secondary buffer layer is 20nm in the upward direction of the bottom of the groove. The thickness in the horizontal direction of the side of the groove is 10nm, the thickness of the Al _0.3 Ga _0.7 N sub-barrier layer is 16nm in the upward direction of the bottom of the groove, the thickness in the horizontal direction of the side of the groove is 8nm, and the thickness of the dielectric layer is 10nm. Gate GaN-based enhancement-mode high electron mobility transistor, the steps of which are:

Step 1: Place the C-plane sapphire substrate in the reaction chamber of the MOCVD equipment, evacuate the vacuum of the reaction chamber to below 1×10 ^-2 Torr, and process the sapphire substrate under the protection of the mixed gas of hydrogen and ammonia. For heat treatment and surface nitriding, the heating temperature is 1050° C., the pressure is 20 Torr, the flow rate of hydrogen gas is 1500 sccm, and the flow rate of ammonia gas is 1500 sccm.

Step 2: Using MOCVD technology at a temperature of 980°C, a pressure of 20 Torr, a flow rate of hydrogen gas of 300 sccm, a flow rate of ammonia gas of 1500 sccm, and a flow rate of aluminum source of 30 sccm, the epitaxy of an AlN transition layer with a thickness of 150 nm is carried out on the sapphire substrate Growth, as shown in Figure 2(a).

Step 3: Use MOCVD technology to epitaxially grow a GaN main buffer with a thickness of 1um on the transition layer under the process conditions of temperature 920°C, pressure 40Torr, hydrogen gas flow rate 500 sccm, ammonia gas flow rate 5000 sccm, and gallium source flow rate 220 sccm layer, as shown in Figure 2(b).

Step 4, using MOCVD technology under the process conditions of temperature 920°C, pressure 40 Torr, hydrogen gas flow rate 500 sccm, ammonia gas flow rate 5000 sccm, aluminum source flow rate 10 sccm, gallium source flow rate 40 sccm, on the main buffer layer, through The N-type doped Al _0.3 Ga _0.7 N main barrier layer with a doping concentration of 5×10 ¹⁹ cm ^-3 and a thickness of 16 nm is epitaxially grown through silane SiH ₄ to form an AlGaN/GaN heterojunction on the AlN transition layer , the main two-dimensional electron gas 2DEG is formed at the AlGaN/GaN heterojunction interface close to the GaN side, and the epitaxial wafer structure formed by epitaxial AlGaN/GaN heterojunction on the AlN transition layer is shown in Figure 2(c).

Step 5, after cleaning the above-mentioned epitaxial wafer, a layer of SiN mask dielectric layer is deposited on the surface of the epitaxial wafer by using plasma enhanced chemical vapor deposition PECVD technology, as shown in Fig. 2(d).

Step 6: On the surface of the epitaxial wafer on which the mask dielectric layer is deposited, firstly carry out positive resist and soft baking; then form the groove window required for etching through exposure and development, and finally use wet etching method to etch away SiN mask dielectric layer under the groove window, and remove residual photoresist on the SiN mask dielectric layer with acetone.

Step 7: Photoetch a groove window on the epitaxial wafer after deglue removal, and use reactive ion etching RIE equipment to etch the AlGaN/GaN heterojunction under the groove window. The etching uses chlorine gas Cl ₂ with a flow rate of 15 sccm, The power is 200W, the pressure is 10mT, and the etching depth is 40nm to form a groove structure with the bottom surface of the groove being a 0001 polar surface and the side surface being a non-0001 surface, as shown in Figure 2(e).

Step eight, remove the etched positive resist with acetone, and clean the surface of the epitaxial wafer.

Step 9: Evacuate the vacuum of the reaction chamber to below 1×10 ^-2 Torr, and heat-treat the cleaned epitaxial wafer under the protection of the mixed gas of hydrogen and ammonia. The heating temperature is 1000°C, the pressure is 20 Torr, and the hydrogen gas The flow rate is 1500 sccm, and the flow rate of ammonia gas is 1500 sccm.

Step 10, repeat step 3, and grow GaN sub-buffer layers of different thicknesses on the inner wall of the groove for the second time, that is, the thickness of the GaN sub-buffer layer grown vertically on the bottom of the groove is 20nm, and the GaN sub-buffer layer grown horizontally on the side of the groove The thickness of the secondary buffer layer is 10nm, as shown in Figure 2(f).

Step 11, using MOCVD technology at a temperature of 920°C, a pressure of 40 Torr, a hydrogen flow rate of 500 sccm, an ammonia gas flow rate of 5000 sccm, an aluminum source flow rate of 10 sccm, and a gallium source flow rate of 40 sccm, on the GaN sub-buffer layer Secondary growth of Al _0.3 Ga _0.7 N sub-barrier layers with different thicknesses, that is, Al _0.3 Ga _0.7 N sub-barrier layers grown vertically on the bottom of the groove with a thickness of 16nm, and Al _{0.3 N} sub-barrier layers grown horizontally on the groove side The thickness of the Ga _0.7 N sub-barrier layer is 8nm, so that an auxiliary two-dimensional electron gas 2DEG is formed at the interface of the sub-AlGaN barrier layer and the sub-GaN buffer layer on the GaN side, and the auxiliary two-dimensional electron gas 2DEG is guaranteed. The horizontal position is lower than that of the main two-dimensional electron gas 2DEG, as shown in Fig. 2(g).

Step 12: On the epitaxial wafer after secondary growth of the Al _0.3 Ga _0.7 N sub-barrier layer, the flow rate of ammonia gas is 2.5 sccm, the flow rate of nitrogen gas is 900 sccm, the flow rate of silane gas is 200 sccm, the temperature is 300°C, the pressure is 900mT, and the power Under the process condition of 25W, a SiN dielectric layer with a thickness of 10nm was deposited by the plasma enhanced chemical vapor deposition PECVD method, and the dielectric layer covered the sub-barrier layer and the inner wall of the groove, as shown in Figure 2(h).

Step 13, photolithography and removal of the SiN dielectric layer under the source, drain and gate regions:

First, spin the positive glue on the SiN dielectric layer at a speed of 5000 rpm, and bake it in a high-temperature oven at a temperature of 80°C for 10 minutes;

Next, forming source, drain and gate regions by exposure and development;

Finally, wet etching is used to remove the SiN dielectric film under the source, drain and gate regions.

Step 14, the epitaxial wafer with the SiN dielectric layer removed from the source, drain, and gate regions is shaken at a speed of 5000 rpm, and baked in a high-temperature oven at a temperature of 80°C for 10 minutes, and finally the source is obtained through exposure and development. , Leaky window.

Step fifteen, using a plasma stripper to remove the undeveloped photoresist thin layer in the window area, so as to improve the yield of metal stripping.

Step 16: Deposit four layers of Ti, Al, Ni and Au ohmic contact metals using an electron beam evaporation instrument under the conditions of a vacuum degree of less than 2.0×10 ^-6 Pa, a power of 200 W, and an evaporation rate of no more than 3 angstroms/second , and the thickness of Ti is 30nm, the thickness of Al is 180nm, the thickness of Ni is 40nm, and the thickness of Au is 60nm.

Step seventeen, soak the evaporated epitaxial wafer in acetone solution for 20 minutes, then perform ultrasonic cleaning, rinse with ultrapure water and blow dry with nitrogen, so as to peel off the metal outside the source and drain windows.

Step 18: Perform ohmic contact annealing on the epitaxial wafer after metal stripping in a nitrogen atmosphere at a temperature of 850° C. for 30 seconds to form source and drain contact electrodes, as shown in FIG. 2( i ).

In step nineteen, on the epitaxial wafer on which the source and drain contact electrodes have been formed, the resist is cast, soft baked, and a gate window is obtained through exposure and development.

Step 20: Deposit Ni/Au two-layer metal on the epitaxial wafer with the gate window by photolithography, the thickness of Ni is 30nm, and the thickness of Au is 200nm; Peel off, rinse with ultrapure water for 2 minutes, and blow dry with nitrogen to finally obtain the gate electrode, as shown in Figure 2(j).

Step 21: Photolithography has formed the epitaxial wafer with source, drain, and gate structures to obtain thickened electrode patterns, and electron beam evaporation technology is used to thicken the electrodes to complete the fabrication of the device as shown in Figure 1.

Example 2

The transition layer is made of AlN, the thickness of the GaN main buffer layer is 2.5um, the thickness of the Al _0.25 Ga _0.75 N main barrier layer is 26nm, the groove etching depth is 90nm, and the thickness of the GaN sub-buffer layer is 60nm in the upward direction of the bottom of the groove 1. The thickness in the horizontal direction of the side of the groove is 30nm, the thickness of the Al _0.25 Ga _0.75 N sub-barrier layer is 26nm in the upward direction of the bottom of the groove, the thickness in the horizontal direction of the side of the groove is 13nm, and the thickness of the dielectric layer is 40nm MS gate GaN-based enhancement-mode high electron mobility transistor, the steps of which are:

Step 1 is the same as Step 1 of Embodiment 1.

Step 2 is the same as Step 2 of Example 1.

Step 3, using MOCVD technology under the process conditions of temperature 920°C, pressure 40Torr, hydrogen gas flow rate 500 sccm, ammonia gas flow rate 5000 sccm, gallium source flow rate 220 sccm, epitaxially grow a GaN main body with a thickness of 2.5um on the transition layer Buffer layer, as shown in Figure 2(b).

Step 4, using MOCVD technology at a temperature of 920°C, a pressure of 40 Torr, a hydrogen flow of 500 sccm, an ammonia flow of 5000 sccm, an aluminum source flow of 10 sccm, and a gallium source flow of 40 sccm, on the main buffer layer, through The N-type doped Al _0.25 Ga _0.75 N main barrier layer with a doping concentration of 5×10 ¹⁹ cm ^-3 and a thickness of 26 nm is epitaxially grown through silane SiH ₄ to form an AlGaN/GaN heterojunction on the AlN transition layer , the main two-dimensional electron gas 2DEG is formed at the AlGaN/GaN heterojunction interface close to the GaN side, and the epitaxial wafer structure formed by epitaxial AlGaN/GaN heterojunction on the AlN transition layer is shown in Figure 2(c).

Step 5 is the same as Step 5 of Embodiment 1.

Step 6 is the same as Step 6 of Embodiment 1.

Step 7, photoetch the groove window on the epitaxial wafer after deglue, and use reactive ion etching RIE equipment to etch the AlGaN/GaN heterojunction under the groove window, and use chlorine gas Cl ₂ with a flow rate of 15 sccm for etching, The power is 200W, the pressure is 10mT, and the etching depth is 90nm to form a groove structure with a 0001 polar surface on the bottom surface and a non-0001 surface on the side surface, as shown in Figure 2(e).

Step 8 is the same as Step 8 of Embodiment 1.

Step 9 is the same as Step 9 in Embodiment 1.

Step 10, repeat step 3, and grow GaN sub-buffer layers with different thicknesses on the inner wall of the groove for the second time, that is, the thickness of the GaN sub-buffer layer grown vertically on the bottom of the groove is 60nm, and the GaN sub-buffer layer grown horizontally on the side of the groove The thickness of the secondary buffer layer is 30nm, as shown in Figure 2(f).

Step 11, using MOCVD technology under the process conditions of temperature 920°C, pressure 40 Torr, hydrogen gas flow rate 500 sccm, ammonia gas flow rate 5000 sccm, aluminum source flow rate 10 sccm, gallium source flow rate 40 sccm, on the GaN sub-buffer layer two Sub-growth Al _0.25 Ga _0.75 N sub-barrier layers with different thicknesses, that is, the thickness of the Al _0.25 Ga _0.75 N sub-barrier layer grown in the vertical direction on the bottom of the groove is 26nm, and the thickness of the Al _0.25 Ga 0.75 N sub-barrier layer grown in the horizontal direction on the groove side The thickness of the _0.75 N sub-barrier layer is 13nm, so that an auxiliary two-dimensional electron gas 2DEG is formed at the interface of the sub-AlGaN barrier layer and the sub-GaN buffer layer on the GaN side, and the level of the auxiliary two-dimensional electron gas 2DEG is guaranteed The position is lower than the horizontal position of the main two-dimensional electron gas 2DEG, as shown in Figure 2(g).

Step 12, on the epitaxial wafer after secondary growth of the Al _0.25 Ga _0.75 N sub-barrier layer, the flow rate of ammonia gas is 2.5 sccm, the flow rate of nitrogen gas is 900 sccm, the flow rate of silane gas is 200 sccm, the temperature is 300°C, the pressure is 900mT, and the power is Under the process condition of 25W, a SiN dielectric layer with a thickness of 40nm was deposited by plasma-enhanced chemical vapor deposition PECVD method, and the dielectric layer covered the sub-barrier layer and the inner wall of the groove, as shown in Figure 2(h).

Step 13 is the same as Step 13 in Embodiment 1.

Step 14 is the same as Step 14 in Embodiment 1.

Step 15 is the same as Step 15 of Embodiment 1.

Step 16 is the same as Step 16 in Embodiment 1.

Step 17 is the same as Step 17 in Embodiment 1.

Step 18 is the same as Step 18 in Embodiment 1.

Step 19 is the same as Step 19 in Embodiment 1.

Step 20 is the same as Step 20 of Embodiment 1.

Step 21 is the same as Step 21 of Embodiment 1.

Example 3

The transition layer is made of AlN, the thickness of the GaN main buffer layer is 4um, the thickness of the Al _0.2 Ga _0.8 N main barrier layer is 36nm, the groove etching depth is 150nm, and the thickness of the GaN secondary buffer layer is 110nm in the upward direction of the bottom of the groove. The thickness in the horizontal direction of the side of the groove is 55nm, the thickness of the Al _0.2 Ga _0.8 N sub-barrier layer is 36nm in the upward direction of the bottom of the groove, the thickness in the horizontal direction of the side of the groove is 18nm, and the thickness of the dielectric layer is 60nm. Gate GaN-based enhancement-mode high electron mobility transistor, the steps of which are:

Step A is the same as step one of embodiment 1.

Step B is the same as Step 2 of Example 1.

Step C, using MOCVD technology to epitaxially grow a GaN main buffer with a thickness of 4um on the transition layer under the process conditions of a temperature of 920°C, a pressure of 40Torr, a flow rate of hydrogen gas of 500 sccm, a flow rate of ammonia gas of 5000 sccm, and a flow rate of gallium source of 220 sccm layer, as shown in Figure 2(b).

Step D, using MOCVD technology at a temperature of 920°C, a pressure of 40 Torr, a hydrogen flow of 500 sccm, an ammonia flow of 5000 sccm, an aluminum source flow of 10 sccm, and a gallium source flow of 40 sccm, on the main buffer layer, through The N-type doped Al _0.2 Ga _0.8 N main barrier layer with a doping concentration of 5×10 ¹⁹ cm ^-3 and a thickness of 36nm is epitaxially grown through silane SiH ₄ to form an AlGaN/GaN heterojunction on the AlN transition layer , the main two-dimensional electron gas 2DEG is formed at the AlGaN/GaN heterojunction interface close to the GaN side, and the epitaxial wafer structure formed by epitaxial AlGaN/GaN heterojunction on the AlN transition layer is shown in Figure 2(c).

Step E is the same as Step 5 of Example 1.

Step F is the same as Step 6 of Embodiment 1.

Step G, photoetching a groove window on the epitaxial wafer after degelling, and using reactive ion etching RIE equipment to etch the AlGaN/GaN heterojunction under the groove window, using chlorine gas Cl ₂ with a flow rate of 15 sccm for etching, The power is 200W, the pressure is 10mT, and the etching depth is 150nm to form a groove structure with a 0001 polar surface on the bottom surface and a non-0001 surface on the side surface, as shown in Figure 2(e).

Step H is the same as Step 8 of Example 1.

Step 1 is the same as Step 9 of Embodiment 1.

Step J, repeat step 3, and grow GaN sub-buffer layers with different thicknesses on the inner wall of the groove for the second time, that is, the thickness of the GaN sub-buffer layer grown vertically on the bottom of the groove is 110 nm, and the GaN sub-buffer layer grown horizontally on the side of the groove The thickness of the secondary buffer layer is 55nm, as shown in Figure 2(f).

In step K, using MOCVD technology at a temperature of 920° C., a pressure of 40 Torr, a hydrogen gas flow rate of 500 sccm, an ammonia gas flow rate of 5000 sccm, an aluminum source flow rate of 10 sccm, and a gallium source flow rate of 40 sccm, on the GaN sub-buffer layer two Sub-growth Al _0.2 Ga _0.8 N sub-barrier layers with different thicknesses, that is, the thickness of the Al _0.2 Ga _0.8 N sub-barrier layer grown in the vertical direction on the bottom of the groove is 36nm, and the Al _0.2 Ga 0.8 N sub-barrier layer grown in the horizontal direction on the groove side The thickness of the _0.8 N sub-barrier layer is 18nm, so that an auxiliary two-dimensional electron gas 2DEG is formed at the interface of the sub-AlGaN barrier layer and the sub-GaN buffer layer on the GaN side, and the level of the auxiliary two-dimensional electron gas 2DEG is guaranteed The position is lower than the horizontal position of the main two-dimensional electron gas 2DEG, as shown in Figure 2(g).

In step L, on the epitaxial wafer after secondary growth of the Al _0.2 Ga _0.8 N sub-barrier layer, the flow rate of ammonia gas is 2.5 sccm, the flow rate of nitrogen gas is 900 sccm, the flow rate of silane gas is 200 sccm, the temperature is 300°C, the pressure is 900mT, and the power is Under the process condition of 25W, a SiN dielectric layer with a thickness of 60nm was deposited by plasma-enhanced chemical vapor deposition PECVD method, and the dielectric layer covered the sub-barrier layer and the inner wall of the groove, as shown in Figure 2(h).

Step M is the same as Step 13 of Embodiment 1.

Step N is the same as Step 14 of Embodiment 1.

Step 0 is the same as Step 15 of Embodiment 1.

Step P is the same as Step 16 of Embodiment 1.

Step Q is the same as Step 17 of Embodiment 1.

Step R is the same as Step 18 of Embodiment 1.

Step S is the same as Step 19 of Embodiment 1.

Step T is the same as Step 20 of Embodiment 1.

Step U is the same as Step 21 of Embodiment 1.

The above-described embodiments are only several preferred examples of the present invention, and do not constitute any limitation to the present invention. Obviously, for those skilled in the art, after understanding the contents and principles of the present invention, they can Under the circumstances of the invention, various amendments and changes in form and details are made according to the method of the present invention, but these amendments and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims (8)

1. a metal semiconductor MS grid GaN base enhancement type high electron mobility transistor comprises: substrate (1), transition zone (2), GaN host buffer layer (3), N type AlGaN master barrier layer (4), source electrode (9) and drain electrode (10); Transition zone (2) is positioned at substrate (1) top; GaN host buffer layer (3) is positioned at transition zone (2) top; Both sides, GaN host buffer layer (3) top are N type AlGaN master barrier layer (4); N type AlGaN master barrier layer (4) both sides, top are respectively source electrode (9) and drain electrode (10); It is characterized in that the centre of GaN host buffer layer (3) is etched with groove (5), the inwall of this groove (5) extension successively has GaN resilient coating (6) and AlGaN barrier layer (7); Gate electrode is deposited on AlGaN the barrier layer (7), and covers whole groove (5) zone; Be provided with medium (8) outside the source of N type AlGaN master barrier layer (4) top of groove (5) both sides, the drain electrode.

2. HEMT according to claim 1, the bottom surface of groove (5) is 0001 polar surface, the groove side is non-0001.

3. HEMT according to claim 1 is characterized in that, the main two-dimensional electron gas 2DEG of the formation at the interface raceway groove (11) of GaN host buffer layer (3) and AlGaN master's barrier layer (4), and this raceway groove (11) is positioned at the both sides of groove (5); GaN the resilient coating (6) of extension forms auxilliary two-dimensional electron gas 2DEG raceway groove (12) with AlGaN barrier layer (7) interface in the groove.

4. HEMT according to claim 1 is characterized in that, the horizontal level of auxilliary two-dimensional electron gas 2DEG raceway groove (12) is lower than the horizontal level of main two-dimensional electron gas 2DEG raceway groove (11).

5. HEMT according to claim 1 is characterized in that, AlGaN master's barrier layer (4) is 5 * 10 for doping content ¹⁹Cm ^-3The N type mix.

6. the manufacture method of metal semiconductor MS grid GaN base enhancement type high electron mobility transistor may further comprise the steps:

1) in metal organic chemical vapor deposition MOCVD reative cell, substrate surface is carried out preliminary treatment;

2) epitaxial growth AlGaN/GaN epitaxial loayer on substrate, wherein GaN thickness is 1um～4um, the Al that the N type mixes _xGa _1-xThe N barrier layer thickness is 16nm～36nm, and wherein the molar content x of Al element is 20%-30%;

3) deposit one deck mask dielectric layer on epitaxial loayer carries out photoetching again, and adopts wet etching method that the dielectric layer on the epitaxial loayer is carried out etching, and shape is grown into the groove of 0.5um on epitaxial loayer;

4) make grooved area by lithography, and adopt reactive ion etching RIE method that the AlGaN/GaN epitaxial loayer in the grooved area is carried out etching, etching depth is 40nm～150nm;

5) the mask dielectric layer outside the reservation groove; Epitaxial loayer after the etching is passed through metal organic chemical vapor deposition MOCVD reative cell; Along the 20nm～110nm that grows on the groove floor direction vertically upward thick GaN layer and the thick AlGaN layer of 16nm～36nm, along thick GaN layer and the thick AlGaN layer of 8nm～18nm of groove side surface direction growth 10nm～55nm;

6) remove the mask dielectric layer;

7) on the epitaxial loayer of removing the mask dielectric layer, adopting chemical vapor deposition CVD or physical vapor deposition PVD method deposition thickness is the dielectric layer of 10nm～60nm;

8) on dielectric layer, make source, leakage, gate region earlier by lithography, etch source, leakage, grid window again;

9) make source, drain region by lithography, again on the epitaxial loayer after the photoetching, adopt electron beam evaporation thickness be four layers of metal of Ti/Al/Ni/Au of 30nm/180nm/40nm/60nm as metal ohmic contact, formation source, drain contact electrode after peeling off, annealing;

10) make gate region by lithography, and on the epitaxial loayer after the photoetching, adopt electron beam evaporation thickness be the Ni/Au double layer of metal of 30nm/200nm as gate metal, the grid of formation metal semiconductor MS through peeling off after;

11) photoetching has formed the device surface of source, leakage, grid, obtains the thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, accomplishes element manufacturing.

7. HEMT according to claim 6 is characterized in that, the process conditions of step 9) and step 10) electron beam evaporation are: vacuum degree is less than 2.0 * 10 ^-6Pa, power are 200W, and evaporation rate is smaller or equal to dust/second.

8. HEMT according to claim 6 is characterized in that, the process conditions of step 4) etching AlGaN/GaN epitaxial loayer are: chlorine Cl ₂Flow is 15sccm's, and power is 200W, and pressure is 10mT.

Images