CN104701262B - A kind of forming method of semiconductor devices - Google Patents

Abstract

The invention provides a method for forming a semiconductor device. After the gate dielectric layer is formed on the semiconductor substrate, the first material layer, the barrier layer and the second material layer are sequentially formed on the gate dielectric layer from bottom to top, and the second material layer, the barrier layer, the first material layer and the second material layer are etched. The gate dielectric layer forms a dummy gate stack. In the above technical solution, the formed dummy gate includes three layers on the gate dielectric layer as the dummy gate material structure. During the process of removing the dummy gate structure of the above three layers of materials, the barrier layer can be used as an etch by dry etching Efficiently remove the etching end point of the second material layer, and after removing the barrier layer, the remaining first material layer is removed by a wet etching process with a higher etching ratio for the first material layer and the gate dielectric layer, thereby While ensuring that all the materials of the three-layer dummy gate are removed, the gate dielectric layer under the three-layer dummy gate structure is prevented from being damaged.

Description

A method of forming a semiconductor device

technical field

The invention relates to the field of semiconductor preparation, in particular to a method for forming a semiconductor device.

Background technique

With the development of integrated circuit manufacturing technology, the integration degree of integrated circuits is increasing, and the feature size of integrated circuits is also decreasing, and the quality requirements for electrical components in integrated circuits are becoming more and more stringent. For this reason, the manufacturing process of integrated circuits is constantly being innovated to improve the quality of the manufactured integrated circuit electrical components.

For example, in the CMOS manufacturing process, the gate last process has gradually replaced the gate first process to improve the quality of the gate. The so-called gate-front process means that after the gate opening is formed in the dielectric layer of the semiconductor substrate, the gate material is directly filled in the gate opening to form the gate, and then the source and drain are implanted and annealing process is performed to activate the source and drain. The ions in it form the source and drain regions. However, in the gate-front process, the gate will inevitably be heated at a high temperature during the annealing process, which will cause the threshold voltage Vt of the transistor to drift, thereby affecting the electrical performance of the semiconductor device. In the gate-last process, a dummy gate (such as polysilicon) is first formed in the gate opening of the dielectric layer, and after the source region and drain region are formed, the dummy gate is removed, a gate trench is formed, and the gate material is filled to Form the grid. The gate-last process successfully avoids damage to the gate due to the high temperature introduced during the formation of the source region and the drain region, thereby improving the electrical performance of the formed semiconductor device.

In the dummy gate removal process of the gate-last process, the efficiency of wet etching to remove the dummy gate material in the dummy gate is low, and the etching cost is high; the dummy gate material can be removed efficiently by the dry etching process, but the dry etching process can effectively remove the dummy gate material. The etching selection of the etching is relatively low, and while removing the dummy gate material, it will damage the gate dielectric layer in the dummy gate and below the dummy gate material.

Therefore, some people have tried to remove most of the dummy gate material by dry etching process, and then remove the remaining dummy gate material by wet etching process, using the combination of dry etching and wet etching, In order to improve the removal efficiency of dummy gate material. But even so, in the gate-last process, the phenomenon that the dummy gate material is over-etched and damages the gate dielectric layer under the dummy gate material still occurs.

Therefore, how to improve the etching efficiency of the dummy gate material and avoid damage to the gate dielectric layer under the dummy gate material while completely removing the dummy gate material is an urgent problem to be solved by those skilled in the art.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a semiconductor device, which can effectively prevent the gate dielectric layer under the dummy gate material from being damaged while improving the removal efficiency of the dummy gate material.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising:

providing a semiconductor substrate on which a gate dielectric layer is formed;

forming a first material layer over the gate dielectric layer;

forming a barrier layer over the first material layer;

forming a second material layer over the barrier layer;

sequentially etching the second material layer, the barrier layer, the first material layer and the gate dielectric layer to form a dummy gate stack;

etching the second material layer to expose the barrier layer;

removing the barrier layer;

removing the first material layer by using a wet etching process to form a gate opening;

The gate opening is filled with metal material to form a gate.

Optionally, the barrier layer material is silicon nitride, silicon oxynitride or silicon oxycarbide.

Optionally,

The thickness ratio of the barrier layer to the second material layer is: 1:8 to 2:65;

The thickness ratio of the barrier layer to the first material layer is 1:5 to 1:1.

Optionally, the thickness of the first material layer is to The thickness of the barrier layer is to

Optionally, the first material layer and the second material layer are polysilicon layers.

Optionally, the etchant used in the wet etching process for removing the first material layer is TMAH.

Optionally, the conditions of the wet etching process are as follows: the volume percentage concentration of TMAH is 2%-20%, the temperature is 30°C-60°C, and the time is 100s-300s.

Optionally, the method for removing the second material layer is dry etching, and the method for removing the barrier layer is dry etching or wet etching.

Optionally, the etchant used to remove the barrier layer by wet etching is DHF.

Optionally, the volume percentage concentration of the DHF is 0.2%-0.1%.

Optionally, the process of removing the barrier layer by dry etching includes: controlling the pressure of the reaction chamber to be 3-10mtoor, the bias voltage to be 100-250V, the radio frequency power to be 100-400W, and the temperature to be 45-60°C, The etching gas used is plasma containing CF ₄ , O ₂ and Ar.

Optionally, the etchant used to remove the second material layer by dry etching is a mixed gas containing HBr, O ₂ and Cl ₂ .

Compared with the prior art, the technical solution of the present invention has the following advantages:

After the gate dielectric layer is formed on the semiconductor substrate, a first material layer, a barrier layer and a second material layer are sequentially formed on the gate dielectric layer from bottom to top, and the second material layer and the barrier layer are etched. , the first material layer and the gate dielectric layer form a dummy gate stack. Through the above technical solution, the formed dummy gate includes three layers on the gate dielectric layer as dummy gate material structures: a first material layer, a barrier layer and a second material layer. In the process of removing the above three dummy gate material layers, the barrier layer can be used as an etching end point for efficiently removing the second material layer, and after removing the barrier layer, the remaining first material layer can be used For the removal of the first material layer and the gate dielectric layer by a wet etching process with a relatively high etching ratio, while ensuring that the three-layer dummy gate material is completely removed, the gate dielectric under the three-layer dummy gate structure is avoided layer is damaged. The above technical solution efficiently removes three dummy gate material layers while effectively avoiding damage to the gate dielectric layer under the dummy gate, thereby ensuring the quality of the subsequently formed gate.

Description of drawings

1 to 7 are schematic structural views of a method for forming a semiconductor device according to an embodiment of the present invention.

detailed description

As mentioned in the background, in the gate-last process, during the process of removing the dummy gate, the defect that the dummy gate is over-etched and damages the gate dielectric layer under the dummy gate often occurs. This affects the process of semiconductor preparation and the quality of the gate finally formed.

After analysis, the reason for the above defects is that in the semiconductor manufacturing process, multiple gates will be formed on the same wafer at the same time, and the arrangement density of these gates is different, including dense regions and sparse regions. During the process, in the dummy gate etching stage of the gate-last process, based on the different density of each dummy gate, there are differences in the removal amount of the dummy gate material. For the dummy gate material removal process in different dummy gates, wet etching and dry etching at the same time will inevitably result in insufficient etching of some dummy gate materials, resulting in residual dummy gate material, and excessive etching of some dummy gate materials , thereby causing damage to the gate dielectric layer under the dummy gate material.

In view of the above defects, the present invention provides a method for forming a semiconductor device. While ensuring the dummy gate material removal efficiency and saving the dummy gate material removal cost, the gate dielectric layer under the dummy gate material is effectively prevented from being damaged.

In order to make the above objects, features and advantages of the present invention more obvious and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, taking the etching process in the gate formation method as an example.

1 to 7 are structural schematic diagrams of an embodiment of a method for forming a semiconductor device provided by the present invention.

Referring first to FIG. 1, a semiconductor substrate 10 is provided, a gate dielectric layer 11 is formed on the semiconductor substrate 10, a first material layer 12 is formed on the gate dielectric layer 11; A barrier layer 13 is formed on the barrier layer 13; a second material layer 14 is formed on the barrier layer 13.

In this embodiment, the semiconductor substrate 10 may be single crystal silicon, polycrystalline silicon or amorphous silicon, or silicon, germanium, gallium arsenide or silicon germanium compound. The semiconductor substrate 10 may have a structure such as an epitaxial layer or a silicon-on-insulator layer. All existing semiconductor substrates can be used as the semiconductor substrate of this embodiment, and will not be listed here.

In this embodiment, the gate dielectric layer 11 is an oxide layer. The formation process of the gate dielectric layer 11 may be a thermal oxidation process.

The first material layer 12 and the second material layer 14 may be polysilicon layers. The formation process of the first material layer 12 and the second material layer 14 is CVD (Chemical Vapor Deposition).

In this embodiment, the material of the barrier layer 13 may be silicon nitride, silicon oxynitride or silicon carbide nitride. The formation process of the barrier layer 13 may be CVD.

In this embodiment, further optionally, the thickness ratio of the barrier layer 13 to the second material layer 14 is 1:8 to 2:65; the thickness ratio of the barrier layer 13 to the first material layer 12 is 1: 5 to 1:1.

In this embodiment, the thickness of the first material layer 12 is to The thickness of the barrier layer 13 is to

Referring to FIG. 2 , the second material layer 14 , barrier layer 13 , first material layer 12 and gate dielectric layer 11 are sequentially etched to form a dummy gate stack.

On the semiconductor substrate 10, a plurality of dummy gate stacks can be formed at the same time. For the convenience of description, in this embodiment, two dummy gate stacks are formed on the semiconductor substrate 10, the first dummy gate stack 100 and the second dummy gate stack 100. Two dummy gate stacks 200 .

The first dummy gate stack 100 includes a gate dielectric layer 111 , a first material layer 112 , a barrier layer 113 and a second material layer 114 in order from bottom to top. The second dummy gate stack 200 includes a gate dielectric layer 211 , a first material layer 212 , a barrier layer 213 and a second material layer 214 in order from bottom to top.

Referring to FIG. 3 , spacer structures (not labeled in the figure) are formed around the first dummy gate stack 100 and the second dummy gate stack 200 .

The forming process of the spacer structure may include first forming a sidewall material layer on the first dummy gate stack 100 and the second dummy gate stack 200 and on the semiconductor substrate 10 by CVD, and then etching The process removes the sidewall material layer above the first dummy gate stack 100 and the second dummy gate stack 200 to expose the second material layers 214 and 114 , thereby forming the sidewall structure as shown in FIG. 3 .

The side wall structure can also be a multi-layer structure, and the existing side wall structure and the method for forming the side wall structure can all be applied in this embodiment, and will not be repeated here.

Afterwards, a dielectric layer 300 is formed on the semiconductor substrate 10, the spacer structure, and the first dummy gate stack 100 and the second dummy gate stack 200, and the first dummy gate stack 100 and the second dummy gate stack 100 and the second dummy gate stack are removed by CMP or other processes. The dielectric layers 300 on the upper part of the stack 200 are stacked so that the upper surface of the dielectric layer 300 is flush with the upper surfaces of the second material layers 214 and 114 and the second material layers 214 and 114 are exposed.

Referring to FIG. 4, the second material layer 114 in the first dummy gate stack 100 and the second material layer 214 in the second dummy gate stack 200 are removed by a dry etching process until the barrier layer 113 is exposed. and 213.

Specifically, in this embodiment, the etching process specifically includes: using a mixed gas containing HBr, O ₂ and Cl ₂ as the etching gas to remove the second material located on the barrier layers 113 and 213 Layers 114 and 214.

In this embodiment, the second material layers 114 and 214 are polysilicon, and the barrier layers 113 and 213 are made of silicon nitride, silicon oxynitride or silicon carbide nitride. Using a mixed gas containing HBr, O ₂ and Cl ₂ as the etching gas has a greater etching selectivity for polysilicon and silicon nitride (silicon oxynitride or silicon carbide nitride). Using etching gas containing HBr, O ₂ and Cl ₂ can quickly remove polysilicon material, but the etching rate for silicon nitride (silicon oxynitride or silicon carbide nitride) is very small. Therefore, the barrier layers 213 and 113 can serve as the etching endpoints of the second material layers 214 and 114 .

Even if, as in this embodiment, the structures of the second material layers 214 and 114 in the first dummy gate stack 100 and the second dummy gate stack 200 are slightly deviated, and the etching rate is different, the etching removal When the second material layers 214 and 114 are used, the barrier layers 213 and 113 and structures below the barrier layers 213 and 113 will not be damaged.

Afterwards, as shown in FIG. 5 , after removing the second material layers 114 and 214 , the barrier layers 213 and 113 are removed.

In this embodiment, the barrier layers 213 and 113 can be removed by either a dry etching process or a wet etching process.

In this embodiment, if the dry etching process is used to remove, the specific process includes: controlling the pressure of the reaction chamber to be 3-10mtoor, the bias voltage to be 100-250V, the radio frequency power to be 100-400W, and the temperature to be 45-60°C, The barrier layers 213 and 113 are removed by using plasma containing CF ₄ , O ₂ and Ar as the etching gas.

If a wet etching process is used to remove, the specific process includes: using dilute hydrofluoric acid (DHF) as a wet etchant to remove the barrier layers 213 and 113 . The volume concentration of the DHF is 0.2%-0.1%.

In this embodiment, the thickness of the barrier layers 213 and 113 can be selected as to The above-mentioned thickness value immediately ensures that when the second material layers 214 and 114 are dry-etched, the further progress of dry etching is blocked. Moreover, the wet etching process or dry etching process for removing the barrier layers 213 and 113 ensures that the barrier layers 213 and 113 are quickly removed.

In this embodiment, the material of the first material layers 212 and 112 is polysilicon, and the wet etching process and the dry etching process for etching and removing the barrier layers 213 and 113 in this embodiment, for the barrier layers 213 and 113 Layers 213 and 113, and the first material layers 212 and 112 all have a larger selective etching ratio, so the first material layers 212 and 112 below the barrier layers 213 and 113 will not be removed too much, thereby avoiding the The gate dielectric layers 111 and 211 below the first material layers 112 and 212 are damaged.

Referring to FIG. 6 , after the barrier layers 213 and 113 are removed, the first material layers 212 and 112 are removed by wet etching to expose the gate dielectric layers 211 and 111 .

In this embodiment, the material of the first material layers 211 and 111 is polysilicon. The wet etching uses TMAH (tetramethylammonium hydroxide) as a wet etchant.

In this embodiment, the gate dielectric layers 211 and 111 are oxide layers, and TMAH has a high etching selectivity for polysilicon and oxide, so when removing the first material layers 212 and 112, there will be no damage to the gate dielectric layers 211 and 111 . In this embodiment, the specific conditions for removing the first material layers 212 and 112 by wet etching process are as follows: the concentration of TMAH is 2% to 20% by volume, the temperature is 30°C to 60°C, and the time is 100s～300s.

In this embodiment, under the above wet etching process conditions, even if the structures of the first dummy gate stack 100 and the second dummy gate stack 200 are deviated or the wet etching rate is deviated, the It is ensured that the gate dielectric layers 211 and 111 will not be damaged when the first material layers 212 and 112 are completely removed.

In this embodiment, the thickness of the first material layers 112 and 212 is to While ensuring that the junction of the barrier layer and the gate dielectric layer is isolated, so as to ensure that the gate dielectric layer will not be damaged when the barrier layer is etched, the first material layer can be wet-etched, was quickly removed. To ensure the etching efficiency and reduce the process cost.

Referring to FIG. 7 , after removing the first material layers 212 and 112 , a first gate opening 130 and a second gate opening 230 are formed in the dielectric layer 300 . Afterwards, the gate material is filled into the first gate opening 130 and the second gate opening 230, and then the gate material above the dielectric layer 300 is removed by CMP (chemical mechanical polishing). A first gate 140 and a second gate 240 are respectively formed in the gate opening 130 and the second gate opening 230 .

Certainly, before filling the gate material into the first gate opening 130 and the second gate opening 230 , the bottom and sidewalls of the first gate opening 130 and the second gate opening 230 may be formed For the high-K dielectric layer, these simple changes are within the protection scope of the present invention.

In today's semiconductor manufacturing process, it is difficult to obtain a material with high etching selectivity for the second material layer, barrier layer, and gate dielectric layer at the same time, so if only a double-layer dummy gate material including the second material layer and barrier layer is used layer structure, when the barrier layer is etched, it will still cause damage to the gate dielectric layer. In this embodiment, the dummy gate structure includes a second material layer, a barrier layer and three layers of dummy gate material layers of the first material layer, wherein the barrier layer can be used as an etching barrier layer for the second material layer, so that When removing the second material layer, over-etching is avoided, and after removing the barrier layer, the wet etching process with a relatively large etching selectivity for the first material layer and the gate dielectric layer is used to remove the The first material layer, so as to avoid damaging the gate dielectric layer when removing the first material layer.

Compared with the existing technical solution of forming a single dummy gate material layer on the gate dielectric layer, the method for forming a semiconductor device provided in this embodiment improves the removal efficiency of the dummy gate structure while ensuring that the gate dielectric layer is not damaged.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. a kind of forming method of semiconductor devices, it is characterised in that including：

Semiconductor substrate is provided, gate dielectric layer is formed on the semiconductor substrate；

First material layer is formed above the gate dielectric layer；

Barrier layer is formed above the first material layer；

Second material layer is formed above the barrier layer；

The second material layer, barrier layer, first material layer and gate dielectric layer are sequentially etched, pseudo- grid is formed and stacks；

The second material layer is etched, to exposing the barrier layer；

Remove the barrier layer；

The first material layer is removed using wet-etching technology, gate openings are formed；

Full metal material is filled in the gate openings, grid is formed；

Wherein, the etching agent that the wet-etching technology of the removal first material layer is used is TMAH；

The condition of the wet-etching technology is：TMAH concentration of volume percent is 2%~20%, and temperature is 30 DEG C~60 DEG C, the time is 100s~300s.

2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the barrier material is nitridation Silicon, silicon oxynitride or silicon oxide carbide.

3. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that

The thickness ratio of the barrier layer and second material layer is：1:8 to 2：65；

The thickness ratio of the barrier layer and first material layer is：1:5 to 1:1.

4. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the thickness of the first material layer isExtremelyThe thickness on the barrier layer isExtremely

5. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the first material layer and the second material The bed of material is polysilicon layer.

6. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that remove the side of the second material layer Method is dry etching, and the method for removing the barrier layer is dry etching or wet etching.

7. the forming method of semiconductor devices as claimed in claim 6, it is characterised in that the resistance is removed using wet etching The etching agent of barrier is dilute hydrofluoric acid DHF.

8. the forming method of semiconductor devices as claimed in claim 7, it is characterised in that the percent by volume of the DHF is dense Spend for 0.2%~0.1%.

9. the forming method of semiconductor devices as claimed in claim 6, it is characterised in that the resistance is removed using dry etching The technique of barrier includes：The air pressure for controlling reaction chamber is 3~10mtoor, and bias voltage is 100~250V, and radio-frequency power is 100 ~400W, temperature is 45~60 DEG C, and the etching gas used is contain CF₄、O₂With Ar plasma.

10. the forming method of semiconductor devices as claimed in claim 6, it is characterised in that removed using dry etching described The etching agent of second material layer is to contain HBr, O₂And Cl₂Mixed gas.