CN105261587A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device, including: a substrate having a first semiconductor layer; a second semiconductor layer located over the substrate; a third semiconductor layer located over the second semiconductor layer; the isolation structures are positioned on the substrate and on two sides of the third semiconductor layer; a cavity between the end of the second semiconductor layer, the third semiconductor layer and the substrate; an oxide layer and an oxidation barrier layer thereon on the inner surface of the cavity and on the sidewalls of the isolation structure; and the device structure is positioned on the third semiconductor layer, and the source-drain region of the device structure is positioned above the cavity. The device structure of the invention has the advantages of both the bulk silicon device and the SOI device, and has the characteristics of low cost, small electric leakage, low power consumption, high speed, simpler process and high integration level.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to the field of semiconductor devices, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

With the continuous shrinking of device size, the number of devices on a chip per unit area is increasing, which will lead to an increase in dynamic power consumption. At the same time, the continuous shrinking of device size will inevitably lead to an increase in leakage current, which in turn will cause an increase in static power consumption. , and with the high integration of semiconductor devices, the channel length of MOSFET continues to shorten, and a series of effects that can be ignored in the MOSFET long channel model become more and more significant, and even become the dominant factor affecting the performance of the device. This phenomenon is collectively referred to as short channel effect. The short channel effect will deteriorate the electrical performance of the device, such as causing a decrease in the gate threshold voltage, an increase in power consumption, and a decrease in the signal-to-noise ratio.

The SOI substrate is embedded with a silicon dioxide layer under the silicon. Compared with bulk silicon devices, the devices formed on the SOI substrate can significantly reduce leakage current and power consumption, improve the short channel effect, and have obvious performance advantages. However, the cost of the SOI substrate is high, and a larger device area is required to avoid the floating body effect (FloatingBodyEffect), which is difficult to meet the requirements of high integration of the device. In addition, due to the embedded silicon dioxide layer, the heat dissipation performance of the device is affected. influences.

Contents of the invention

The purpose of the present invention is to at least solve one of the above-mentioned technical defects, and provide a semiconductor device and a manufacturing method thereof.

The invention provides a semiconductor device, comprising:

a substrate having a first semiconductor layer;

a second semiconductor layer located on the substrate;

a third semiconductor layer located on the second semiconductor layer;

an isolation structure located on both sides of the third semiconductor layer and on the substrate;

a cavity located between the end of the second semiconductor layer, the third semiconductor layer and the substrate;

an oxide layer and an oxidation barrier layer thereon on the inner surface of the cavity and on the sidewalls of the isolation structure;

The device structure is located on the third semiconductor layer, and its source and drain regions are located on the cavity.

Optionally, the substrate is a bulk silicon substrate, the second semiconductor layer is Ge _x Si _1-x , 0<x<1, and the third semiconductor layer is silicon.

The present invention also provides a method for manufacturing a semiconductor device, comprising the steps of:

providing a substrate having a first semiconductor layer;

forming a patterned second semiconductor layer and a third semiconductor layer stack on the first semiconductor layer, with a first oxidation barrier layer on the stack, and isolation trenches on both sides of the stack;

removing a portion of the second semiconductor layer from an end portion of the second semiconductor layer to form an opening;

sequentially forming an oxide layer and a second oxidation barrier layer on the sidewalls of the isolation trench and the inner surface of the opening;

performing an oxidation process so that the isolation trench is filled with the oxide of the first semiconductor layer to form an isolation structure;

removing the first oxidation barrier layer;

A device structure is formed on the third semiconductor layer, and the source and drain regions of the device structure are formed on the opening.

Optionally, the substrate is a bulk silicon substrate, and the steps of forming the second semiconductor layer and the third semiconductor layer are specifically:

epitaxially growing a second semiconductor layer of Ge _x Si _1-x on the substrate, 0<x<1;

epitaxially growing a third semiconductor layer of silicon on the second semiconductor layer;

forming a first oxidation barrier layer on the third semiconductor layer, where the first oxidation barrier layer is a mask layer;

Patterning is performed to form a stack of the second semiconductor layer and the third semiconductor layer, with isolation trenches on both sides of the stack.

Optionally, the step of removing part of the second semiconductor layer from the end of the second semiconductor layer to form the opening specifically includes:

Wet etching is used to selectively remove the second semiconductor layer to form an opening at the end of the second semiconductor layer.

Optionally, the wet etching etchant is a mixed solution of HF, H ₂ O ₂ , CH ₃ COOH and H ₂ O.

Optionally, the step of forming the isolation structure specifically includes: performing a wet oxidation process, so that the isolation trench is filled with the oxide of the first semiconductor layer, so as to form the isolation structure.

Optionally, the step of forming the oxide layer on the sidewall of the isolation trench and the inner surface of the opening specifically includes: performing a dry oxidation process to form the oxide layer on the inner wall of the isolation trench and the inner surface of the opening.

In the semiconductor device and its manufacturing method provided by the embodiments of the present invention, a cavity structure is formed under the source and drain regions of the third semiconductor layer forming the device, and a semiconductor layer is formed under the channel region of the third semiconductor layer. Such a device structure has the respective advantages of bulk silicon devices and SOI devices, and has the characteristics of low cost, low leakage, low power consumption, fast speed, relatively simple process and high integration. At the same time, compared with SOI devices, the floating body effect and self-heating effect are eliminated, and the lower dielectric constant at the cavity makes it withstand higher voltage. In addition, both the inner surface of the cavity and the sidewall of the isolation trench are covered with an oxidation barrier layer, so that the isolation structure can be formed by a traditional oxidation process, and the process is simple and easy to integrate.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

1-6 show schematic diagrams of various stages of formation of a semiconductor device according to an embodiment of the present invention;

FIG. 7 shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

detailed description

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

The invention proposes a method for manufacturing a semiconductor device with a cavity structure under the source and drain regions, and further forms an oxidation barrier layer on the inner walls of the cavity and the trench, so that the process of forming the isolation structure is different from the existing isolation structure. The process is compatible, the process is simple and easy to integrate.

In order to better understand the technical solutions and technical effects of the present invention, specific embodiments will be described in detail below in conjunction with Flowchart 7 .

First, in step S01 , a substrate is provided, the substrate has a first semiconductor layer 10 , as shown in FIG. 1 .

In the present invention, the substrate is a semiconductor substrate, preferably a bulk substrate with a single semiconductor material, such as a Si substrate, a Ge substrate, a SiGe substrate, or a semiconductor containing other elements or compound semiconductors. The substrate, such as GaAs, InP or SiC, etc., in this embodiment, the substrate is a bulk silicon substrate.

Next, in step S02, a patterned stack of the second semiconductor layer 11 and the third semiconductor layer 12 is formed on the first semiconductor layer 10, the stack has a first oxidation barrier layer 13, and the two sides of the stack are isolation trenches 15, Refer to Figure 2.

In this embodiment, the first semiconductor layer is a bulk silicon substrate. Specifically, first, as shown in FIG. The second semiconductor layer 11 and the third semiconductor layer 12 are formed in a manner, the second semiconductor layer 11 is, for example, epitaxially grown Ge _x Si _1-x , and the third semiconductor layer is, for example, epitaxially grown Si, wherein, 0<x<1; then, deposit a hard mask 13 on the third semiconductor layer 12, and the hard mask 13 is simultaneously the first oxidation barrier layer or at least includes one oxidation barrier layer, such as silicon nitride or silicon nitride and stack of silicon oxide, silicon oxynitride, etc., and then apply a photoresist (photoresist) 14 and etch to form a patterned hard mask 13, as shown in Figure 2; then, the photoresist 14; then, under the cover of the hard mask 13, continue to etch to form patterned second semiconductor layer 11 and third semiconductor layer 12, as shown in Figure 2, the region of the third semiconductor layer 12 is In the area of the active region, the openings on both sides of it are isolation trenches 15, as shown in Figure 2, in this patterning step, according to specific needs, the substrate can also be etched away part of the thickness to form isolation trenches required.

In this embodiment, the second semiconductor layer is formed by selective epitaxial growth. In this way, the device in the first region can be consistent with the traditional device, and the device failure caused by the additional stress caused by the existence of the second semiconductor layer can be avoided. The reduction of mobility improves the performance of the device.

Next, in step S03 , part of the second semiconductor layer is removed from the end of the second semiconductor layer 11 to form an opening 20 , as shown in FIG. 3 .

In this embodiment, wet etching can be used to selectively remove part of the second semiconductor layer 11. Specifically, in a preferred embodiment, the solvent can be 49% HF, 30% H ₂ O ₂ , A mixed solution of 99.8% CH ₃ COOH and H ₂ O, the ratio is 1:18:27:8, by controlling the time, remove the second semiconductor layer at both ends, that is, under the source and drain regions of the active region Without the support of the second semiconductor layer, it is an empty part, thereby forming an opening 20, as shown in FIG. 3 .

Then, in step S04 , an oxide layer 16 and a second oxidation barrier layer 17 are sequentially formed on the sidewalls of the isolation trench and the inner surface of the opening, as shown in FIG. 4 .

In this embodiment, first, the oxide layer 16 is formed by a dry oxidation method, such as a rapid thermal oxidation method, to form an ultra-thin oxide layer, and the thickness can be After thermal oxidation, an oxide layer is formed on the exposed surface of the semiconductor material, that is, an oxide layer 16 is formed on the sidewall and bottom of the isolation trench 15 and the inner surface of the opening 20 . This oxidation process, on the one hand, enables the defects formed on the surface of the semiconductor layer to be repaired during the etching process, and the surface of the exposed semiconductor material is flatter; on the other hand, it also prevents the subsequently formed oxidation barrier layer from directly contacting the second semiconductor layer 11 and The third semiconductor layer 12 is in direct contact.

Next, a second oxidation barrier layer 17 is formed, such as silicon nitride or a stack of silicon nitride. In this embodiment, the second oxidation barrier layer is silicon nitride. First, low-pressure chemical vapor deposition (LPCVD) can be used. method to deposit an oxidation barrier layer of silicon nitride, and then perform etching. Reactive ion etching (RIE) can be used for etching, thereby forming a second Oxidation barrier layer 17, as shown in FIG. 4 .

Then, in step S05 , an oxidation process is performed so that the isolation trench is filled with the oxide of the first semiconductor layer to form an isolation structure 18 , as shown in FIG. 5 .

In this embodiment, a wet oxidation process can be used to form the isolation structure. Since the sidewalls of the isolation trench and the inner surface of the opening are covered by the second oxidation barrier layer 17, during oxidation, the active region of the device will not Subject to oxidation, this process is compatible with traditional device isolation processes, and the wet oxidation process has fast oxidation speed and high efficiency. After the isolation structure 18 is formed, the ends of the opening are closed to form a cavity, as shown in FIG. 5 .

Next, in step S06 , the first oxidation barrier layer 13 is removed, as shown in FIG. 6 .

The first oxidation barrier layer 13 can be selectively removed to expose the third semiconductor layer 12 in the active region, as shown in FIG. 6 .

Finally, a device structure 30 is formed on the third semiconductor layer, and the source and drain regions 31 of the device structure are formed on the opening 20 , as shown in FIG. 6 .

The device can be formed according to a conventional process. In this embodiment, a CMOS device 30 is formed. As shown in FIG. In part of the substrate under the second semiconductor layer, a gate structure 33 is formed on the third semiconductor layer 12; sidewalls 34 are formed on the side walls of the gate structure 33; the third semiconductor layer on both sides of the gate A source-drain region 31 is formed in the layer, and the source-drain region is located above the opening 20; a metal silicide layer 35 is also formed above the source-drain region 31. Afterwards, other components of the device, such as source-drain contacts, gate contacts, and interconnection structures, can also be formed.

So far, the semiconductor device of the embodiment of the present invention has been formed, and the above is only a preferred embodiment of the present invention, and does not limit the present invention in any form.

In addition, the present invention also provides a semiconductor device formed by the above method, as shown in FIGS. 5 and 6, including:

a substrate 10 having a first semiconductor layer;

The second semiconductor layer 11 is located on the substrate 10;

The third semiconductor layer 13 is located on the second semiconductor layer 11;

The isolation structure 18 is located on both sides of the third semiconductor layer 12 and on the substrate 10;

The cavity 20 is located between the end of the second semiconductor layer 11, the third semiconductor layer 12 and the substrate 10;

an oxide layer 16 with an oxidation barrier layer 17 thereon on the inner surface of the cavity 20 and on the sidewalls of the isolation structure 18;

The device structure 30 is located on the third semiconductor layer 12 , and its source and drain regions 31 are located on the cavity 20 .

In the semiconductor device of the present invention, the second semiconductor layer is formed on the substrate, the third semiconductor layer for forming the device is arranged on the second semiconductor layer, and the second semiconductor layer is formed only in the groove of the third semiconductor layer. Under the channel region, a cavity structure is formed between the second semiconductor layer and the isolation, and under the source and drain regions. In this way, due to the existence of the cavity, the leakage current and power consumption of the device are significantly reduced, and the power consumption is increased. device integration. Compared with SOI devices, the bottom of the channel region is connected to the substrate, which has better heat dissipation performance and avoids the generation of floating body effect. At the same time, because the device can use bulk silicon as the substrate, the limitation of high cost of SOI wafer is avoided. In addition, the lower dielectric constant of air in the cavity allows the device to withstand higher voltages.

In addition, the device of the present invention can be applied to environments with strong radiation, such as strategic weapons, etc. Since there is no insulating layer of silicon oxide under the channel, the area of the radiation-sensitive area is reduced, and the back gate can be adjusted to release part of the radiation. Electron-hole pairs caused by irradiation, avoiding the floating body effect caused by irradiation.

In the present invention, the materials of the substrate, the second semiconductor layer, and the third semiconductor layer can be selected according to the needs of the device in the manufacturing process and the performance of the device, and the same or different semiconductor materials can be used. In the preferred implementation of the present invention In an example, the substrate is a bulk silicon substrate, the second semiconductor layer is Ge _x Si _1-x , 0<x<1, and the third semiconductor layer is silicon. The choice of this semiconductor material facilitates the formation of crystals by epitaxial growth The second and third semiconductor layers, the device has more excellent performance.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent of equivalent change Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (8)

1. A semiconductor device, characterized in that, comprising: a substrate having a first semiconductor layer; a second semiconductor layer located on the substrate; a third semiconductor layer located on the second semiconductor layer; an isolation structure located on both sides of the third semiconductor layer and on the substrate; a cavity located between the end of the second semiconductor layer, the third semiconductor layer and the substrate; an oxide layer and an oxidation barrier layer thereon on the inner surface of the cavity and on the sidewalls of the isolation structure; The device structure is located on the third semiconductor layer, and its source and drain regions are located on the cavity. 2. The semiconductor device according to claim 1, wherein the substrate is a bulk silicon substrate, the second semiconductor layer is Ge _x Si _1-x , 0<x<1, and the third semiconductor layer is silicon . 3. A method for manufacturing a semiconductor device, comprising the steps of: providing a substrate having a first semiconductor layer; forming a patterned second semiconductor layer and a third semiconductor layer stack on the first semiconductor layer, with a first oxidation barrier layer on the stack, and isolation trenches on both sides of the stack; removing a portion of the second semiconductor layer from an end portion of the second semiconductor layer to form an opening; sequentially forming an oxide layer and a second oxidation barrier layer on the sidewalls of the isolation trench and the inner surface of the opening; performing an oxidation process so that the isolation trench is filled with the oxide of the first semiconductor layer to form an isolation structure; removing the first oxidation barrier layer; A device structure is formed on the third semiconductor layer, and the source and drain regions of the device structure are formed on the opening. 4. The manufacturing method according to claim 3, wherein the substrate is a bulk silicon substrate, and the steps of forming the second semiconductor layer and the third semiconductor layer are specifically: epitaxially growing a second semiconductor layer of Ge _x Si _1-x on the substrate, 0<x<1; epitaxially growing a third semiconductor layer of silicon on the second semiconductor layer; forming a first oxidation barrier layer on the third semiconductor layer, where the first oxidation barrier layer is a mask layer; Patterning is performed to form a stack of the second semiconductor layer and the third semiconductor layer, with isolation trenches on both sides of the stack. 5. The manufacturing method according to claim 4, wherein the step of removing part of the second semiconductor layer from the end of the second semiconductor layer to form the opening specifically comprises: Wet etching is used to selectively remove the second semiconductor layer to form an opening at the end of the second semiconductor layer. 6 . The manufacturing method according to claim 5 , wherein the wet etching etchant is a mixture of HF, H ₂ O ₂ , CH ₃ COOH and H ₂ O. 7 . The manufacturing method according to claim 3 , wherein the step of forming the isolation structure comprises: performing a wet oxidation process so that the isolation trench is filled with the oxide of the first semiconductor layer to form the isolation structure. 8. The manufacturing method according to claim 3, wherein the step of forming an oxide layer on the sidewalls of the isolation trench and the inner surface of the opening is specifically: performing a dry oxidation process to form an oxide layer on the inner wall of the isolation trench And an oxide layer is formed on the inner surface of the opening.