CN106935503A - The forming method of semiconductor devices - Google Patents

Abstract

A method for forming a semiconductor device, comprising: providing a substrate, an interlayer dielectric layer is provided on the substrate, an opening through the thickness of the interlayer dielectric layer is provided, and sidewalls of the opening have sidewalls; a silicon layer is formed on the sidewall and bottom of the opening, The silicon layer has a first surface roughness; performing repair etching treatment on the surface of the silicon layer, so that the silicon layer has a second surface roughness, and the second surface roughness is smaller than the first surface roughness; after performing the repair etching treatment , performing oxygen plasma treatment on the silicon layer, the sidewall of the sidewall of the opening and the substrate at the bottom of the opening to form a silicon oxide layer with uniform thickness on the sidewall and bottom of the opening; after removing the silicon oxide layer, A gate dielectric layer is formed at the bottom and bottom of the gate dielectric layer; a metal gate electrode filling the opening is formed on the surface of the gate dielectric layer. The method reduces the surface roughness of the gate dielectric layer, thereby reducing the variance of the threshold voltage of semiconductor devices.

Description

Method of forming semiconductor device

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device.

Background technique

MOS (Metal-Oxide-Semiconductor) transistor is one of the most important elements in modern integrated circuits. The basic structure of MOS transistors includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and the gate structure includes : a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; source and drain regions located in the semiconductor substrate on both sides of the gate structure.

With the increasing integration of MOS transistors, the voltage and current required for the operation of MOS transistors continue to decrease, and the switching speed of transistors increases accordingly, and the requirements for semiconductor technology are greatly increased. Therefore, the industry has found a high dielectric constant material (High-K Material) to replace SiO ₂ as the gate dielectric layer to better isolate the gate structure from other parts of the MOS transistor and reduce leakage. At the same time, in order to be compatible with high-K (K greater than 3.9) dielectric constant materials, metal materials are used to replace the original polysilicon as the gate electrode layer. The high-K gate dielectric layer and the metal gate electrode form a metal gate structure, which further reduces the leakage of the MOS transistor.

Usually, a gate-last process is used to form a MOS transistor with a metal gate structure. In the gate-last process, a dummy gate structure is first formed on the semiconductor substrate, and an interlayer dielectric layer is formed on the semiconductor substrate on both sides of the dummy gate structure. , the top surface of the interlayer dielectric layer is flush with the top surface of the dummy gate structure, and then the dummy gate structure is removed, and a metal gate structure is formed at a position defined by the dummy gate structure.

However, in the method for forming a semiconductor device in the prior art, the surface roughness of the gate dielectric layer is relatively large, resulting in a large difference in threshold voltage between different semiconductor devices.

Contents of the invention

The problem solved by the invention is to avoid the problem of large surface roughness of the gate dielectric layer, thereby avoiding the large difference of the threshold voltage of semiconductor devices.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, an interlayer dielectric layer is provided on the substrate, an opening extending through the thickness of the interlayer dielectric layer is provided, and the sidewall of the opening is having a sidewall; forming a silicon layer on the sidewall and bottom of the opening, the silicon layer having a first surface roughness; performing repair etching on the surface of the silicon layer, so that the silicon layer has a second surface roughness degree, the second surface roughness is smaller than the first surface roughness; after the repair etching treatment, oxygen plasma treatment is performed on the silicon layer, the sidewall of the sidewall of the opening, and the substrate at the bottom of the opening, and the A silicon oxide layer with uniform thickness is formed on the sidewall and bottom of the opening; after removing the silicon oxide layer, a gate dielectric layer is formed on the sidewall and bottom of the opening; and a metal layer filling the opening is formed on the surface of the gate dielectric layer. gate electrode.

Optionally, the restoration etching process is a chemical downstream etching method.

Optionally, the process parameters of the chemical downstream etching method are: the etching gas includes CF ₄ and O ₂ , the flow rate of CF ₄ is 100 sccm to 1000 sccm, the flow rate of O ₂ is 5 sccm to 100 sccm, and the source power is 100 watts to 1500 watts, the chamber pressure is 2mtorr~50mtorr, and the temperature is 0°C~200°C.

Optionally, the process parameters of the oxygen plasma treatment are: the gas used includes oxygen, the flow rate of the oxygen is 10sccm-1000sccm, the source radio frequency power is 100 watts-1500 watts, the chamber pressure is 5mtorr-200mtorr, the temperature It is 25 degrees Celsius to 120 degrees Celsius.

Optionally, the silicon layer has a thickness of 5 angstroms to 100 angstroms.

Optionally, the process for forming the silicon layer is an atomic layer deposition process or a plasma chemical vapor deposition process.

Optionally, the process for removing the silicon oxide layer is a wet etching process or a dry etching process.

Optionally, the material of the sidewall is silicon oxide, silicon oxynitride or silicon oxycarbide.

Optionally, the material of the interlayer dielectric layer is silicon oxide, silicon oxynitride or silicon oxycarbide.

Optionally, the material of the gate dielectric layer is a high-K dielectric material.

Optionally, the material of the metal gate electrode is W, Al, Ti, Cu, Mo or Pt.

Compared with the prior art, the technical solution of the present invention has the following advantages:

A silicon layer with a first surface roughness is formed on the sidewall and bottom of the opening, the first surface roughness is relatively large, and the silicon layer has a first surface roughness due to the repair etching treatment on the surface of the silicon layer. Two surface roughness, the second surface roughness is smaller than the first surface roughness, that is, the surface roughness of the silicon layer is reduced by repair etching treatment, and then the silicon layer and part of the sidewall of the opening sidewall Part of the substrate at the bottom of the opening is treated with oxygen plasma to form a silicon oxide layer with a uniform thickness on the sidewall and bottom of the opening. After the repair etching treatment, the surface of the silicon layer on the sidewall and bottom of the opening is rough. The thickness of the oxide layer is small, and the thickness of the oxide layer formed after the oxygen plasma treatment is uniform, so that after the oxide layer is removed, the roughness of the side wall surface of the opening side wall and the base surface of the opening bottom is small, The surface roughness of the gate dielectric layer formed on the sidewall surface and the substrate surface with less roughness is also small, so the difference in the surface roughness of the gate dielectric layer corresponding to different semiconductor devices is small, so that the performance of the semiconductor device The variance of the function is reduced, and the variance of the threshold voltage of the semiconductor device is reduced.

Description of drawings

1 to 8 are structural schematic diagrams of the process of forming a semiconductor device in the first embodiment of the present invention;

9 to 18 are schematic structural views of the process of forming a semiconductor device in the second embodiment of the present invention.

detailed description

As mentioned in the background, semiconductor devices formed in the prior art have poor performance.

The method for forming a semiconductor device in the prior art is studied. The method for forming a semiconductor device includes: providing a semiconductor substrate; forming a dummy gate structure on the semiconductor substrate; forming a dummy gate structure on both sides of the dummy gate structure. sidewalls; forming source and drain regions in the semiconductor substrate on both sides of the dummy gate structure and the sidewalls; after forming the source and drain regions, forming an interlayer dielectric covering the sidewalls of the sidewalls on the semiconductor substrate layer; removing the dummy gate structure to form an opening; forming a gate dielectric layer on the sidewall and bottom of the opening; forming a metal gate electrode filling the opening on the surface of the gate dielectric layer.

In the above method, due to the limit of the process in the process of forming the dummy gate structure, the roughness of the sidewall of the formed dummy gate structure is relatively high. Specifically, as the feature size decreases, the dummy gate structure The size of the photoresist layer is getting smaller and smaller, and the patterned photoresist layer that defines the position and size of the dummy gate structure has higher requirements on photolithography precision, and is limited by the photolithography process. The side of the patterned photoresist layer It is difficult for the wall to be completely perpendicular to the surface of the semiconductor substrate, and the patterned photoresist layer will be lost in the process of forming the dummy gate structure, and the patterned photoresist layer that is damaged by etching acts as a mask The effect becomes worse, resulting in a larger surface roughness of the sidewall forming the dummy gate structure. After the sidewall is formed, the roughness of the interface between the sidewall and the dummy gate structure is relatively large. When the dummy gate structure is removed, the roughness of the sidewall of the opening is relatively large. After the gate dielectric layer is formed, the resulting The surface roughness of the gate dielectric layer on the sidewall of the opening is relatively large, resulting in a large difference in the surface topography of the gate dielectric layer corresponding to different semiconductor devices, and thus a large difference in the threshold voltage of different semiconductor devices.

On this basis, the present invention proposes a method for forming a semiconductor device, by forming a silicon layer on the sidewall and bottom of the opening, and then performing repair etching on the surface of the silicon layer, so that the surface of the silicon layer is rough After that, oxygen plasma treatment is performed on the silicon layer, the sidewall of the sidewall of the opening, and the substrate at the bottom of the opening to form a silicon oxide layer with uniform thickness on the sidewall and bottom of the opening; remove the oxide layer Afterwards, the roughness of the sidewall surface of the sidewall of the opening and the base surface of the bottom of the opening is relatively small. After the gate dielectric layer is formed, the surface roughness of the formed gate dielectric layer is relatively small, so that different semiconductor devices correspond to The variance of the surface roughness of the gate dielectric layer is small, so the variance of the work function of the semiconductor device is reduced, thereby reducing the variance of the threshold voltage of the semiconductor device.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

first embodiment

1 to 8 are structural schematic diagrams of the process of forming a semiconductor device in the first embodiment of the present invention. In this embodiment, description is made by taking that the semiconductor device is a planar MOS transistor as an example.

Referring to FIG. 1 , a substrate is provided, which is a substrate 100 with a dummy gate structure 110, sidewalls 120 positioned on both sides of the dummy gate structure 110, and an interlayer covering the sidewalls of the sidewalls 120. dielectric layer 130 , the top surface of the interlayer dielectric layer 130 is flush with the top surface of the dummy gate structure 110 .

The substrate 100 provides a process platform for subsequent formation of semiconductor devices. The substrate 100 may be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the substrate 100 may also be semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide; in this embodiment, the substrate 100 The material is silicon.

The dummy gate structure 110 includes a dummy gate dielectric layer 111 on the surface of the substrate and a dummy gate electrode 112 on the surface of the dummy gate dielectric layer 111 . In this embodiment, the material of the dummy gate dielectric layer 111 is silicon oxide, and the material of the dummy gate electrode 112 is polysilicon.

The steps of forming the dummy gate structure 110 are: forming a dummy gate dielectric material layer (not shown) and a dummy gate electrode material layer on the surface of the dummy gate dielectric material layer on the surface of the substrate; patterning the dummy gate dielectric material layer and a dummy gate electrode material layer to form a dummy gate dielectric layer 111 and a dummy gate electrode 112 .

Due to the limitation of the process during the process of forming the dummy gate structure 110 , the roughness of the sidewall of the formed dummy gate structure 110 is relatively high.

In one embodiment, the spacer 120 includes an offset sidewall covering the sidewall of the dummy gate structure 110 and a spacer spacer covering the offset sidewall. In another embodiment, the spacer 120 may only include a spacer, and the role of the spacer is to define the distance between the dummy gate structure 110 and the subsequently formed source and drain regions. In this embodiment, the side wall 120 is described as an example that includes only gap side walls.

The process of forming the sidewall 120 is: forming a sidewall material layer covering the dummy gate structure 110 and the substrate; using an anisotropic dry etching process to etch the sidewall material layer. The side walls 110 form side walls 120 . The material of the sidewall 120 is silicon oxide, silicon oxynitride or silicon oxycarbide.

Due to the high roughness of the sidewall of the dummy gate structure 110 , the roughness of the interface between the sidewall 120 and the sidewall of the dummy gate structure 110 is relatively high.

In this embodiment, after the spacer 120 is formed, source and drain regions are formed in the substrate on both sides of the dummy gate structure 110 and the spacer 120 , and then the interlayer dielectric layer 130 is formed.

The material of the interlayer dielectric layer 130 is silicon oxide, silicon oxynitride or silicon oxycarbide.

The step of forming the interlayer dielectric layer 130 is: forming an interlayer dielectric material layer covering the dummy gate structure 110, the spacer 120 and the base, the entire surface of the interlayer dielectric material layer is higher than the top surface of the dummy gate structure 110 ; planarizing the interlayer dielectric material layer until the top surface of the dummy gate structure 110 is exposed to form an interlayer dielectric layer 130 .

Referring to FIG. 2 , the dummy gate structure 110 (refer to FIG. 1 ) is removed to form an opening 140 .

The process of removing the dummy gate structure 110 is a wet etching process or a dry etching process.

Due to the high roughness of the interface between the sidewall 120 and the sidewall of the dummy gate structure 110 , after removing the dummy gate structure 110 , the surface roughness of the sidewall 120 of the sidewall of the opening 140 is relatively high.

Referring to FIG. 3 , a silicon layer 150 having a first surface roughness is formed on sidewalls and bottoms of the opening 140 .

The material of the silicon layer 150 is silicon. The process for forming the silicon layer 150 is a deposition process, such as a plasma chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the silicon layer 150 is formed by an atomic layer deposition process. In this embodiment, the formed silicon layer 150 not only covers the sidewalls 120 of the sidewalls of the opening 140 and the base at the bottom of the opening 140 , but also covers the top surface of the interlayer dielectric layer 130 .

Since the surface roughness of the sidewall 120 of the sidewall of the opening 140 is relatively high, the formed silicon layer 150 is affected by the surface roughness of the sidewall 120 . At this time, the silicon layer 150 has a first surface roughness.

If the thickness of the silicon layer 150 is less than 5 angstroms, the silicon layer 150 in some areas will be consumed during the subsequent repair etching process on the surface of the silicon layer 150, exposing part of the sidewall 120, and the subsequent The chemical downstream etching method used in the repair etching treatment can only be processed for silicon materials at present, so that some areas lose the material basis for the repair etching treatment; if the thickness of the silicon layer 150 is greater than 100 angstroms, the subsequent oxygen plasma During the processing, it is difficult to completely oxidize the silicon layer 150, especially the silicon layer 150 on the sidewall of the opening, so that after the subsequent removal of the oxide layer, part of the silicon layer 150 remains on the sidewall of the opening, increasing the subsequent formation of the silicon layer 150. The capacitance between the gate structure and the conductive plug located on the source and drain regions. Therefore, in this embodiment, the thickness of the silicon layer 150 is selected to be 5 angstroms to 100 angstroms.

Referring to FIG. 4 , the surface of the silicon layer 150 is repaired and etched so that the silicon layer 150 has a second surface roughness which is smaller than the first surface roughness.

The restorative etching process is performed by using a chemical downstream etching (CDE, Chemical Downstream Etch) method.

Before performing the repair etching treatment, the surface roughness of the silicon layer 150 is relatively large, especially the surface roughness of the silicon layer 150 on the sidewall of the opening 140 is relatively large. Referring to FIG. 5, the surface of the silicon layer 150 has a protruding area and a recessed area corresponding to the protruding area.

The process of repairing and etching the surface of the silicon layer 150 by chemical downstream etching is as follows: a passivation film 160 is formed on the surface of the protruding area and the recessed area, and the thickness of the passivation film 160 on the surface of the protruding area is smaller than that of the passivation film in the recessed area. The thickness of 160; gas is generated during the process, and the gas etches the passivation film 160 until the passivation film 160 is completely etched away. Since the thickness of the passivation film 160 in the recessed area is greater than the thickness of the passivation film 160 in the protruding area, and the etching process will also etch the silicon layer 150 to a certain extent, in the process of etching and removing the passivation film 160, The repair gas will etch the protruding area on the surface of the silicon layer 150 to reduce the size of the protruding area; repeat the steps of depositing the passivation film 160, etching to remove the passivation film 160 and etching the protruding area until the silicon layer 150 The roughness of the surface meets the requirements.

Wherein, the material of the passivation film 160 is SiOF; the gas generated during the process is SiF, and the gas etches the passivation film 160 and etches the protruding area of the silicon layer 150 at the same time.

In this embodiment, the process parameters of the chemical downstream etching method for restoration etching treatment are: the etching gas includes CF ₄ and O ₂ , the flow rate of CF ₄ is 100 sccm-1000 sccm, the flow rate of O ₂ is 5 sccm-100 sccm, The source power is 100 watts to 1500 watts, the chamber pressure is 2 mtorr to 50 mtorr, and the temperature is 0 degrees Celsius to 200 degrees Celsius.

After the repair etching process is performed on the surface of the silicon layer 150, the silicon layer 150 has a second surface roughness, and the second surface roughness is smaller than the first surface roughness. That is, the surface of the silicon layer 150 is repaired and etched by a chemical downstream etching method to further reduce the surface roughness of the silicon layer 150 .

Referring to FIG. 6, after performing the repair etching treatment, oxygen plasma treatment is performed on the silicon layer 150, the sidewall 120 of the sidewall of the opening 140, and the substrate at the bottom of the opening, and the sidewall and bottom of the opening 140 are treated with oxygen plasma. A silicon oxide layer 170 with a uniform thickness is formed.

The purpose of the oxygen plasma treatment is to oxidize the silicon layer 150 , part of the sidewall 120 of the sidewall of the opening 140 and part of the substrate at the bottom of the opening.

Since the surface roughness of the silicon layer 150 is relatively small after the repair etching treatment, on this basis, oxygen plasma treatment can form a silicon oxide layer with uniform thickness on the sidewall and bottom of the opening 140 170.

The gas used in the oxygen plasma treatment includes oxygen.

If the flow rate of oxygen used in the oxygen plasma treatment is less than 10 sccm, the density of oxygen plasma will decrease, resulting in low efficiency of oxygen plasma treatment; if the flow rate of oxygen gas is greater than 1000 sccm, process waste will be caused. Therefore, in this embodiment, the flow rate of the oxygen plasma treatment is 10 sccm˜1000 sccm.

If the temperature of the oxygen plasma treatment is lower than 25 degrees centigrade, the energy of the oxygen plasma is low, resulting in a weak bombardment of the oxygen plasma on the surface of the silicon layer 150, resulting in the silicon layer 150, sidewalls 120 and Silicon atoms and oxygen atoms in the substrate are difficult to combine, and if the temperature of the oxygen plasma treatment is higher than 120 degrees Celsius, it is easy to cause damage to other components. Therefore, in this embodiment, the temperature of the oxygen plasma treatment is selected to be 25 degrees Celsius to 120 degrees Celsius.

The source radio frequency power of the oxygen plasma treatment makes the oxygen plasma. If the source radio frequency power is lower than 100 watts, the oxygen cannot be plasmaized. If the source radio frequency power is higher than 1500 watts, It will increase the production cost and be limited by the process conditions. Therefore, in this embodiment, the high-frequency radio frequency power used in the oxygen plasma treatment is 100 watts to 1500 watts.

The chamber pressure used in the oxygen plasma treatment is 5mtorr-200mtorr.

Referring to FIG. 7, after oxygen plasma treatment, the silicon oxide layer 170 (refer to FIG. 6) is removed.

The process for removing the silicon oxide layer 170 is a wet etching process or a dry etching process. In this implementation, the silicon oxide layer 170 is removed by a wet etching process. Specifically, the etching solution used is a hydrofluoric acid solution, the volume percentage concentration of the hydrofluoric acid solution is 20% to 50%, and the temperature is 10 degrees Celsius to 50 degrees Celsius.

Since the surface roughness of the silicon layer 150 on the sidewall and bottom of the opening 140 is relatively small after the restoration etching treatment, and the thickness of the silicon oxide layer 170 formed after the oxygen plasma treatment is uniform, the silicon oxide layer 170 is removed. After the layer 170, the surface of the side wall 120 of the side wall of the opening 140 and the surface of the substrate at the bottom of the opening 140 have relatively small roughness.

Referring to FIG. 8 , after removing the silicon oxide layer 170 , a gate dielectric layer 180 is formed on the sidewall and bottom of the opening 140 ; and a metal gate electrode 190 filling the opening 140 is formed on the surface of the gate dielectric layer 180 .

The material of the gate dielectric layer 180 is a high-K dielectric material (K greater than 3.9), such as HfO ₂ , HfSiO, HfSiON, Al ₂ O ₃ or ZrO ₂ , and the material of the metal gate electrode 190 is metal, such as W, Al , Ti, Cu, Mo or Pt.

The steps of forming the gate dielectric layer 180 and the metal gate electrode 190 are: using a deposition process, such as a plasma chemical vapor deposition process or an atomic layer deposition process, to form a gate dielectric material layer ( not shown) and a metal gate electrode material layer covering the gate dielectric material layer, the entire surface of the metal gate electrode material layer is higher than the top surface of the interlayer dielectric layer 130, and then planarize the gate dielectric material layer and The metal gate electrode material layer exposes the top surface of the interlayer dielectric layer 130 to form the gate dielectric layer 180 and the metal gate electrode 190 .

In this embodiment, before forming the metal gate electrode 190, a work function layer (not shown) covering the gate dielectric layer 180 may also be formed, and after forming the work function layer, a metal gate covering the work function layer may be formed. electrode 190 . The work function layer can adjust the threshold voltage of the semiconductor device.

When the semiconductor device is a P-type MOS transistor, the material of the work function layer is TaN; when the semiconductor device is an N-type MOS transistor, the material of the work function layer is TiAl. The process for forming the work function layer is a deposition process, such as a chemical vapor deposition process or an atomic layer deposition process.

Since the silicon oxide layer 170 is removed, the surface of the sidewall 120 of the side wall of the opening 140 and the surface of the substrate at the bottom of the opening 140 have relatively small roughness. After the gate dielectric layer 180 is formed, the formed gate dielectric layer The surface roughness of the 180 is small, so the difference in the surface roughness of the gate dielectric layer 180 corresponding to different semiconductor devices is small, so that the difference in the work function of the semiconductor device is reduced, and the difference in the threshold voltage of the semiconductor device is reduced. .

Further, if the semiconductor device is a P-type MOS transistor, and the material of the source and drain regions is silicon germanium doped with P-type ions, since silicon germanium has stress on the channel, the performance of the semiconductor device can be improved. Carrier mobility, and in this embodiment, during the process of oxygen plasma treatment, oxygen plasma treatment is performed on the substrate at the bottom of the opening 140, so the substrate at the bottom of the opening 140 will also be oxidized , so that after the silicon oxide layer 170 is removed, a recess will be formed in the substrate, so that the position of the channel moves down relative to the surface of the substrate, so that the stress exerted on the channel by the silicon germanium doped with P-type ions in the source and drain regions further increase.

second embodiment

9 to 18 are schematic structural views of the process of forming a semiconductor device in the second embodiment of the present invention. In this embodiment, the semiconductor device is a fin field effect transistor as an example for description.

9 and FIG. 10 in combination, FIG. 10 is a cross-sectional view taken along the extending direction (A-A1 axis) of the fin in FIG. 220 ; the surface of the fin portion 220 has a dummy gate structure 230 across the fin portion 220 , and the dummy gate structure 230 covers part of the top surface and sidewall of the fin portion 220 .

The substrate 200 provides a process platform for subsequent formation of semiconductor devices. The substrate 200 may be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the substrate 200 may also be semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide; in this embodiment, the substrate 200 The material is silicon.

The fins 220 are formed by patterning the substrate 200 .

The surface of the substrate 200 also has an isolation structure 210 , the surface of the isolation structure 210 is lower than the top surface of the fins 220 , and the isolation structure 210 is used to electrically isolate adjacent fins 220 . The material of the isolation structure 210 includes silicon oxide or silicon oxynitride.

The dummy gate structure 230 includes a dummy gate dielectric layer 231 across the fin portion 220 and a dummy gate electrode 232 covering the dummy gate dielectric layer 231 . Wherein, the dummy gate dielectric layer 231 is located on the surface of the isolation structure 210 and covers part of the top surface and sidewall of the fin 220 . The material of the gate dielectric layer 231 is silicon oxide, and the material of the dummy gate electrode 232 is polysilicon.

The steps of forming the dummy gate structure 230 are: forming a dummy gate dielectric material layer (not shown) and a dummy gate electrode material layer on the surface of the dummy gate dielectric material layer on the surface of the substrate; patterning the dummy gate dielectric material layer and a dummy gate electrode material layer to form a dummy gate dielectric layer 231 and a dummy gate electrode 232 .

Due to the limitation of the process during the process of forming the dummy gate structure 230 , the sidewall of the formed dummy gate structure 230 has relatively high roughness.

Referring to FIG. 11 , FIG. 11 is a schematic diagram formed on the basis of FIG. 10 , forming sidewalls 240 on the sidewalls on both sides of the dummy gate dielectric layer 231 , and then forming fins on both sides of the dummy gate structure 230 and the sidewalls 240 The source and drain regions are formed in part 220, and then an interlayer dielectric layer 250 is formed on the surface of the substrate. The interlayer dielectric layer 250 covers the sidewall of the dummy gate structure 230, and the top surface of the interlayer dielectric layer 250 is connected to the dummy gate. The top surface of structure 230 is flush.

In one embodiment, the spacer 240 includes an offset sidewall covering the sidewall of the dummy gate structure 230 and a spacer spacer covering the offset sidewall. In another embodiment, the spacer 240 may only include spacer spacers, and the role of the spacer spacers is to define the distance between the dummy gate structure 230 and the source and drain regions formed in the fin portion 220 . In this embodiment, the side wall 240 is described as an example that includes only gap side walls.

The process of forming the sidewall 240 is as follows: forming a sidewall material layer covering the dummy gate structure 230 and the substrate; using an anisotropic dry etching process to etch the sidewall material layer, and on the side of the dummy gate structure 230 The walls form side walls 240 . The material of the side wall 240 is silicon oxide, silicon oxynitride or silicon oxycarbide.

Due to the high roughness of the sidewall of the dummy gate structure 230 , the roughness of the interface between the sidewall 240 and the sidewall of the dummy gate structure 230 is relatively high.

The material of the interlayer dielectric layer 250 is silicon oxide, silicon oxynitride or silicon oxycarbide.

The step of forming the interlayer dielectric layer 250 is: forming an interlayer dielectric material layer covering the fin portion 220, the dummy gate structure 230, the isolation structure 210 and the substrate 200, and the entire top surface of the interlayer dielectric material layer is as high as On the top surface of the dummy gate structure 230 ; planarizing the interlayer dielectric material layer until the top surface of the dummy gate structure 230 is exposed to form an interlayer dielectric layer 250 .

Referring to FIG. 12 , the dummy gate structure 230 is removed to form an opening 260 .

The process of removing the dummy gate structure 230 is a wet etching process or a dry etching process.

Since the roughness of the interface between the sidewall 240 and the sidewall of the dummy gate structure 230 is relatively high, after the dummy gate structure 230 is removed, the surface roughness of the sidewall 240 of the sidewall of the opening 260 is relatively high.

Referring to FIG. 13 , a silicon layer 270 having a first surface roughness is formed on sidewalls and bottoms of the opening 260 .

In this embodiment, the formed silicon layer 270 not only covers the sidewalls 240 of the sidewalls of the opening 260 and the base at the bottom of the opening 260 , but also covers the top surface of the interlayer dielectric layer 250 . The material of the silicon layer 270 is silicon. The process for forming the silicon layer 270 is a deposition process, such as a plasma chemical vapor deposition process or an atomic layer deposition process.

Since the surface roughness of the sidewall 240 of the sidewall of the opening 260 is relatively high, and the formed silicon layer 270 is affected by the surface roughness of the sidewall 240 , at this time, the silicon layer 270 has a first surface roughness.

If the thickness of the silicon layer 270 is less than 5 angstroms, the silicon layer 270 in some areas will be consumed in the subsequent repair etching process on the surface of the silicon layer 270, exposing part of the sidewall 240, and the subsequent The chemical downstream etching method used in the repair etching treatment can only be processed for silicon materials at present, so that some areas lose the material basis for the repair etching treatment; if the thickness of the silicon layer 270 is greater than 100 angstroms, the subsequent oxygen plasma During the processing, it is difficult to completely oxidize the silicon layer 270, especially the silicon layer 270 on the sidewall of the opening 260, so that after the subsequent removal of the oxide layer, part of the silicon layer 270 remains on the sidewall of the opening 260, which increases the The subsequently formed gate structure and the capacitance between the conductive plugs on the source and drain regions. Therefore, in this embodiment, the thickness of the silicon layer 270 is selected to be 5 angstroms to 100 angstroms.

Referring to FIG. 14 , the surface of the silicon layer 270 is repaired and etched so that the silicon layer 270 has a second surface roughness which is smaller than the first surface roughness.

The restorative etching process is performed by using a chemical downstream etching (CDE, Chemical Downstream Etch) method.

Before performing the repair etching treatment, the surface roughness of the silicon layer 270 is relatively large, especially the surface roughness of the silicon layer 270 on the sidewall of the opening 260 is relatively large. Referring to FIG. 15 , the surface of the silicon layer 270 has a protruding area. and a recessed area corresponding to the protruding area.

The process of repairing and etching the surface of the silicon layer 270 by chemical downstream etching is as follows: a passivation film 280 is formed on the surface of the protruding area and the recessed area, and the thickness of the passivation film 280 on the surface of the protruding area is smaller than that of the passivation film in the recessed area 280; gas is generated during the process, and the gas etches the passivation film 280 until the passivation film 280 is completely etched away. Since the thickness of the passivation film 280 in the recessed area is greater than the thickness of the passivation film 280 in the protruding area, and the etching process will also etch the silicon layer 270 to a certain extent, during the process of etching and removing the passivation film 280, The repair gas will etch the protruding area on the surface of the silicon layer 270 to reduce the size of the protruding area; repeat the steps of depositing the passivation film 280, etching to remove the passivation film 280 and etching the protruding area until the silicon layer 270 The roughness of the surface meets the requirements.

Wherein, the material of the passivation film 280 is SiOF; the gas generated during the process is SiF, and the gas etches the passivation film 280 and etches the protruding area of the silicon layer 270 at the same time.

In this embodiment, the process parameters of the chemical downstream etching method for restoration etching treatment are: the etching gas includes CF ₄ and O ₂ , the flow rate of CF ₄ is 100 sccm-1000 sccm, the flow rate of O ₂ is 5 sccm-100 sccm, The source power is 100 watts to 1500 watts, the chamber pressure is 2 mtorr to 50 mtorr, and the temperature is 0 degrees Celsius to 200 degrees Celsius.

After the repair etching process is performed on the surface of the silicon layer 270, the silicon layer 270 has a second surface roughness, and the second surface roughness is smaller than the first surface roughness. That is, the surface of the silicon layer 270 is repaired and etched by a chemical downstream etching method to further reduce the surface roughness of the silicon layer 270 .

Referring to FIG. 16, after performing the repair etching treatment, oxygen plasma treatment is performed on the silicon layer 270, the sidewall 240 of the sidewall of the opening 260 and the substrate at the bottom of the opening 260, and the sidewall of the opening 260 and the substrate at the bottom of the opening 260 are treated with oxygen plasma. A silicon oxide layer 271 with uniform thickness is formed at the bottom.

The purpose of the oxygen plasma treatment is to oxidize the silicon layer 270 , part of the sidewall 240 of the sidewall of the opening 260 and part of the substrate at the bottom of the opening 260 .

Since the surface roughness of the silicon layer 270 is small after the repair etching treatment, on this basis, oxygen plasma treatment can be performed to form a silicon oxide layer with uniform thickness on the side wall and bottom of the opening 260 271.

The process parameters of the oxygen plasma treatment are as follows: the gas used includes oxygen, the flow rate of the oxygen is 10sccm～1000sccm, the source radio frequency power is 100 watts～1500 watts, the chamber pressure is 5mtorr～200mtorr, and the temperature is 25 degrees Celsius～ 120 degrees Celsius.

Specifically, the reason for setting the parameter range of the oxygen plasma treatment refers to the first embodiment, and will not be described in detail.

Referring to FIG. 17, after oxygen plasma treatment, the silicon oxide layer 271 (see FIG. 16) is removed.

The method for removing the silicon oxide layer 271 refers to the method for removing the silicon oxide layer 170 in the first embodiment, and will not be described in detail.

Since the surface roughness of the silicon layer 270 on the sidewall and bottom of the opening 260 is relatively small after the repair etching treatment, and the thickness of the silicon oxide layer 271 formed after the oxygen plasma treatment is uniform, the silicon oxide layer 271 is removed. After the layer 271, the surface of the side wall 240 of the side wall of the opening 260 and the surface of the substrate at the bottom of the opening 260 have relatively small roughness.

Referring to FIG. 18 , after removing the silicon oxide layer 271 , a gate dielectric layer 290 is formed on the sidewall and bottom of the opening 260 ; and a metal gate electrode 291 filling the opening 260 is formed on the surface of the gate dielectric layer 290 .

The method of forming the gate dielectric layer 290 and the metal gate electrode 291 refers to the first embodiment and will not be described in detail.

In this embodiment, before forming the metal gate electrode 291, a work function layer (not shown) covering the gate dielectric layer 290 may also be formed, and after forming the work function layer, a metal gate covering the work function layer may be formed. electrode 291 . The work function layer can adjust the threshold voltage of the semiconductor device. The method for forming the work function layer refers to the first embodiment and will not be described in detail.

Since the silicon oxide layer 271 is removed, the surface roughness of the sidewall 240 of the sidewall of the opening 260 and the surface of the substrate at the bottom of the opening 260 are relatively small, so that the surface roughness of the formed gate dielectric layer 290 is relatively small. Therefore, the difference in the surface roughness of the gate dielectric layer 290 corresponding to different semiconductor devices is small, so that the difference in the work function of the semiconductor devices is reduced, and the difference in the threshold voltage of the semiconductor devices is reduced.

Further, if the semiconductor device is a P-type fin field effect transistor, and the material of the source region and the drain region is silicon germanium doped with P-type ions, since silicon germanium has stress on the channel, The carrier mobility of the semiconductor device can be improved, and in this embodiment, during the process of oxygen plasma treatment, the substrate at the bottom of the opening 260 is treated with oxygen plasma, so part of the thickness of the bottom of the opening 260 The base is also oxidized so that after removal of the silicon oxide layer 271 a recess is formed in the base such that the position of the channel at the top of the fin 220 is shifted down relative to the top surface of the fin 220 such that the source and drain regions SiGe doped with P-type ions further increases the stress on the channel.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (11)

1. A method for forming a semiconductor device, characterized in that, comprising: A substrate is provided, the substrate has an interlayer dielectric layer, the interlayer dielectric layer has an opening through its thickness, and the sidewall of the opening has a sidewall; forming a silicon layer on the sidewall and bottom of the opening, the silicon layer having a first surface roughness; Performing repair etching treatment on the surface of the silicon layer, so that the silicon layer has a second surface roughness, and the second surface roughness is smaller than the first surface roughness; After the repair etching treatment, oxygen plasma treatment is performed on the silicon layer, the sidewall of the sidewall of the opening, and the substrate at the bottom of the opening to form a silicon oxide layer with uniform thickness on the sidewall and bottom of the opening; After removing the silicon oxide layer, a gate dielectric layer is formed on the sidewall and bottom of the opening; A metal gate electrode filling the opening is formed on the surface of the gate dielectric layer. 2 . The method for forming a semiconductor device according to claim 1 , wherein the restoration etching process is a chemical downstream etching method. 3 . 3. The method for forming a semiconductor device according to claim 2, wherein the process parameters of the chemical downstream etching method are: the etching gas includes CF ₄ and O ₂ , the flow rate of CF ₄ is 100 sccm-1000 sccm, The flow rate of O ₂ is 5 sccm-100 sccm, the source power is 100 watts-1500 watts, the chamber pressure is 2 mtorr-50 mtorr, and the temperature is 0 degrees Celsius to 200 degrees Celsius. 4. The method for forming a semiconductor device according to claim 1, wherein the process parameters of the oxygen plasma treatment are: the gas used includes oxygen, the flow rate of the oxygen is 10 sccm to 1000 sccm, and the source radio frequency power is 100 watts to 1500 watts, the chamber pressure is 5 mtorr to 200 mtorr, and the temperature is 25 degrees Celsius to 120 degrees Celsius. 5 . The method for forming a semiconductor device according to claim 1 , wherein the silicon layer has a thickness of 5 angstroms to 100 angstroms. 6 . The method for forming a semiconductor device according to claim 1 , wherein the process for forming the silicon layer is an atomic layer deposition process or a plasma chemical vapor deposition process. 7. The method for forming a semiconductor device according to claim 1, wherein the process for removing the silicon oxide layer is a wet etching process or a dry etching process. 8 . The method for forming a semiconductor device according to claim 1 , wherein the material of the sidewall is silicon oxide, silicon oxynitride or silicon oxycarbide. 9. The method for forming a semiconductor device according to claim 1, wherein the material of the interlayer dielectric layer is silicon oxide, silicon oxynitride or silicon oxycarbide. 10. The method for forming a semiconductor device according to claim 1, wherein the material of the gate dielectric layer is a high-K dielectric material. 11. The method for forming a semiconductor device according to claim 1, wherein the material of the metal gate electrode is W, Al, Ti, Cu, Mo or Pt.