CN104733307A - Method for forming semiconductor device - Google Patents

Abstract

A method for forming a semiconductor device comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a first region and a second region, a first initial fin is formed on the surface of the semiconductor substrate in the first region, and a second initial fin is formed on the surface of the semiconductor substrate in the second region; forming a first dummy gate across the first initial fin and a second dummy gate across the second initial fin; forming a sacrificial layer covering the semiconductor substrate, the first initial fin and the second initial fin; removing the first dummy gate to form a first groove and removing the second dummy gate to form a second groove by a first etching process; and removing part of the second initial fin in the thickness direction on the bottom of the second groove by a second etching process, and forming a second fin with a second height. A semiconductor device formed by the method of the invention has fins of different heights, and therefore, the requirements of different devices can be met.

Description

Method of forming semiconductor device

technical field

The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device.

Background technique

With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube.

However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making sub-threshold leakage (sub-threshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to better adapt to the requirement of scaling down the device size, the semiconductor process has gradually begun to transition from planar MOSFET transistors to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFET, the gate can control the ultra-thin body (fin) from at least two sides, which has a much stronger gate-to-channel control ability than planar MOSFET devices, and can well suppress short-channel effects; and FinFET is relatively Compared with other devices, it has better compatibility with the existing integrated circuit manufacturing technology.

However, it is currently required that FinFETs have fins of different heights to meet the requirements of different device performances. For example, the requirements for logic and memory transistors are different, with logic transistors requiring larger fin heights and memory transistors requiring relatively smaller fin heights.

How to manufacture fins with different heights on the same wafer has become an urgent problem to be solved.

Contents of the invention

The problem solved by the present invention is to provide a method for forming a semiconductor device, forming fins with different heights on the same wafer.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate, the semiconductor substrate includes a first region and a second region, and the first region is formed with a first region on the surface of the semiconductor substrate. An initial fin, a second initial fin is formed on the surface of the semiconductor substrate in the second region, and both the first initial fin and the second initial fin have a first height; The first dummy gate, the second dummy gate across the second initial fin; forming a sacrificial layer covering the semiconductor substrate, the first initial fin and the second initial fin; using a first etching process to remove all The first dummy gate is used to form a first groove, and the second dummy gate is removed to form a second groove; a second etching process is used to remove a part of the thickness of the second initial fin at the bottom of the second groove to form a second groove. Three grooves, and forming a second fin with a second height; forming a first gate structure located on the surface of the first initial fin and located in the first groove, forming a structure located on the surface of the second fin and located on the first groove The second gate structure in the triple groove.

Optionally, the step of forming the second fin includes: forming a mask layer filling the first groove and covering the sacrificial layer in the first region; using the mask layer as a mask, using a second etching process , etching and removing part of the thickness of the second initial fin located at the bottom of the second groove, forming a third groove, and forming a second fin with a second height; removing the mask layer.

Optionally, the second etching process is wet etching or dry etching.

Optionally, the process parameters of the dry etching process are: the etching gas includes CF ₄ , Si ₂ F ₆ , HCl, HBr, Cl ₂ , He, Ar or N ₂ , and the flow rate of the etching gas is 40 sccm to 80 sccm, the pressure of the etching reaction chamber is 5 mtorr to 50 mtorr, the etching power is 200 watts to 2000 watts, and the temperature of the etching reaction chamber is 20 degrees to 80 degrees.

Optionally, the difference between the first height and the second height is 20 angstroms to 200 angstroms.

Optionally, a first dielectric layer is formed between the first initial fin and the first dummy gate, and a second dielectric layer is formed between the second initial fin and the second dummy gate.

Optionally, the material of the first dielectric layer and the second dielectric layer is silicon oxide.

Optionally, after the first etching process, the bottom of the first groove exposes the surface of the first dielectric layer, and the bottom of the second groove exposes the surface of the second dielectric layer.

Optionally, before forming the first gate structure and the second gate structure, a step is further included: removing the first dielectric layer.

Optionally, the first etching process is dry etching or wet etching.

Optionally, the dry etching process is plasma etching, and the process parameters of the plasma etching process are: the etching gas includes HBr, O ₂ , Cl ₂ and He, the HBr flow rate is 50 sccm to 500 sccm, The flow rate of _O2 is 2sccm to 20sccm, the flow rate of _Cl2 is 10sccm to 300sccm, the flow rate of He is 50sccm to 500sccm, the pressure of the etching reaction chamber is 2 mTorr to 50 mTorr, and the source power of etching is 200 watts to 2000 watts, The etching plus bias power is 10 watts to 100 watts.

Optionally, after forming the first dummy gate and the second dummy gate, further include the step of: using the first dummy gate as a mask, doping the first initial fins on both sides of the first dummy gate to form The first doping region: using the second dummy gate as a mask, doping the second initial fins on both sides of the second dummy gate to form a second doping region.

Optionally, the first gate structure includes a first gate dielectric layer and a first gate electrode layer located on the surface of the first gate dielectric layer, and the second gate structure includes a second gate dielectric layer and a first gate electrode layer located on the surface of the second gate dielectric layer. The second gate electrode layer on the surface of the dielectric layer.

Optionally, the material of the first gate dielectric layer and the second gate dielectric layer is silicon oxide or a high-k dielectric material, and the material of the first gate electrode layer and the second gate electrode layer is polysilicon or metal.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, after forming the first initial fin portion and the second initial fin portion having the same first height; forming the first dummy gate and the second dummy gate; forming a sacrificial layer; removing the first dummy gate and the second dummy gate dummy gate; using a second etching process to remove part of the thickness of the second initial fin to form a second fin with a second height; the semiconductor devices formed in the present invention have different heights, and by controlling the second etching process The process parameters can be used to adjust the height of the formed second fin to form the height of the second fin consistent with the predetermined target.

Further, in the present invention, after forming the first doped region and the second doped region, the first gate structure and the second gate structure are formed, so as to avoid the high-temperature process for forming the first doped region and the second doped region. The first gate structure and the second gate structure cause adverse effects, and the present invention improves the reliability of the semiconductor device.

Furthermore, a first dielectric layer is formed between the first initial fin and the first dummy gate to protect the top of the first initial fin from damage, prevent the subsequent second etching process from causing adverse effects on the first initial fin, and improve The electrical properties of the formed semiconductor devices.

Description of drawings

FIG. 1 is a schematic flow diagram of forming a semiconductor device provided by an embodiment of the present invention;

2 to 15 are schematic cross-sectional structure diagrams of a semiconductor device formation process provided by another embodiment of the present invention.

Detailed ways

It can be seen from the background art that in the prior art, FinFET fins formed on the same wafer (ie semiconductor substrate) have the same height, which is not conducive to meeting the performance requirements of different devices.

In order to solve the above problems, the formation process of semiconductor devices is studied. The formation method of semiconductor devices includes the following steps, please refer to FIG. 1: step S1, providing an initial semiconductor substrate, the initial semiconductor substrate has a first region and a second region; step S2, forming a patterned mask layer on the surface of the initial semiconductor substrate; step S3, using the mask layer as a mask, etching the initial semiconductor substrate to form a semiconductor substrate, and the A first fin is formed on the surface of the semiconductor substrate in the first region, and a second fin is formed on the surface of the semiconductor substrate in the second region; step S4, forming a first dummy gate across the first fin, across the second fin the second dummy gate; step S5, forming a first doped region in the semiconductor substrate on both sides of the first dummy gate, and forming a second doped region in the semiconductor substrate on both sides of the second dummy gate Step S6, forming a sacrificial layer covering the surface of the semiconductor substrate, the top of the sacrificial layer is flush with the top of the first dummy gate and the top of the second dummy gate; step S7, removing the first dummy gate to form a first groove, removing The second dummy gate forms a second groove; step S8, forming a first gate structure located on the surface of the first fin and located in the first groove, forming a structure located on the surface of the second fin and located in the second groove The second gate structure.

However, in the semiconductor device formed by the above method, since the first fin and the second fin are formed in the same process, the formed first fin and the second fin have the same height. Currently, fins with different heights are required to meet the requirements of different device performances. For example, the requirements for logic and memory transistors are different, with logic transistors requiring larger fin heights and memory transistors requiring relatively smaller fin heights.

To this end, the present invention provides a method for forming a semiconductor device, forming a first initial fin and a second initial fin with a first height on the surface of a semiconductor substrate; forming a first dummy gate across the first initial fin , the second dummy gate across the second initial fin; forming a sacrificial layer on the surface of the semiconductor substrate; removing the first dummy gate and the second dummy gate; using a second etching process to etch and remove a partial thickness of the second initial fin portion, forming a second fin portion having a second height. The invention forms fins with different heights to meet the requirements of different devices.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

2 to 15 are schematic cross-sectional structure diagrams of a semiconductor device formation process provided by another embodiment of the present invention.

Please refer to FIG. 2 to FIG. 3 , FIG. 3 is a schematic cross-sectional structural view of FIG. 2 along the XX1 direction, providing a semiconductor substrate 200, the semiconductor substrate 200 includes a first region I and a second region II, and the first region I A first initial fin 201 is formed on the surface of the semiconductor substrate 200, a second initial fin 202 is formed on the surface of the second region II semiconductor substrate 200, and the first initial fin 201 and the second initial fin 202 Both have a first height h1.

The function of the semiconductor substrate 200 is to provide a working platform for subsequent formation of semiconductor devices.

The material of the semiconductor substrate 200 is silicon, germanium, silicon germanium, gallium arsenide, silicon carbide or silicon on insulator.

In this embodiment, the material of the semiconductor substrate 200 is silicon.

The first area I is used to define the area of the working platform where the first initial fin 201 with the first height h1 is formed, and the second area II is used to define the area where the second fin with the second height is formed subsequently. Working platform area. The first area I is one of the NMOS area or the PMOS area, the second area II is one of the NMOS area or the POMS area, and the types of the first area I and the second area II can be the same or can be different.

The first initial fin portion 201 and the second initial fin portion 202 may be the same initial fin portion, or separate and different initial fin portions. In this embodiment, the first initial fin 201 and the second initial fin 202 are used as the same initial fin for exemplary illustration. The first initial fin 201 located on the surface of the semiconductor substrate 200 in the first region I is the first initial fin 201 located in the second region. II The surface of the semiconductor substrate 200 is the second initial fin portion 202, which is distinguished by a dotted line in the figure.

The first initial fin portion 201 and the second initial fin portion 202 are formed by etching an initial semiconductor substrate by dry etching (RIE: Reactive Ion Etching).

As an example, the steps of forming the first initial fin 201 and the second initial fin 202 are: providing an initial semiconductor substrate, forming a patterned mask on the surface of the initial semiconductor substrate, so The mask plate defines the positions for the subsequent formation of the first initial fin portion 201 and the second initial fin portion 202. Using the patterned mask plate as a mask, a reactive ion etching process is used to etch a partial thickness of the initial semiconductor substrate. To form the semiconductor substrate 200 , a first initial fin 201 is formed on the surface of the semiconductor substrate 200 in the first region I, and a second initial fin 202 is formed on the surface of the semiconductor substrate 200 in the second region II.

Both the first initial fin portion 201 and the second initial fin portion 202 have a first height h1. The first height h1 at this time is the height from the top surfaces of the first initial fin portion 201 and the second initial fin portion 202 to the surface of the semiconductor substrate 200 .

In other embodiments of the present invention, when the first initial fin and the second initial fin are separate initial fins, an isolation layer may also be formed on the surface of the semiconductor substrate, and the top of the isolation layer is lower than the first fin. The initial fin and the top of the second initial fin, the isolation layer is used to isolate the adjacent first initial fin and the second initial fin, to prevent the electricity generated between the subsequently formed first fin and the second fin connect. The material of the isolation layer is silicon oxide, silicon nitride or silicon oxynitride, and the isolation layer is formed by physical vapor deposition or chemical vapor deposition process. When an isolation layer is formed on the surface of the semiconductor substrate, the first height of the first initial fin is the distance from the top surface of the first initial fin to the surface of the isolation layer, and the first height of the second initial fin is the second The distance from the top surface of the initial fin to the surface of the isolation layer.

It should also be noted that, in this embodiment, a first initial fin 201 is formed on the surface of the semiconductor substrate 200 in the first region I, and a second initial fin 202 is formed on the surface of the semiconductor substrate 200 in the second region II. In other embodiments of the present invention, a plurality of first initial fins may be formed on the surface of the semiconductor substrate in the first region, and a plurality of second initial fins may be formed on the surface of the semiconductor substrate in the second region. The number of initial fins and second initial fins.

Please refer to FIG. 4 to FIG. 5. FIG. 5 is a schematic cross-sectional structure diagram along the XX1 direction of FIG. Grid 222.

The first dummy gate 212 and the second dummy gate 222 define the positions of the subsequently formed first gate structure and the second gate structure. The first dummy gate 211 spans the first initial fin 201, that is, the first dummy gate 211 covers the top and sidewalls of the first initial fin 201; the second dummy gate 222 spans the second initial fin portion 202 , that is, the second dummy gate 222 covers the top and sidewalls of the second initial fin portion 202 .

The first dummy gate 212 and the second dummy gate 222 will be removed in subsequent processes, therefore, the materials of the first dummy gate 212 and the second dummy gate 222 are compatible with the first initial fin portion 201 and the second initial fin The material of the portion 202 is different. In this embodiment, the material of the first dummy gate 212 and the second dummy gate 222 is polysilicon.

In this embodiment, a first dielectric layer 211 is formed between the first initial fin 201 and the first dummy gate 212 , and a second dielectric layer 211 is formed between the second initial fin 202 and the second dummy gate 222 . Medium layer 221. The first dielectric layer 211 is used as an etch stop layer for subsequent etching to remove the first dummy gate 211, and the first dielectric layer 211 can also be used as a barrier layer for subsequent etching to remove the first dummy gate 211 to avoid the first The top of the initial fin portion 201 is damaged; the second dielectric layer 221 serves as an etch stop layer for subsequent etching to remove the second dummy gate 222, and the second dielectric layer 221 can also be used as a subsequent etching to remove the second dummy gate 222 to prevent the top of the second initial fin portion 202 from being damaged.

In this embodiment, the material of the first dielectric layer 211 and the second dielectric layer 221 is silicon oxide.

The step of forming the first dielectric layer 211, the first dummy gate 212, the second dielectric layer 221 and the second dummy gate 222 includes: forming the covering semiconductor substrate 200, the first initial fin 201 and the second initial fin 202 A dielectric film and a dummy gate film positioned on the surface of the dielectric film; a patterned photoresist layer is formed on the surface of the dummy gate film, and the patterned photoresist layer has a structure corresponding to the formation of the first dummy gate 212 and the second dummy gate 212. The pattern of the dummy gate 222; using the patterned photoresist layer as a mask, etch the dielectric film and the dummy gate film to form the first dummy gate 212 across the first initial fin 201, and across the The second dummy gate 222 of the second initial fin portion 202, and the first dielectric layer 211 is formed between the first initial fin portion 201 and the first dummy gate 212, and between the second initial fin portion 202 and the second dummy gate 222 A second dielectric layer 221 is formed.

It should be noted that, after forming the first dummy gate 212 and the second dummy gate 222 , a step may also be included: using the first dummy gate 212 as a mask, forming the first initial fins on both sides of the first dummy gate 212 Doping the fin portion 201 to form a first doped region; using the second dummy gate 222 as a mask, doping the second initial fins 202 on both sides of the second dummy gate 222 to form a second doped region .

Please continue to refer to FIG. 4 to FIG. 5 , first spacers 203 are formed on both sides of the first dummy gate 212 , and second spacers 204 are formed on both sides of the second dummy gate 222 .

The function of the first sidewall 203 is to protect the sidewall of the subsequently formed first gate structure, and the function of the second sidewall 204 is to protect the sidewall of the subsequently formed second gate structure.

The material of the first sidewall 203 and the second sidewall 204 is silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the first sidewall 203 and the second sidewall 204 is silicon nitride.

As an embodiment, the step of forming the first spacer 203 and the second sidewall 204 includes: forming 212 and the sidewall layer of the second dummy gate 222; remove the sidewall layer located on the surface of the semiconductor substrate 200, the top of the first initial fin 201 and the top of the second initial fin 202, and form the second dummy gate 211 on both sides A sidewall 203 forms a second sidewall 204 on both sides of the second dummy gate 222 .

Please refer to FIG. 6 , a sacrificial layer 205 covering the semiconductor substrate 200 , the first initial fin 201 and the second initial fin is formed, and the top of the sacrificial layer 205 is connected to the first dummy gate 212 and the second dummy gate 222 The top is flush.

The sacrificial layer 205 is used for subsequent protection of the first initial fin portion 201 and the second initial fin portion 202 to ensure effective subsequent processes.

The material of the sacrificial layer 205 is silicon oxide, silicon nitride or silicon oxynitride, and the sacrificial layer 205 is formed by physical vapor deposition or chemical vapor deposition. In this embodiment, the material of the sacrificial layer 205 is silicon nitride. In other embodiments of the present invention, the material of the sacrificial layer may be silicon oxide.

As an embodiment, the step of forming the sacrificial layer 205 includes: forming a gate covering the semiconductor substrate 200 , the first initial fin portion 201 , the second initial fin portion 202 , the first dummy gate 212 and the second dummy gate 222 sacrificial film: planarizing the sacrificial film to expose tops of the first dummy gate 212 and the second dummy gate 222 to form a sacrificial layer 205 .

Referring to FIG. 7 , using the sacrificial layer 205 as a mask, the first dummy gate 212 is removed to form a first groove 206 , and the second dummy gate 222 is removed to form a second groove 207 .

Specifically, the first dummy gate 212 and the second dummy gate 222 are etched and removed by dry etching or wet etching until the first dielectric layer 211 and the second dielectric layer 221 are exposed.

As an embodiment, the first dummy gate 212 and the second dummy gate 222 are etched and removed by using a plasma dry etching process. The process parameters of the plasma dry etching process are: the etching gas includes HBr, O ₂ , Cl ₂ and He, the flow rate of HBr is 50 sccm to 500 sccm, the flow rate of O ₂ is 2 sccm to 20 sccm, and the flow rate of Cl ₂ is 10 sccm to 300 sccm , the He flow rate is 50 sccm to 500 sccm, the etching reaction chamber pressure is 2 mTorr to 50 mTorr, the etching source power is 200 W to 2000 W, and the etching bias power is 10 W to 100 W.

The bottom of the first groove 206 exposes the surface of the first dielectric layer 211 , and the bottom of the second groove 207 exposes the surface of the second dielectric layer 221 . The first dielectric layer 211 can be used as an etching stop layer, and can also protect the top of the first initial fin portion 201 from being damaged by the etching process; similarly, the second dielectric layer 221 can be used as an etching stop layer , can also protect the top of the second initial fin portion 202 from being damaged by the etching process.

Referring to FIG. 8 , a mask layer 208 filling the first groove 206 (please refer to FIG. 7 ) and covering the first region I sacrificial layer 205 is formed.

The material of the mask layer 208 is different from that of the sacrificial layer 205 .

In this embodiment, the mask layer 208 is a photoresist layer. As an embodiment, the forming step of the mask layer 208 includes: forming an initial photoresist layer that fills the first groove 206, the second groove 207 and covers the sacrificial layer 205; Perform exposure and development, remove the initial photoresist layer located in the second groove 207, remove the initial photoresist layer located on the surface of the second region II sacrificial layer 205, and form a layer that fills the first groove 206 and covers the first region I. The masking layer 208 of the sacrificial layer 205 .

The bottom of the first groove 206 has a first dielectric layer 211, and the first dielectric layer 211 prevents the mask layer 208 from directly contacting the top of the first initial fin 201, preventing the process of forming the mask layer 208 from affecting the first initial fin. damage to the top of portion 201 and improve the electrical performance of the formed semiconductor device.

In other embodiments of the present invention, the mask layer may be a stacked structure of a photoresist layer and an anti-reflection coating, and the material of the mask layer may also be silicon nitride.

Please refer to FIG. 9 , using the mask layer 208 as a mask, the second initial fin 202 (please refer to 8 ), forming a third groove 209 and forming a second fin 210 with a second height h2.

In this embodiment, the bottom of the second groove 207 has a second dielectric layer 221 (please refer to FIG. 8 ), and the second dielectric layer 221 is etched and removed before the partial thickness of the second initial fin 202 is etched away.

The second etching process is wet etching or dry etching.

As an example, the process parameters of the dry etching process are: the etching gas includes CF ₄ , Si ₂ F ₆ , HCl, HBr, Cl ₂ , He, Ar or N ₂ , and the flow rate of the etching gas is 40 sccm to 80 sccm, the pressure of the etching reaction chamber is 5 mtorr to 50 mtorr, the etching power is 200 watts to 2000 watts, and the temperature of the etching reaction chamber is 20 degrees to 80 degrees.

In this embodiment, the etched thickness of the second initial fin portion 202 is 20 angstroms to 200 angstroms.

The first initial fin portion 201 has a first height h1, the second fin portion 210 has a second height h2, and the difference between the first height h1 and the second height h2 is 20 angstroms to 200 angstroms. The first initial fin portion 201 serves as the first fin portion for forming a semiconductor device. By controlling the second etching process parameters, the second initial fin portion 202 with a predetermined thickness can be etched away to form a first fin portion with a predetermined height difference. and the second fin. It should be noted that, when part of the thickness of the second initial fin 202 (please refer to FIG. 8 ) is removed, the width of the removed part of the thickness of the second initial fin 202 is: the width of the second dummy gate 222 (please refer to FIG. 6 ). The spanned width when spanning the second initial fin 202 .

Referring to FIG. 10 , the mask layer 208 (please refer to FIG. 9 ) and the first dielectric layer 211 (please refer to FIG. 9 ) are removed to expose the top of the first initial fin portion 201 .

In this embodiment, the mask layer 208 is a photoresist layer, and the mask layer 208 is removed by an ashing process. As an example, the process parameters of the ashing process are as follows: the flow rate of O ₂ is 50 sccm to 200 sccm, and the ashing temperature is 100 degrees to 450 degrees.

In other embodiments of the present invention, when the material of the mask layer is silicon nitride, a wet etching process is used to remove the mask layer, and the etching liquid of the wet etching is a phosphoric acid solution, wherein the solution The temperature is 120 to 200 degrees, and the mass percentage of phosphoric acid is 65% to 85%.

The first dielectric layer 211 is removed by using a wet etching process. As an embodiment, the etching liquid in the wet etching process is a hydrofluoric acid solution.

In other embodiments of the present invention, the mask layer may also be removed by dry etching or wet etching.

The first dielectric layer 211 is removed to expose the top of the first initial fin portion 201 . In this embodiment, the first initial fin 201 is the first fin, the height difference between the first fin and the second fin 209 is 20 Å to 200 Å, and the top of the second fin 209 is lower than the first fin. section top.

Please refer to FIG. 11 , a first gate structure 230 is formed on the surface of the first initial fin 201 , the first gate structure 230 includes a first gate dielectric layer 231 on the surface of the first initial fin 201 , The first gate electrode layer 232 on the surface of a gate dielectric layer 231 forms a second gate structure 240 on the surface of the second fin 209, and the second gate structure 240 includes a second gate structure 240 on the surface of the second fin 209. The gate dielectric layer 241 and the second gate electrode layer 242 located on the surface of the second gate dielectric layer 241 .

The material of the first gate dielectric layer 231 and the second gate dielectric layer 241 is silicon oxide or a high-k dielectric material (a high-k dielectric material refers to a dielectric material with a relative permittivity greater than 3.9 (relative permittivity of silicon oxide)) . The high-k dielectric material is HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ .

The material of the first gate electrode layer 232 and the second gate electrode layer 242 is polysilicon or conductive metal. The conductive metal is one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN or WSi.

In this embodiment, the material of the first gate dielectric layer 231 and the second gate dielectric layer 241 is HfO ₂ , the thickness is 50 angstroms to 200 angstroms, and the second gate electrode layer 232 and the second gate electrode layer 242 The material is W, and the thickness is 1000 angstroms to 10000 angstroms.

In this embodiment, after the first doped region and the second doped region are formed, the first gate structure 230 and the second gate structure 240 are formed to avoid the formation of the first doped region and the second doped region. The first gate structure 230 and the second gate structure 240 cause adverse effects and improve the reliability of the formed semiconductor device. If the first doped region and the second doped region are formed after the first gate structure and the second gate structure are formed, the high temperature for forming the first doped region and the second doped region will cause the first gate electrode layer and the The metal ions in the second gate electrode layer diffuse into the first gate dielectric layer and the second gate dielectric layer, causing electric leakage of the semiconductor device and reducing the reliability of the semiconductor device.

Please refer to Figure 12 to Figure 15, Figure 13 is a schematic cross-sectional structure diagram of Figure 12 along the XX1 direction, Figure 14 is a schematic cross-sectional structural diagram of Figure 12 along the YY1 direction, Figure 15 is a schematic cross-sectional structural schematic diagram of Figure 12 along the ZZ1 direction, remove all The sacrificial layer 205 (please refer to FIG. 11 ).

The sacrificial layer 205 is removed by a wet etching process. In this embodiment, the material of the sacrificial layer 205 is silicon nitride, and the etching liquid of the wet etching process is a hot phosphoric acid solution, wherein the temperature of the solution is 120 to 200 degrees, and the mass percentage of phosphoric acid is 65%. to 85%.

In other embodiments of the present invention, when the material of the sacrificial layer is silicon oxide, the etching liquid of the wet etching process is a hydrofluoric acid solution.

In this embodiment, the first initial fin 201 is a first fin of a semiconductor device, the first fin has a first height h1, and a second fin with a second height h2 is formed. Since the thickness of the second initial fin portion 202 (please refer to FIG. 8 ) is removed from 20 angstroms to 200 angstroms, the height difference between the first height h1 and the second height h2 is 20 angstroms to 200 angstroms; in other embodiments of the present invention, By controlling the process parameters of the second etching process, the direct height difference between the first height and the second height can be controlled to form fins with different heights that meet the set target.

It should be noted that, in other embodiments of the present invention, more regions can also be formed, and more fins with different heights can be formed according to the above method, for example, the semiconductor substrate is divided into three regions, and fins with three fins are formed. fins with different heights, or divide the semiconductor substrate into four or five regions to form fins with four or five different heights respectively.

In the following, the semiconductor substrate is divided into three regions to form fins with three different heights for an exemplary description.

Specifically, a semiconductor substrate is provided, the semiconductor substrate includes a first region, a second region and a third region, the surface of the semiconductor substrate in the first region has a first initial fin, and the surface of the semiconductor substrate in the second region has a second The initial fin, the surface of the semiconductor substrate in the third region has a third initial fin, and the first initial fin, the second initial fin and the third initial fin have the same height, which is the first height H1; The first dummy gate of the first initial fin, forming the second dummy gate across the second initial fin, forming the third dummy gate across the third initial fin; forming a sacrificial layer; removing the first dummy gate to form the second dummy gate A groove, removing the second dummy gate to form a second groove, removing the third dummy gate to form a third groove; forming a first mask covering the first region, the first groove, the second region, and the second groove plate; using the first mask plate as a mask, the third initial fin portion at the bottom of the third groove with a partial thickness is etched and removed to form a third fin portion, and the third fin portion has a third height H3 ; removing the first mask; forming a second mask covering the first region, the first groove, the third region, and the third fin; using the second mask as a mask, etching Partial thickness of the second initial fin at the bottom of the second groove is removed to form a second fin having a second height H2. The first fin is the first initial fin, the height of the first fin is H1, the height difference between the first fin and the second fin is H1-H2, and the height difference between the first fin and the third fin is The height difference is H1-H3.

In summary, the technical solution of the present invention has the following advantages:

First, after forming the first initial fin and the second initial fin having the same first height; forming the first dummy gate and the second dummy gate; forming a sacrificial layer; removing the first dummy gate and the second dummy gate; The second etching process removes part of the thickness of the second initial fin to form a second fin with a second height; the semiconductor devices formed in the present invention have different heights, and by controlling the process parameters of the second etching process, The height of the formed second fin can be changed to form the height of the second fin consistent with the predetermined target.

Secondly, in the present invention, the first gate structure and the second gate structure are formed after the first doped region and the second doped region are formed, so as to avoid the high-temperature process for forming the first doped region and the second doped region. The first gate structure and the second gate structure cause adverse effects, and the present invention improves the reliability of the semiconductor device.

Again, a first dielectric layer is formed between the first initial fin and the first dummy gate to protect the top of the first initial fin from damage, prevent the subsequent second etching process from causing adverse effects on the first initial fin, and improve the formation of the first initial fin. electrical properties of semiconductor devices.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (14)

1. A method for forming a semiconductor device, comprising: A semiconductor substrate is provided, the semiconductor substrate includes a first region and a second region, a first initial fin is formed on the surface of the semiconductor substrate in the first region, and a second initial fin is formed on the surface of the semiconductor substrate in the second region. fins, and each of the first initial fin and the second initial fin has a first height; forming a first dummy gate across the first initial fin and a second dummy gate across the second initial fin; forming a sacrificial layer covering the semiconductor substrate, the first initial fin, and the second initial fin; Using a first etching process, removing the first dummy gate to form a first groove, and removing the second dummy gate to form a second groove; Using a second etching process, removing part of the thickness of the second initial fin located at the bottom of the second groove, forming a third groove, and forming a second fin with a second height; A first gate structure is formed on the surface of the first initial fin and located in the first groove, and a second gate structure is formed on the surface of the second fin and located in the third groove. 2. The method for forming a semiconductor device according to claim 1, wherein the step of forming the second fin comprises: forming a mask layer that fills the first groove and covers the sacrificial layer in the first region; The mask layer is a mask, and a second etching process is used to etch and remove part of the thickness of the second initial fin located at the bottom of the second groove to form a third groove and form a second fin with a second height. the fin portion; removing the masking layer. 3. The method for forming a semiconductor device according to claim 2, wherein the second etching process is wet etching or dry etching. 4. The method for forming a semiconductor device according to claim 3, wherein the process parameters of the dry etching process are: the etching gas includes CF ₄ , Si ₂ F ₆ , HCl, HBr, Cl ₂ , He, Ar or N ₂ , the flow rate of the etching gas is 40 sccm to 80 sccm, the pressure of the etching reaction chamber is 5 millitorr to 50 millitorr, the etching power is 200 watts to 2000 watts, and the temperature of the etching reaction chamber is 20 degrees to 80 degrees. 5 . The method for forming a semiconductor device according to claim 1 , wherein the difference between the first height and the second height is 20 angstroms to 200 angstroms. 6. The method for forming a semiconductor device according to claim 1, wherein a first dielectric layer is formed between the first initial fin and the first dummy gate, and a first dielectric layer is formed between the second initial fin and the first dummy gate. A second dielectric layer is formed between the two dummy gates. 7. The method for forming a semiconductor device according to claim 6, wherein the material of the first dielectric layer and the second dielectric layer is silicon oxide. 8. The method for forming a semiconductor device according to claim 6, wherein after the first etching process, the bottom of the first groove exposes the surface of the first dielectric layer, and the bottom of the second groove exposes the surface of the second dielectric layer. layer surface. 9. The method for forming a semiconductor device according to claim 6, further comprising a step of removing the first dielectric layer before forming the first gate structure and the second gate structure. 10. The method for forming a semiconductor device according to claim 1, wherein the first etching process is dry etching or wet etching. 11. The method for forming a semiconductor device according to claim 10, wherein the dry etching process is plasma etching, and the process parameters of the plasma etching process are: the etching gas comprises HBr, O ₂ , Cl ₂ and He, the HBr flow rate is 50 sccm to 500 sccm, the O ₂ flow rate is 2 sccm to 20 sccm, the Cl ₂ flow rate is 10 sccm to 300 sccm, the He flow rate is 50 sccm to 500 sccm, and the etching reaction chamber pressure is 2 mTorr to 50 mTorr, the etching source power is 200 watts to 2000 watts, and the etching bias power is 10 watts to 100 watts. 12. The method for forming a semiconductor device according to claim 1, further comprising the step of: using the first dummy gate as a mask, forming the first dummy gate Doping the first initial fins on both sides of the dummy gate to form a first doped region; using the second dummy gate as a mask, doping the second initial fins on both sides of the second dummy gate to form the second doped region. 13. The method for forming a semiconductor device according to claim 1, wherein the first gate structure comprises a first gate dielectric layer, a first gate electrode layer located on the surface of the first gate dielectric layer, and the first The double gate structure includes a second gate dielectric layer and a second gate electrode layer located on the surface of the second gate dielectric layer. 14. The method for forming a semiconductor device according to claim 13, wherein the material of the first gate dielectric layer and the second gate dielectric layer is silicon oxide or a high-k dielectric material, and the first gate electrode layer and the material of the second gate electrode layer is polysilicon or metal.