CN104485325A - Structure for reducing warpage of wafer-level integrated passive device and manufacturing method - Google Patents

Abstract

The invention relates to a structure and a manufacturing method for reducing warping of wafer-level integrated passive devices, comprising a first metal layer and a second metal layer, the second metal layer is located on the upper layer of the first metal layer, and the second metal layer The second metal layer is a spiral coil structure, and the first metal layer is a bridge wire connecting the inside and outside of the coil; it is characterized in that: insulation is provided in the overlapped area between the first metal layer and the second metal layer layer. The manufacturing method includes the following steps: (1) making the first metal layer on the wafer; (2) coating the entire wafer with a photosensitive organic polymer to make through holes; removing the photosensitive organic polymer and retaining the first The photosensitive organic polymer in the area where the metal layer is located is cured; (3) making the second metal layer, and the overlapping area between the second metal layer and the first metal layer overlaps with the insulating layer. The invention improves the problem of disc warpage caused by the organic medium layer.

Description

Structure and fabrication method for reducing warpage of wafer-level integrated passive devices

technical field

The invention relates to a structure and a manufacturing method for reducing the warping of wafer-level integrated passive devices, and belongs to the technical field of wafer-level integration of passive devices.

Background technique

Traditional passive devices are packaged in discrete packages, containing only one electronic component in a package. This type of packaging cannot meet the growing demand for low cost and high integration, so integrated passive devices have been developed rapidly. Fabricating integrated passive devices on wafers using thin-film technology is a potential manufacturing scheme for integrated passive devices.

Organic polymers (such as polyimide, BCB (benzocyclobutene), etc.) can be used as dielectric layers for integrated passive devices due to their low cost, mature technology, and excellent electrical properties. The traditional method of making an organic dielectric layer is to coat a whole layer of organic dielectric on the surface of the wafer, and make through holes on this layer of organic dielectric layer by etching or photolithography to realize the gap between the upper and lower layers of the dielectric layer. interconnection between. However, due to the large gap between the thermal expansion coefficient CTE of organic polymers (such as BCB 42ppm/℃) and the thermal expansion coefficient of general substrate materials (such as silicon 3.2ppm/℃, laminated materials 15~17ppm/℃), in the process Due to the heating and cooling process of lithography, curing and other processes, large thermal stress often occurs, causing wafer warping, affecting process accuracy, and bringing some reliability problems, affecting yield.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art and provide a structure and manufacturing method for reducing the warpage of wafer-level integrated passive devices. Wafer warpage caused by the dielectric layer.

According to the technical solution provided by the present invention, the structure for reducing the warpage of wafer-level integrated passive devices includes a first metal layer and a second metal layer arranged on the wafer, and the second metal layer is located on the first The upper layer of the first metal layer, the second metal layer is a spiral coil structure arranged on the surface of the wafer; one end of the first metal layer is located at the inner circle of the second metal layer coil, and the other end of the first metal layer One end is located on the outer ring of the second metal layer coil, and the first metal layer forms a bridge line connecting the inside and outside of the second metal layer coil; it is characterized in that: between the first layer metal layer and the second layer metal layer An insulating layer is provided in the overlapping area, and the insulating layer covers the area where the first metal layer is located, the overlapping part of the isolated bridge line and the coil.

Further, the plane shape of the insulating layer is a rounded rectangle.

Further, the first metal layer and the second metal layer are connected through through holes provided on the wafer.

The manufacturing method of the wafer-level integrated passive device warping structure is characterized by comprising the following steps:

(1) Make the first metal layer on the wafer as a bridge connecting the inside and outside of the inductor coil;

(2) Coat the entire wafer with a photosensitive organic polymer, and make a through hole connecting the first metal layer and the second metal layer through a photolithography or etching process; remove the photosensitive organic polymer and retain the first layer of metal The photosensitive organic polymer in the area where the layer is located forms an insulating layer and cures the insulating layer;

(3) Make a second metal layer on the wafer, the overlapping area between the second metal layer and the first metal layer overlaps with the insulating layer, and the insulating layer connects the first metal layer and the second metal layer Achieve isolation.

Further, the photosensitive organic polymer adopts BCB material.

The invention has the following advantages: (1) The area of the invention is significantly reduced, and the area of the organic medium on the entire wafer can be reduced to less than 30% of the original; (2) It is beneficial to reduce the stress of the medium layer and the warpage caused by it , and at the same time prevent cracks or other reliability problems that occur during the tape-out process from spreading to the entire wafer, thereby effectively increasing the yield without increasing the cost.

Description of drawings

Fig. 1 is a structural schematic diagram of the present invention.

Serial numbers in the figure: the first metal layer 101 , the photosensitive BCB layer 102 , the insulating layer 103 , and the second metal layer 104 .

Detailed ways

The present invention will be further described below in conjunction with specific drawings.

As shown in Figure 1: the structure for reducing the warpage of wafer-level integrated passive devices includes a first metal layer 101 and a second metal layer 104 arranged on the wafer, and the second metal layer 104 is located on the first metal layer. The upper layer of one layer of metal layer 101, the second layer of metal layer 104 is a spiral coil structure arranged on the surface of the wafer; one end of the first layer of metal layer 101 is located at the inner circle of the coil of the second layer of metal layer 104, the first The other end of the layer metal layer 101 is positioned at the outer circle of the second layer metal layer 104 coil, so that the first layer metal layer 101 forms a bridge line connecting the inside and outside of the second layer metal layer 104 coil; in the first layer metal layer 101 and An insulating layer 103 is provided in the overlapping area between the second metal layers 104, the insulating layer 103 covers the area where the first metal layer 101 is located, and the insulating layer 103 is used to isolate the overlapped part of the bridge wire and the coil;

The planar shape of the insulating layer 103 is a rectangle with rounded corners, and the use of rounded corners can reduce stress concentration points;

The first metal layer 101 and the second metal layer 104 are connected through vias provided on the wafer.

The manufacturing method for reducing the warping structure of wafer-level integrated passive devices includes the following steps:

(1) Form the first layer of metal layer 101 on the wafer by photolithography and electroplating process, as a bridge line connecting the inside and outside of the inductor coil;

(2) Coat the photosensitive BCB material 102 on the entire wafer, and form a through hole connecting the first metal layer 101 and the second metal layer 104 by photolithography or etching process; and remove the BCB material by exposure and development, and retain The BCB material in the area where the first metal layer 101 is located forms an insulating layer 103, and the BCB material of the insulating layer 103 is cured;

(3) The second metal layer 104 is fabricated on the wafer by photolithography and electroplating process, and the overlapping area between the second metal layer 104 and the first metal layer 101 overlaps with the insulating layer 103, so that the insulating layer 103 will The first metal layer 101 and the second metal layer 104 are isolated, and the first metal layer 101 , the insulating layer 103 and the second metal layer 104 together form a planar coil inductor.

The insulating layer 103 used in the present invention only covers the area where the first metal layer 101 and the second metal layer 104 overlap each other, compared to the method in which the insulating layer of the planar coil inductor in the traditional process covers the entire wafer except the through hole, The area of the present invention is significantly reduced, and the area of the organic medium on the entire wafer can be reduced to less than 30% of the original, which is beneficial to reduce the stress of the medium layer and the warpage caused by it, and at the same time prevent cracks or other defects that occur during the tape-out process. Reliability issues do not spread to the entire wafer, effectively increasing yield without increasing cost.

Claims (5)

1. A structure for reducing warping of wafer-level integrated passive devices, comprising a first metal layer (101) and a second metal layer (104) arranged on the wafer, and the second metal layer (104) Located on the upper layer of the first metal layer (101), the second metal layer (104) is a spiral coil structure arranged on the surface of the wafer; one end of the first metal layer (101) is located on the second metal layer (104) the inner circle of the coil, the other end of the first metal layer (101) is located at the outer circle of the second metal layer (104), the first metal layer (101) forms a connection to the second metal layer (104) ) a bridge wire inside and outside the coil; it is characterized in that: an insulating layer (103) is provided in the overlapping area between the first metal layer (101) and the second metal layer (104), and the insulating layer (103) Covering the area where the first metal layer (101) is located, isolating the overlapping portion of the bridge wire and the coil. 2. The structure for reducing warpage of wafer-level integrated passive devices according to claim 1, characterized in that: the planar shape of the insulating layer (103) is a rounded rectangle. 3. The structure for reducing the warpage of wafer-level integrated passive devices according to claim 1, characterized in that: the first metal layer (101) and the second metal layer (104) are arranged on a circle on-chip through-hole connections. 4. A method for reducing the warpage structure of wafer-level integrated passive devices, characterized in that it comprises the following steps: (1) Fabricate the first metal layer (101) on the wafer as a bridge wire connecting the inside and outside of the inductance coil; (2) Coat the entire wafer with a photosensitive organic polymer (102), and make through holes connecting the first metal layer (101) and the second metal layer (104) through photolithography or etching; remove the photosensitive organic polymer, retaining the photosensitive organic polymer in the region where the first metal layer (101) is located, forming an insulating layer (103), and curing the insulating layer (103); (3) Fabricate the second metal layer (104) on the wafer, the overlapping area between the second metal layer (104) and the first metal layer (101) overlaps with the insulating layer (103), and the insulating layer (103) isolating the first metal layer (101) and the second metal layer (104). 5. The manufacturing method of the wafer-level integrated passive device warpage-reducing structure according to claim 4, characterized in that: the photosensitive organic polymer is made of BCB material.