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CN1043839A - 半导体集成电路 - Google Patents

半导体集成电路 Download PDF

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CN1043839A
CN1043839A CN89109119A CN89109119A CN1043839A CN 1043839 A CN1043839 A CN 1043839A CN 89109119 A CN89109119 A CN 89109119A CN 89109119 A CN89109119 A CN 89109119A CN 1043839 A CN1043839 A CN 1043839A
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circuit
logical
integrated circuit
signal
unit
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CN1022077C (zh
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理查德·朱利·克立弗
肯尼思·奥斯汀
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NXP USA Inc
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Pilkington Micro Electronics Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

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  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Amplifiers (AREA)

Abstract

本发明涉及GBB-2180382中所公开的可构成逻辑电路阵列的半导体集成电路。这种阵列编程可以在其中构成多个“与非”门(G1)来完成各种不同的逻辑功能。本发明特别涉及在各单元处提供一个可由控制装置(GCS)控制的附加逻辑电路(C)，以使逻辑电路和附加逻辑电路(C)完成简单“与非”逻辑功能或简单锁存逻辑功能。

Description

本发明涉及包括有可构成逻辑电路阵列的电子集成电路。
本发明在我们的专利说明书GB    B-2180382中所公开的可构成逻辑电路阵列中特别有用（GB    B-2180382所公开的内容结合在此作为参考）。该说明书中的逻辑电路阵列包括一个分立的地点或单元的矩阵。每一单元处是一个用于完成简单逻辑功能的逻辑电路。通常，简单逻辑功能是由两个输入“与非”门完成的。
这种阵列能被编程以根据需要构成各种“与非”门来完成各种不同的逻辑功能。逻辑功能之一被称为锁存功能。在GB    B-2180382中公开的逻辑阵列中，锁存功能是利用四个“与非”门完成的。
这有一个缺点，即需要逻辑阵列完成的锁存功能越多，则剩下完成其它功能的“与非”门越少。这会减小阵列的总有效性。
本发明的一个目的是通过提供一个附加逻辑电路克服这一缺点。它在每个分立单元处的每个逻辑电路中增加一个附加逻辑电路，使每个单元具有更大的编程能力，从而提高阵列的总利用率。
根据本发明，提供了一种GB    B-2180382权利要求1所提出可构成的半导体集成电路。它如所制成的那样包括一个区域，其中在各分立单元处分别形成有多个逻辑电路，每个逻辑电路具有一个有限的简单逻辑功能的能力，并且只能完成一个简单的逻辑功能，同时还在逻辑电路的输入和输出间形成有一个有限的信号传送系统，承担输入输出间的直接连接通路，每个都可选为导通状态，对每个逻辑电路说这些通路从其输出端延伸至第一组其它逻辑电路的输入端，并从其输入端延伸至第二组其它逻辑电路的输出端，所有组（所有逻辑电路）中，每组都与其它组不同，其不同的特征在于，集成电路还在各分立的组或单元中包括一附加逻辑电路，该附加逻辑电路在组或单元逻辑电路中被配置得使其可由控制装置有选择地控制以使构成单元的逻辑电路和附加逻辑电路能起到第一或第二不同的简单逻辑功能的作用。
附加逻辑电路包括一个倒相器，它与单元中逻辑电路中的一个倒相器并列和以背对背的关系安排着，以作为一个锁存机构、一个第一开关装置和一个第二开关装置工作。
第一开关装置最好是一个包括第一和第二晶体管的传输门，该传输门可被从逻辑电路输入到其中的信号控制为关闭和开启状态，第二开关装置包括一个单一的晶体管，其导通状态由上述控制装置控制。
为方便起见，控制装置由一门控制信号构成，当该信号存在时，引起该单个晶体管处于导通状态，结果使传输门短路而不工作，因而，该单元仅作为“与非”门工作。
当门控制信号不存在时，引起该单个晶体管处于非导通状态，而使传输门被控制于开启和关闭状态，单元仅作为锁存电路工作。
逻辑电路包括一逻辑门电路，其排列使输入信号通过传输门的暂态时间短于同一信号通过逻辑门电路的暂态时间，进而导致传输门关闭和开启状态间的快速转换。
本发明的另一构思是将许多单个单元级联，构成锁存电路功能以形成移位寄存器。
通过参照附图和本发明的一实施范例的说明将会更容易地理解本发明。
附图是两个互连逻辑电路或单元的示意图，根据本发明，每个逻辑电路都包括一个附加逻辑电路。
参看附图，为方便起见，各单元中同样元件将用相同符号表示。所示的两个单元是主锁存单元MC和受控锁存单元SC。
每个单元包括一个基本的两输入“与非”门G1和一个倒相器形成的输出缓冲器I1，以及另一个倒相器I2。参看主单元MC，门G1的一个输入CK将时钟信号从多路转接器MUX1传送到单元，另一输入D将数据信号从另一多路转接器MUX2传送至单元中。
附加逻辑电路C连接在“与非”门G1和输出缓冲器I1之间。通过利用来自比特存贮器BS的控制信号（BS也为多路转接器MUX1和MUX2提供控制信号），使附加逻辑电路将单元的“与非”门功能变为锁存电路功能。
附加逻辑电路包括一个附加倒相器I3，它与I2在现有逻辑电路中并联和具有背对背的关系，并被安排起到锁存机构的作用。另外还包括一个倒相器I4用于将来自单元MC的输入CK的时钟信号变换至单元SC的晶体管T2。
电路中还有两个开关装置，第一开关装置包括两个反极性的晶体管T1和T2，它们并联形成一传输门。第二开关装置是一单个晶体管T3作为一个简单开关。
在运行中，对单元（包括逻辑电路和附加逻辑电路）进行选择以使其作为“与非”门工作或作为锁存器工作，这选择是受门控制信号GCS控制的，这信号GCS是从比特存贮器BS中产生的。当信号GCS存在时，使晶体管T3导通，而开关将使形成传输门的晶体管T1和T2短路，使传输门不工作。
在这种情况下，单元只作为一个“与非”门工作。
另一方面，当GCS信号不存在时，晶体管T3不导通，而晶体T1和T2这时由来自“与非”门G1输出端CK的时钟信号控制。该时钟信号一方面被直接加到晶体管T1，另一方面通过倒相器I4加到晶体管T2，与此同时，门G1自身主要的输出OP加到传输门。这时由传输门（T1+T2）传输的输出OP被由倒相器I2和I3组成的锁存机构有效地锁存。在这种情况下，单元只完成锁存电路的功能。
下表总结了锁存功能的运行及传输门的控制。
表1
CK D OP 传输门（T1 + T2)
1 1 0 关闭
0 0 1 开启
1 0 1 关闭
0 1 0 开启
当输入信号CK处于二进制1的状态并且传输门关闭时，锁存器（I1和I3）跟随输入D上的数据信号变化。然而，为防止在传输门将要开启时，存在锁存器中的信号丢失，送给传输门的信号必须足够快以便在门G1输入端上的信号在锁存器（I2+I3）中起作用前，使开关的状态发生变化。因而，由于把信号传送到传输门的暂态时间比信号通过“与非”门G1自己的暂态时间短，于是就实现了锁存器（I2+I3）的快速转换。在实际应用包括工作于上述锁存模式并进而联接成移位寄存器的若干单元（这样的两级被示为主单元MC和受控单元SC）的本发明时，可以很方便地利用前一单元的倒相器I4的倒相输出作为下一单元的倒相时钟输入。
在这样一种电路配置中，很显然，本领域的技术人员利用多个锁存器级联可形成一个适用的移位寄存器，这样形成的移位寄存器不仅能增加运行速度，而且能更有效地利用阵列本身。

Claims (8)

1、一种可制成的半导体集成电路包括一个区域，该区域是由在各分立单元处的多个逻辑电路分别形成的，每个逻辑电路具有一个有限的简单逻辑功能的能力并只能完成简单逻辑功能，同时该区域还有在逻辑电路的输入和输出间形成一个有限的信号的传送系统，用来承担输入、输出间的直接通路，每一通路当选至其导通状态时，对每个逻辑电路说，这些通路从其输出端延伸至第一组其它逻辑电路的输入端，并从其输入端延伸至第二组其它逻辑电路的输出端，所有的组(所有逻辑电路)中，每组都与其它组不同，此集成电路的特征在于：在各分立单元中还包括一附加逻辑电路(C)，该附加逻辑电路在单元逻辑电路中被配置得使其可由控制装置(GCS)有选择地控制以使构成单元的逻辑电路和附加逻辑电路能执行第一或第二不同的简单逻辑功能。
2、权利要求1的集成电路，其中，附加逻辑电路（C）包括一倒相器（I3），它与单元中的逻辑电路的倒相器（I2）安排为并联和背对背的关系，作为锁存机构，第一开关装置（T1，T2）和第二开关装置（T3）。
3、权利要求2的集成电路，其中第一开关装置（T1，T2）是一个包括第一晶体管（T1）和第二晶体管（T2）的传输门，传输门（T1，T2）可由来自上述逻辑电路的传送给传输门的信号控制关闭和开启。
4、权利要求2或3的集成电路，其中，第二开关装置包括一单一晶体管（T3），其导通状态由上述控制装置（GCS）控制。
5、权利要求4的集成电路，其中，控制装置（GCS）由门控制信号（GCS）构成，当该信号存在时，引起单一晶体管（T3）处于导通状态，并将传输门（T1、T2）短路使其不工作，这样，单元只起“与非”门功能的作用。
6、权利要求4的集成电路，其中，控制装置由门控制信号（GCS）构成，当该信号不存在时，引起单一晶体管（T3）处于非导通状态，使传输门（T1，T2）被控制于开启和关闭的工作状态，这样单元只起锁存功能。
7、权利要求6的集成电路，其中逻辑电路包括一逻辑门电路（G1），上述逻辑门电路（G1）的配置使把输入信号传递到传输门的暂态时间比同一信号通过逻辑门电路（G1）的暂态时间短，进而使传输门在关闭和开启状态之间快速转换。
8、权利要求6或7的集成电路，其中多个构成锁存电路的分立单元，级联成一个移位寄存器。
CN89109119A 1988-12-09 1989-12-08 半导体集成电路 Expired - Fee Related CN1022077C (zh)

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GB888828828A GB8828828D0 (en) 1988-12-09 1988-12-09 Semiconductor integrated circuit
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CA2004778C (en) 2000-04-25
EP0372749A3 (en) 1990-08-01
US5001368A (en) 1991-03-19
EP0372749A2 (en) 1990-06-13
RU2054801C1 (ru) 1996-02-20
KR0130760B1 (ko) 1998-10-01
DE68918413T2 (de) 1995-02-23
CA2004778A1 (en) 1990-06-09
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GB8828828D0 (en) 1989-01-18
ES2064463T3 (es) 1995-02-01
KR900011151A (ko) 1990-07-11
ATE112114T1 (de) 1994-10-15
CN1022077C (zh) 1993-09-08
JPH02185118A (ja) 1990-07-19
EP0372749B1 (en) 1994-09-21
DE68918413D1 (de) 1994-10-27

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