CN103839807A - Trench DMOS transistor manufacturing method and trench DMOS transistor - Google Patents
Trench DMOS transistor manufacturing method and trench DMOS transistor Download PDFInfo
- Publication number
- CN103839807A CN103839807A CN201210473682.9A CN201210473682A CN103839807A CN 103839807 A CN103839807 A CN 103839807A CN 201210473682 A CN201210473682 A CN 201210473682A CN 103839807 A CN103839807 A CN 103839807A
- Authority
- CN
- China
- Prior art keywords
- groove
- layer
- epitaxial wafer
- grid
- carried out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 68
- 230000003064 anti-oxidating effect Effects 0.000 claims abstract description 35
- 230000003647 oxidation Effects 0.000 claims abstract description 22
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 22
- 238000012545 processing Methods 0.000 claims abstract description 9
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 33
- 238000001259 photo etching Methods 0.000 claims description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000005137 deposition process Methods 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 238000010992 reflux Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 115
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 229940090044 injection Drugs 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 238000009834 vaporization Methods 0.000 description 2
- 230000008016 vaporization Effects 0.000 description 2
- -1 wherein Substances 0.000 description 2
- 241000931705 Cicada Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ZEAWTGZZORIFDL-UHFFFAOYSA-N [P].[B].[Si](=O)=O Chemical compound [P].[B].[Si](=O)=O ZEAWTGZZORIFDL-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种沟槽DMOS管的制造方法及一种沟槽DMOS管，所述方法包括：对一用于制造所述沟槽DMOS管的外延片进行处理，形成一与栅极对应的沟槽，并在所述沟槽底部形成第一栅极氧化层；在所述处延片的表面进行淀积处理，形成一抗氧化层；在所述抗氧化层的表面，去除所述沟槽外的所述抗氧化层和所述沟槽底部的所述抗氧化层，以保留所述沟槽内侧壁的所述抗氧化层；在所述沟槽内进行第二次氧化，在所述沟槽底部的第一栅极氧化表面形成第二栅极氧化层。
The invention discloses a method for manufacturing a grooved DMOS transistor and a grooved DMOS transistor. The method includes: processing an epitaxial wafer used to manufacture the grooved DMOS transistor to form a grid corresponding to the grid. trench, and form a first gate oxide layer at the bottom of the trench; perform deposition treatment on the surface of the wafer at the place to form an anti-oxidation layer; on the surface of the anti-oxidation layer, remove the trench The anti-oxidation layer outside the groove and the anti-oxidation layer at the bottom of the groove, so as to retain the anti-oxidation layer on the inner wall of the groove; carry out the second oxidation in the groove, and A second gate oxide layer is formed on the first gate oxide surface at the bottom of the trench.
Description
Technical field
The invention belongs to semiconductor integrated circuit and manufacture field, relate in particular to a kind of manufacture method and a kind of groove DMOS pipe of groove DMOS pipe.
Background technology
In the prior art, the transistor of Metal-oxide-semicondutor (Metal-Oxide-Semiconductor) structure is called for short MOS transistor, and metal-oxide-semiconductor is as the most basic electronic devices and components, generally for various electronic products.
MOS transistor has opening time (ton) and turn-off time (toff) two parameters in application, in the time that opening time and turn-off time are all long, so, the frequency of switch is just very low, like this, the electric weight of consumption is just very large, thereby driving force is just very not strong.
But the inventor realizing in the process of technical scheme in the embodiment of the present invention, finds that prior art at least has following problem:
Due in the prior art, after the channel bottom of metal-oxide-semiconductor is carried out to a gate oxidation, the grid oxic horizon forming is thinner, make the capacitance of metal-oxide-semiconductor larger, thereby the electric weight that grid consumes also can be larger, the electric weight consuming when grid is when larger, and the switching frequency of metal-oxide-semiconductor will be very low, and driving force is not strong.
Summary of the invention
The embodiment of the present invention provides the manufacture method of a kind of groove MOS pipe and metal-oxide-semiconductor, for solving the not high technical problem of prior art metal-oxide-semiconductor switching frequency.
The application provides following technical scheme by the application's a embodiment:
A manufacture method for groove MOS pipe, comprising:
Process for the manufacture of the epitaxial wafer of described groove DMOS pipe one, form a groove corresponding with grid, and form first grid oxide layer at described channel bottom;
Prolong the surface of sheet at described place and carry out deposition process, form an anti oxidation layer;
On the surface of described anti oxidation layer, remove described anti oxidation layer outside described groove and the described anti oxidation layer of described channel bottom, to retain the described anti oxidation layer of described groove madial wall;
In described groove, be oxidized for the second time, form second grid oxide layer at the first grid oxidized surface of described channel bottom.
Further, describedly process for the manufacture of the epitaxial wafer of described groove DMOS pipe one, form a groove corresponding with grid, and form a grid oxic horizon at described channel bottom, specifically comprise:
To described epitaxial wafer pad oxygen oxidation and hard mask deposit;
By the described epitaxial wafer that forms hard mask deposit is carried out to photoetching, hard mask etching, etching groove, forms groove;
Remove the described hard mask illuvium outside described groove;
Be oxidized on described epitaxial wafer surface, form first grid oxide layer.
Further, deposition process is carried out on the described surface at described epitaxial wafer, forms an anti oxidation layer, is specially:
Carry out the processing of deposit silicon nitride on the surface of described epitaxial wafer, described silicon nitride has non-oxidizability.
Further, after the first grid oxidized surface of described channel bottom forms second grid oxide layer, described method also comprises:
Remove the described non-oxidizability layer of described groove madial wall.
Further, after the described non-oxidizability layer of the described groove madial wall of described removal, described method also comprises:
Carry out polycrystalline deposition in treated described epi-layer surface, polycrystalline returns quarter, forms grid;
Photoetching is carried out in described epitaxial wafer first area, and inject the first ion, then described the first ion is carried out to knot dark, form well region;
Described epitaxial wafer second area is carried out to photoetching, and inject the second ion, then described the second ion is carried out to knot dark, form source region.
Further, after described formation source region, described method also comprises:
In the enterprising interline dielectric layer of described epitaxial loayer deposit after treatment, reflux, fairlead photoetching and etching;
By to metal deposit, photoetching and etching, passivation layer photoetching and etching, form passivation layer;
Described epi-layer surface after treatment is carried out to alloy, thinning back side, evaporated metal technique.
On the other hand, the application, by another embodiment of the application, provides following technical scheme:
A kind of groove DMOS pipe, comprising: epitaxial wafer, wherein, epitaxial wafer comprises substrate and groove, forms second grid oxide layer on the first grid oxide layer surface of this channel bottom.
The one or more technical schemes that provide in the embodiment of the present application, at least have following technique effect or advantage:
Due in the embodiment of the present application, adopt after the channel bottom of groove DMOS pipe forms first grid oxide layer, again increase the technical scheme of second grid oxide layer on this first grid oxide layer surface, solve in prior art in the time that the channel bottom of DMOS pipe only has one deck grid oxic horizon, make the not high technical problem of switching frequency of DMOS pipe, realized can high-speed switch groove DMOS pipe technique effect, the driving force of groove DMOS pipe is strengthened.
Brief description of the drawings
Fig. 1 is a kind of flow chart of manufacture method of groove DMOS pipe;
Fig. 2 is a kind of raw material structure figure of groove DMOS pipe;
Fig. 3 is that a kind of raw material of groove DMOS pipe are through the structure chart of the oxidation of pad oxygen and hard mask deposit;
Fig. 4 be a kind of groove DMOS pipe pad oxygen oxide layer and hard mask layer are carried out to the structure chart after photoetching and etching;
Fig. 5 is a kind of structure chart of groove of groove DMOS pipe;
Fig. 6 is a kind of groove DMOS pipe after sacrificing oxidation, forms the structure chart of first grid oxide layer;
Fig. 7 is that a kind of groove DMOS pipe is at the structure chart carrying out after deposition process;
Fig. 8 is that a kind of groove DMOS pipe is carrying out the structure chart after etching to illuvium;
To be a kind of groove DMOS pipe carry out the structure chart after gate oxidation for the second time at channel bottom to Fig. 9;
Figure 10 is that a kind of groove DMOS pipe is removed the structure chart after the illuvium of trenched side-wall.
Embodiment
The embodiment of the present application, by a kind of manufacture method and a kind of groove DMOS pipe of groove DMOS pipe are provided, has solved the not high technical problem of groove DMOS pipe switching frequency in prior art, has reached the technique effect that improves groove DMOS pipe switching frequency.
Technical scheme in the embodiment of the present application is for addressing the above problem, and general thought is as follows:
On epitaxial wafer one for the manufacture of groove DMOS pipe, through the oxidation of pad oxygen and hard mask deposit, and then by trench lithography, hard mask etching, etching groove, sacrifices oxidation, then removes oxide layer again, thereby forms groove figure.After gate oxidation is carried out for the first time in the bottom of this groove, deposit silicon nitride, the silicon nitride of this channel bottom is carried out to dry etching, retain the silicon nitride of trenched side-wall, carry out gate oxidation for the second time, thereby remove the silicon nitride that is retained in groove DMOS pipe sidewall by wet method, like this, just formed grid gate oxide in the bottom of this groove DMOS pipe.Then pass through polycrystalline deposition, polycrystalline returns quarter again, forms grid, and through trap oxidation, photoetching, injects ion, and knot is dark, thereby forms well region, and then through source region photoetching, injects ion, and knot is dark, thereby forms source region.Then in the process middle dielectric layer deposit of epitaxial wafer after treatment surface, reflux, through lead-in wire photoetching and etching, inject ion, annealing, forms fairlead figure, then carry out aluminium lamination sputter, pass through again metal lithographic and etching, form aluminum strip lead-in wire, carry out passivation layer deposit, through passivation layer photoetching and etching, form passivation layer figure, finally complete thinning back side, the technique of evaporated metal.
As shown in Figure 1, the manufacture method of this groove DMOS pipe is specific as follows:
S10, processes for the manufacture of the epitaxial wafer of described groove DMOS pipe one, forms a groove corresponding with grid, and forms first grid oxide layer at this channel bottom.
The concrete steps that form a grid oxic horizon at the channel bottom of groove DMOS pipe are: to described epitaxial wafer pad oxygen oxidation and hard mask deposit; By the described epitaxial wafer that forms hard mask deposit is carried out to photoetching, hard mask etching, etching groove, forms groove; Remove the described hard mask illuvium outside described groove; Be oxidized on described epitaxial wafer surface, form first grid oxide layer.
In concrete implementation process, as shown in Figure 2, described groove DMOS pipe is N-type epitaxial wafer, and resistivity is 0.9ohm.cm, and thickness is about 8um.This N-type epitaxial wafer also includes layer of semiconductor N-type substrate layer.It on this N-type substrate layer, is the monocrystal material of certain ion concentration of having adulterated.
First, this epitaxial wafer is processed, as shown in Figure 3, in this adulterated certain density monocrystal material outer surface pad oxygen oxidation and hard mask deposit, wherein, this pad oxygen oxide layer is silicon dioxide, and the silicon dioxide layer of formation is probably at the thickness of 0.05um, hard mask illuvium is silicon nitride, and this silicon nitride layer is probably at the thickness of 0.32um.
Then, in order to obtain groove, oxide layer and hard mask layer are processed, as shown in Figure 4, first determined the position of etching groove, then at this position, the pad oxygen oxide layer to above-mentioned formation and hard mask layer carry out photoetching, etching, thus expose epitaxial wafer.
The above-mentioned epitaxial wafer exposing is carried out to etching groove, as shown in Figure 5, obtain groove shape.
Then sacrificial oxide layer, as shown in Figure 6, carries out gate oxidation to the epitaxial wafer after sacrificial oxide layer, forms grid oxic horizon, and this grid oxic horizon can be silicon dioxide, and this thickness of grid oxide layer is 0.06um, and this is ground floor grid oxic horizon.Make in flow process in traditional technique, the groove DMOS pipe of formation only has this one deck grid oxic horizon at this channel bottom.
In the execution mode of this programme, after forming ground floor grid oxic horizon, then perform step S20, prolong the surface of sheet at described place and carry out deposition process, form an anti oxidation layer.Wherein, this anti oxidation layer can be silicon nitride layer.Carry out the processing of deposit silicon nitride at this groove and groove outside, the thickness of this silicon nitride layer is about 0.05um.As shown in Figure 7.
Form after anti oxidation layer, execution step S30, on the surface of described anti oxidation layer, removes described anti oxidation layer outside described groove and the described anti oxidation layer of described channel bottom, to retain the described anti oxidation layer of described groove madial wall.As shown in Figure 8.
In concrete implementation process, the method for removing anti oxidation layer comprises, dry method removal oxide layer and wet method removal oxide layer, plasma etching method in addition.Here, we use dry method to remove oxide layer.
In concrete execution mode, this silicon nitride is carried out to dry etching, so-called dry etching utilizes exactly electricity slurry to touch and carves, the effect of etching during electricity slurry touches and carves, can be that electricity slurry intermediate ion clashes into the physical action that wafer surface produces, or the chemical reaction of living radical and wafer surface atom in electricity slurry, can be even also above both composite action, thereby remove the silicon nitride layer of groove outer surface and channel bottom, retained the silicon nitride layer of sidewall.Removing, thickness is thicker, when the larger anti oxidation layer of area coverage, adopts dry method to remove more.Because wet method is only thinner for cladding thickness, the anti oxidation layer that area is again less, and, larger for area coverage, when the anti oxidation layer that thickness is thicker uses wet method to remove, can not completely this anti oxidation layer be got rid of completely.
After removing the anti oxidation layer of channel bottom, execution step S40 is oxidized for the second time in described groove, as shown in Figure 9, forms second grid oxide layer at the first grid oxidized surface of described channel bottom.
So, after having removed anti oxidation layer, then carrying out gate oxidation for the second time at channel bottom, the silicon dioxide layer that this time oxidation forms is about 0.3um.And on the trenched side-wall without oxidation, be coated with non-oxidizability layer, protected sidewall not oxidized.Like this, just make the grid oxic horizon thickening of channel bottom.
Now, through after gate oxidation for the first time and gate oxidation for the second time, just form the grid gate oxide of about 0.35um at the channel bottom of this DMOS pipe, it is thick many that the grid oxic horizon forming compared to traditional handicraft is wanted.
After forming second grid oxide layer, remove the non-oxidizability layer of groove madial wall.As shown in figure 10.
This non-oxidizability layer is the above-mentioned silicon nitride layer of mentioning, and first, can remove by wet method the silicon nitride of trenched side-wall here, and the silicon nitride that so-called wet method is removed trenched side-wall uses chemical solution exactly, reaches the object of etching after after chemical reaction.For example, can corrode with certain density hydrofluoric acid, or hot phosphoric acid.Wet method is removed silicon nitride, can be corroded number of times and controlled by control the degree of corrosion, is to remove completely, or need to retain a part of anti oxidation layer, or by controlling the time of solution corrosion, the time is suitable, this anti oxidation layer can be removed completely, also do not affected product quality.Certainly, the concentration of etchant solution be can also pass through to control, thereby degree and the speed of removing anti oxidation layer controlled.Thereby meet the quality of product.Through after above-mentioned processing, can carry out follow-up technique.
After getting rid of the unnecessary anti oxidation layer that is attached to trenched side-wall, the manufacture method of this groove DMOS pipe also comprises: carry out polycrystalline deposition in treated epi-layer surface, polycrystalline returns quarter, forms grid; Photoetching is carried out in epitaxial wafer first area, and inject the first ion, then the first ion is carried out to knot dark, form well region; Epitaxial wafer second area is carried out to photoetching, and inject the second ion, then the second ion is carried out to knot dark, form source region.
In concrete implementation process, carry out polycrystalline deposition, wherein, polycrystalline refers to the deposit of polysilicon, first depositing polysilicon processing on epitaxial wafer after treatment, this deposition process is filled up the groove of above-mentioned formation, and the polysilicon layer of this deposit need to exceed the height of the about 1.2um of epitaxial wafer outer surface.
Then, this polysilicon layer is returned to quarter, the polysilicon layer that exposes groove outer surface is got rid of.Polysilicon is returned to the method at quarter, normally with sulphur hexafluoride, chlorine, oxygen and helium, polysilicon is carried out to etching, after entering such processing, then carry out etching with hydrogen bromide, chlorine and oxygen, ensure the clean stable of etching process, also improved the utilance of equipment simultaneously.Carve through returning of polysilicon, thereby obtain grid.
Then, treated this epitaxial wafer is carried out to trap oxidation.First, at epi-layer surface resist coating, photoetching is carried out in subregion, inject ion, this ion can be boron ion, and it adds energy can be 180 kilo electron volts.Wherein, be in order to form terminal P ring in the effect of well region photoetching, and the effect of terminal is high pressure resistant, for example, in the time that drain electrode adds high voltage, PN junction can be reverse-biased, and due to the expansion of space charge region, PN junction curvature is larger, makes electric field more concentrated, easily breakdown.So, if there is the formation of terminal P ring, just effectively alleviated the curvature of PN junction, thereby effectively improved the voltage endurance capability of terminal.Because be spreads p type island region on N-type substrate, so formed P well region.In P well region, ion is carried out to knot dark, namely the ion of above-mentioned injection is pushed away deeply, make ion concentration thin out.If ion is not pushed away deeply, the cut-in voltage of the DMOS pipe that this manufacture produces will be very large, just device is difficult for opening in the time opening.
Then, carry out, after photoetching, carrying out arsenic ion injection in another region of epitaxial wafer, the arsenic ion energy of injection can be 80 kilo electron volts, the arsenic ion injecting is carried out to knot equally dark, thereby has formed source region.
Because DMOS pipe also comprises drain electrode, wherein, N-type substrate just belongs to drain electrode.At above-mentioned grid, source region, after well region is all determined, the manufacture method of this groove DMOS pipe also comprises: in the enterprising interline dielectric layer of described epitaxial loayer deposit after treatment, reflux, fairlead photoetching and etching; By to metal deposit, photoetching and etching, passivation layer photoetching and etching, form passivation layer; Described epi-layer surface after treatment is carried out to alloy, thinning back side, evaporated metal technique.
In concrete execution mode, middle dielectric layer deposit refers to the inter-level dielectric of the boron phosphorus silicon dioxide that adulterated, and the thickness of this interlayer dielectric layer is 0.45um.Wherein, this middle dielectric layer is made up of two parts, wherein, the plain silicon dioxide layer of Part I, thickness can be 0.2um; Part II is the silicon dioxide layer of boron-doping phosphorus, and thickness can be 0.45um.Then this dielectric layer is carried out to reflow treatment.Then carry out fairlead photoetching and etching, thereby at this fairlead place B Implanted ion, energy can be 60 kilo electron volts, the object of this B Implanted ion is in order to reduce contact resistance, and circuit is very sensitive to the variation of contact resistance, wherein, the contact resistance of switch is the maximum of the contact resistance allowing in the contact of the several times of switch.Then the result of this processing is carried out to rapid thermal treatment, wherein, this heat treated temperature may be controlled to 1050 degrees Celsius, and can continue 30 seconds.
After Overheating Treatment, carry out metal deposit, namely make metal level, the manufacture method of metal level has several like this, for example, evaporation, by controlling the temperature of host material and the pressure of vaporization chamber, makes to want the material vaporization of deposit, when freeing while condensing again, just form evaporating film, such as, conducting film is exactly aluminium film; Sputtering method, uses high-energy ion bombardment sputter material, clashes into micel, and the surface that these micels are attracted to substrate forms film; Galvanoplastic, are used for thickening metal, form the metal level of the above thickness of 1um.In the embodiment of the present application, use sputtering method to form titanium layer and titanium nitride layer, wherein, titanium layer thickness can be 0.03um, and titanium nitride layer thickness can be also 0.03um, then proceeds heat treatment, now, heat treated temperature is controlled at 800 degrees Celsius, and time control is 20 seconds.Then carry out aluminium lamination sputter, the metallic aluminium layer thickness of formation can be 3um.
After metal level forms, through lead-in wire photoetching and etching, thereby form aluminum strip lead-in wire.Then carry out passivation layer deposit.This passivation layer comprises silicon dioxide layer and silicon nitride layer, and wherein, silicon dioxide layer thickness can be 0.6um, and the thickness of silicon nitride can be 0.3um.The passivation layer of this formation is carried out to photoetching and etching, thereby form passivation layer figure.
Further, also need through alloy technique, thinning back side, the processing of evaporation back metal, wherein, in alloy technique, temperature is controlled at 450 degrees Celsius, and the time is controlled at 30 minutes; In technique for thinning back side, need to be retained in the thickness of about 250um; Evaporation back metal makes the thickness of titanium layer can be at 0.1um, and the thickness of nickel dam can be at 0.1um, and the thickness of silver layer can be 1um.
Finally, also need the test through parameter, thereby completed the manufacture to DMOS pipe.
Based on same inventive concept, another embodiment of the application provides a kind of groove DMOS pipe, comprise, and epitaxial wafer, wherein, this epitaxial wafer comprises substrate and groove; First grid oxide layer surface at this channel bottom forms second grid oxide layer.
In concrete execution mode, after obtaining first grid oxide layer, by carrying out the deposit of silicon nitride on first grid oxide layer surface, remove again and be positioned at the silicon nitride layer of channel bottom and be positioned at the silicon nitride layer outside groove, again channel bottom is carried out to gate oxidation, thereby obtain grid gate oxide.Compared to the channel bottom in traditional DMOS pipe, it is thick a lot of that the channel bottom of the groove DMOS pipe in this programme is wanted.Thereby make the capacitance of this groove DMOS pipe less, need the electric weight of consumption also just less, make the frequency of switch higher.
The groove DMOS pipe of introducing due to the present embodiment is the product of a kind of manufacture method of groove DMOS in another embodiment of the application; so; based on the manufacture method of groove DMOS pipe in another embodiment; described in this area, technical staff can understand detailed structure and the concrete deformation of the groove DMOS pipe that the manufacture method of the groove DMOS pipe adopting in the embodiment of the present application obtains; so introduce no longer in detail at this; as long as the groove DMOS pipe that described in this area, technical staff obtains by said method, all belongs to the scope that the application institute wish is protected.
One or more technical schemes that the application provides, at least have following technique effect or advantage:
Due in the embodiment of the present application, adopt after the channel bottom of groove DMOS pipe forms first grid oxide layer, again increase the technical scheme of second grid oxide layer on this first grid oxide layer surface, solve in prior art in the time that the channel bottom of DMOS pipe only has one deck grid oxic horizon, make the not high technical problem of switching frequency of DMOS pipe, realized can high-speed switch groove DMOS pipe technique effect, the driving force of groove DMOS pipe is strengthened.
Although described the preferred embodiments of the present invention, once those skilled in the art obtain the basic creative concept of cicada, can make other change and amendment to these embodiment.So claims are intended to be interpreted as comprising preferred embodiment and fall into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (7)
1. a manufacture method for groove DMOS pipe, is characterized in that, described method comprises:
Process for the manufacture of the epitaxial wafer of described groove DMOS pipe one, form a groove corresponding with grid, and form first grid oxide layer at described channel bottom;
Prolong the surface of sheet at described place and carry out deposition process, form an anti oxidation layer;
On the surface of described anti oxidation layer, remove described anti oxidation layer outside described groove and the described anti oxidation layer of described channel bottom, to retain the described anti oxidation layer of described groove madial wall;
In described groove, be oxidized for the second time, form second grid oxide layer at the first grid oxidized surface of described channel bottom.
2. the method for claim 1, is characterized in that, describedly processes for the manufacture of the epitaxial wafer of described groove DMOS pipe one, forms a groove corresponding with grid, and in described channel bottom formation first grid oxide layer, specifically comprises:
To described epitaxial wafer pad oxygen oxidation and hard mask deposit;
By the described epitaxial wafer that forms hard mask deposit is carried out to photoetching, hard mask etching, etching groove, forms groove;
Remove the described hard mask illuvium outside described groove;
Be oxidized on described epitaxial wafer surface, form first grid oxide layer.
3. the method for claim 1, is characterized in that, deposition process is carried out on the described surface at described epitaxial wafer, forms an anti oxidation layer, is specially:
Carry out the processing of deposit silicon nitride on the surface of described epitaxial wafer, described silicon nitride has non-oxidizability.
4. the method for claim 1, is characterized in that, after the first grid oxidized surface of described channel bottom forms second grid oxide layer, described method also comprises:
Remove the described non-oxidizability layer of described groove madial wall.
5. method as claimed in claim 4, is characterized in that, after the described non-oxidizability layer of the described groove madial wall of described removal, described method also comprises:
Carry out polycrystalline deposition in treated described epi-layer surface, polycrystalline returns quarter, forms grid;
Photoetching is carried out in described epitaxial wafer first area, and inject the first ion, then described the first ion is carried out to knot dark, form well region;
Described epitaxial wafer second area is carried out to photoetching, and inject the second ion, then described the second ion is carried out to knot dark, form source region.
6. method as claimed in claim 5, is characterized in that, after described formation source region, described method also comprises:
In the enterprising interline dielectric layer of described epitaxial loayer deposit after treatment, reflux, fairlead photoetching and etching;
By to metal deposit, photoetching and etching, passivation layer photoetching and etching, form passivation layer;
Described epi-layer surface after treatment is carried out to alloy, thinning back side, evaporated metal technique.
7. a groove DMOS pipe, is characterized in that, comprising:
Epitaxial wafer, wherein, described epitaxial wafer comprises substrate and groove;
First grid oxide layer surface at described channel bottom forms second grid oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210473682.9A CN103839807A (en) | 2012-11-20 | 2012-11-20 | Trench DMOS transistor manufacturing method and trench DMOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210473682.9A CN103839807A (en) | 2012-11-20 | 2012-11-20 | Trench DMOS transistor manufacturing method and trench DMOS transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103839807A true CN103839807A (en) | 2014-06-04 |
Family
ID=50803194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210473682.9A Pending CN103839807A (en) | 2012-11-20 | 2012-11-20 | Trench DMOS transistor manufacturing method and trench DMOS transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103839807A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336785A (en) * | 2014-08-15 | 2016-02-17 | 北大方正集团有限公司 | Depletion-type VDMOS device and manufacturing method therefor |
| CN105448733A (en) * | 2014-09-02 | 2016-03-30 | 北大方正集团有限公司 | Depletion type VDMOS device and manufacturing method thereof |
| CN113496880A (en) * | 2020-04-01 | 2021-10-12 | 成都蓉矽半导体有限公司 | Method for thickening bottom oxide layer of silicon carbide substrate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100029083A1 (en) * | 2005-06-24 | 2010-02-04 | John Tracey Andrews | Method for Forming Laterally Extending Dielectric Layer in a Trench-Gate FET |
| CN101834142A (en) * | 2010-05-21 | 2010-09-15 | 香港商莫斯飞特半导体有限公司 | A kind of trench with thick insulating bottom and its semiconductor device manufacturing method |
| CN101866849A (en) * | 2009-04-16 | 2010-10-20 | 上海华虹Nec电子有限公司 | Method for preparing oxide film at bottom of trench |
| JP2012169421A (en) * | 2011-02-14 | 2012-09-06 | Semiconductor Components Industries Llc | Semiconductor device and manufacturing method of the same |
-
2012
- 2012-11-20 CN CN201210473682.9A patent/CN103839807A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100029083A1 (en) * | 2005-06-24 | 2010-02-04 | John Tracey Andrews | Method for Forming Laterally Extending Dielectric Layer in a Trench-Gate FET |
| CN101866849A (en) * | 2009-04-16 | 2010-10-20 | 上海华虹Nec电子有限公司 | Method for preparing oxide film at bottom of trench |
| CN101834142A (en) * | 2010-05-21 | 2010-09-15 | 香港商莫斯飞特半导体有限公司 | A kind of trench with thick insulating bottom and its semiconductor device manufacturing method |
| JP2012169421A (en) * | 2011-02-14 | 2012-09-06 | Semiconductor Components Industries Llc | Semiconductor device and manufacturing method of the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336785A (en) * | 2014-08-15 | 2016-02-17 | 北大方正集团有限公司 | Depletion-type VDMOS device and manufacturing method therefor |
| CN105448733A (en) * | 2014-09-02 | 2016-03-30 | 北大方正集团有限公司 | Depletion type VDMOS device and manufacturing method thereof |
| CN113496880A (en) * | 2020-04-01 | 2021-10-12 | 成都蓉矽半导体有限公司 | Method for thickening bottom oxide layer of silicon carbide substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI632608B (en) | Local semiconductor wafer thinning | |
| TWI631725B (en) | Method for depositing an emitter layer of a solar cell | |
| CN101315893A (en) | Method for implementing groove type double-layer grid power MOS structure | |
| CN109755322A (en) | Silicon carbide MOSFET device and preparation method thereof | |
| CN101290879A (en) | Manufacturing method of gate | |
| CN103839807A (en) | Trench DMOS transistor manufacturing method and trench DMOS transistor | |
| CN101246886B (en) | MOS structure power transistor and manufacturing method thereof | |
| CN104966697B (en) | TFT substrate structure and preparation method thereof | |
| CN115410921B (en) | AOT field effect tube preparation method and AOT field effect tube | |
| CN102543716B (en) | The forming method of blocking layer of metal silicide | |
| CN101483153B (en) | Semi-conductor device manufacturing process capable of being optimized | |
| CN113224135B (en) | A shielded gate MOSFET device with high avalanche resistance and a manufacturing method thereof | |
| JP2010283306A5 (en) | ||
| US10026822B2 (en) | Fabrication of nanoscale vacuum grid and electrode structure with high aspect ratio dielectric spacers between the grid and electrode | |
| CN112133750B (en) | Deep trench power device and preparation method thereof | |
| US9219148B2 (en) | Semiconductor device and fabricating method thereof | |
| US9252241B2 (en) | Self-aligned thin film transistor and fabrication method thereof | |
| KR20110018510A (en) | Semiconductor device and manufacturing method thereof | |
| JP2011096788A (en) | Method of manufacturing semiconductor device | |
| CN102479713B (en) | MOSFET manufacture method and MOSFET | |
| EP2486592A1 (en) | Improved trench termination structure | |
| CN115064597B (en) | Thin-film transistors and their fabrication methods, display panels | |
| CN112530867A (en) | Groove type field effect transistor structure and preparation method thereof | |
| CN107359121B (en) | Preparation method of VDMOS power device and VDMOS power device | |
| CN118231450B (en) | Manufacturing method of MOSFET device terminal voltage-resistant design structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140604 |
|
| RJ01 | Rejection of invention patent application after publication |