CN101483153B - Semi-conductor device manufacturing process capable of being optimized - Google Patents
Semi-conductor device manufacturing process capable of being optimized Download PDFInfo
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- CN101483153B CN101483153B CN2008100323445A CN200810032344A CN101483153B CN 101483153 B CN101483153 B CN 101483153B CN 2008100323445 A CN2008100323445 A CN 2008100323445A CN 200810032344 A CN200810032344 A CN 200810032344A CN 101483153 B CN101483153 B CN 101483153B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- 238000005516 engineering process Methods 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 238000006243 chemical reaction Methods 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 57
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 57
- 230000000903 blocking effect Effects 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 8
- 239000011259 mixed solution Substances 0.000 claims description 8
- 229910017052 cobalt Inorganic materials 0.000 claims description 7
- 239000010941 cobalt Substances 0.000 claims description 7
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 5
- 238000001459 lithography Methods 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 4
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 claims description 4
- NICDRCVJGXLKSF-UHFFFAOYSA-N nitric acid;trihydrochloride Chemical compound Cl.Cl.Cl.O[N+]([O-])=O NICDRCVJGXLKSF-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000002265 prevention Effects 0.000 abstract 2
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 241000208340 Araliaceae Species 0.000 description 8
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 8
- 235000003140 Panax quinquefolius Nutrition 0.000 description 8
- 235000008434 ginseng Nutrition 0.000 description 8
- 238000002955 isolation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a semiconductor device manufacture method capable of optimizing the technology. The semiconductor device has a Metal-Oxide-Semiconductor (MOS) tube and a resistance made on a silicification metal zone and a silicification metal prevention zone. In the prior art a silicification metal prevention layer is formed on the zone after a side wall medium layer of the silicification metal zone is etched, thereby the process steps are complex, a silicon and oxide consumptions are increased and an electrical leakage of the semiconductor device is increased. The invention firstly manufactures a gate oxide and a polycrystalline silicon layer, removes the gate oxide and the polycrystalline silicon layer outside a gate zone and a resistance zone and dopes the resistance zone, then deposits the side wall medium layer and coats a photo resist and photoetches into the silicification metal zone; subsequently forms the gate side wall through a wet etching process; then removes the photo resist and performs the ion injection process; and deposit the metal layer and performs heat treatment; finally removes the metal layer of a silicification reaction layer. The invention greatly optimizes the process and reduces the electrical leakage of the semiconductor device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of method, semi-conductor device manufacturing method of optimizing technology.
Background technology
In the deep-submicron field of semiconductor manufacture, for reducing the contact resistance of metal-oxide-semiconductor grid source-drain electrode, the existing self-aligned silicide technology (Salicide Process) that adopts usually forms metal silicide simultaneously on metal-oxide-semiconductor grid source-drain electrode.
Except that direct manufacturing metal-oxide-semiconductor, common also direct manufacturing resistance below has the manufacture process of the semiconductor device of metal-oxide-semiconductor and resistance with detailed description on the silicon substrate of semiconductor device: at first manufacturing gate oxide layers and polysilicon layer on silicon substrate; Remove gate regions and outer gate oxide and the polysilicon layer of resistance area through etching technics then; Then resistance area is mixed; Deposit side wall medium layer afterwards and form side wall at grid and resistance both sides through dry etch process; Then cvd silicon oxide also forms the metal silicide blocking layer through photoetching and etching technics at metal silicide blocking area; Get final product similarly metal level and heat-treating such as titanium deposition, nickel and cobalt subsequently; This moment, not have metal silicide blocking layer region covered be to form metal silicide on the metal-oxide-semiconductor grid source-drain electrode, and after this mixed solution of the mixed solution through chloroazotic acid or ammoniacal liquor, hydrogen peroxide solution and water or sulfuric acid and hydrogen peroxide solution removes the metal level of not silication again.
But; Above-mentioned manufacturing process with semiconductor device of metal-oxide-semiconductor and resistance at first exists the waste of material and technology; Behind the side wall medium of the stoped metal of etching metal silicide blocking area and silicon silicided reaction, form metal silicide blocking layer (being oxide layer) in this district's deposition and through photoetching and etching technics again; Repeatedly make the consumption that oxide layer can increase silicon and oxide (comprising fleet plough groove isolation structure and grid curb wall) in addition, the electric leakage that so can increase semiconductor device.
Therefore, how to provide a kind of method, semi-conductor device manufacturing method of optimizing technology, and reduce the consumption of silicon and oxide, and reduce the electric leakage of semiconductor device, become the technical problem that industry needs to be resolved hurrily with the optimization processing step.
Summary of the invention
The object of the present invention is to provide a kind of method, semi-conductor device manufacturing method of optimizing technology, can optimize manufacturing process, reduce the consumption of silicon and oxide, and reduce the electric leakage of semiconductor device through said manufacturing approach.
The objective of the invention is to realize like this: a kind of method, semi-conductor device manufacturing method of optimizing technology; It is manufactured on the silicon substrate and has metal-oxide-semiconductor and resistance; This metal-oxide-semiconductor and resistance are produced in metal silicide district and metal silicide blocking area, and this method may further comprise the steps: a, manufacturing gate oxide layers and polysilicon layer on silicon substrate; B, remove gate regions and outer gate oxide and the polysilicon layer of resistance area through etching technics; C, resistance area is mixed; D, deposition side wall medium layer; E, be coated with photoresist and make the metal silicide district by lithography; F, form grid curb wall through dry etch process; G, remove photoresist and carry out the source and leak ion implantation technology; H, depositing metal layers are also heat-treated with the grid source-drain electrode formation metal silicide at metal-oxide-semiconductor; I, remove the not metal level of silicification reaction through wet-etching technology.
In the method, semi-conductor device manufacturing method of the above-mentioned technology optimized, this metal level is titanium layer, nickel dam or cobalt layer, and correspondingly this metal silicide is titanium silicide, nickle silicide or cobalt silicide.
In the method, semi-conductor device manufacturing method of the above-mentioned technology optimized, this side wall medium layer is silicon oxide layer or silicon nitride layer.
In the method, semi-conductor device manufacturing method of the above-mentioned technology optimized, in step h, this heat treatment comprises phase I heat treatment and second stage heat treatment, and the temperature range of this first and second phase heat treatment is respectively 450 to 550 and 700 to 850 degrees centigrade.
In the method, semi-conductor device manufacturing method of the above-mentioned technology optimized, in step h, through the sputter coating process depositing metal layers.
In the method, semi-conductor device manufacturing method of the above-mentioned technology optimized, in step I, the etching liquid of this wet-etching technology is a chloroazotic acid.
In the method, semi-conductor device manufacturing method of the above-mentioned technology optimized, in step I, the etching liquid of this wet-etching technology is the mixed solution of ammoniacal liquor, hydrogen peroxide solution and water or the mixed solution of sulfuric acid and hydrogen peroxide solution.
With also form the metal silicide blocking layer after the side wall medium layer of etching metal silicide blocking area in the prior art in this district; Thereby cause processing step loaded down with trivial details; And the consumption that has increased silicon and oxide is compared; The method, semi-conductor device manufacturing method of optimizing technology of the present invention is when to be the metal-oxide-semiconductor manufacturing district in the metal silicide district through etching technics form grid curb wall; The side wall medium layer of metal silicide blocking area is protected through photoresist, and this side wall medium layer that is protected can be avoided follow-up and also form metal silicide on this metal silicide blocking area when on leak in metal-oxide-semiconductor grid source, forming metal silicide, so will optimize technology significantly; Reduce the consumption of silicon and oxide, can reduce the electric leakage of semiconductor device in addition greatly.
Description of drawings
The method, semi-conductor device manufacturing method of optimizing technology of the present invention is provided by following embodiment and accompanying drawing.
Fig. 1 is a flow chart of optimizing the method, semi-conductor device manufacturing method of technology of the present invention;
Fig. 2 to Figure 10 is for accomplishing among Fig. 1 the cutaway view of semiconductor device behind the step S10 to S18.
Embodiment
Below will do further to describe in detail to the method, semi-conductor device manufacturing method of optimizing technology of the present invention.
Semiconductor device described in the method, semi-conductor device manufacturing method of optimizing technology of the present invention is manufactured on the silicon substrate and has metal-oxide-semiconductor and resistance, and said metal-oxide-semiconductor and resistance are produced in metal silicide district and metal silicide blocking area.
Referring to Fig. 1, the method, semi-conductor device manufacturing method of optimizing technology of the present invention at first carries out step S10, manufacturing gate oxide layers and polysilicon layer on silicon substrate.In the present embodiment, respectively through thermal oxidation technology and chemical vapor deposition method manufacturing gate oxide layers and polysilicon layer.
Referring to Fig. 2; The cutaway view that has shown semiconductor device behind the completing steps S10; As shown in the figure; Have a plurality of fleet plough groove isolation structures 10 and conductive well 11 in the silicon substrate 1, gate oxide 12 stacks gradually on silicon substrate 1 with polysilicon layer 13, and metal-oxide-semiconductor that semiconductor device had and resistance are produced on metal silicide district SA and the metal silicide blocking area SAB.
Then continue step S11, remove gate regions and outer gate oxide and the polysilicon layer of resistance area through etching technics.
Referring to Fig. 3, in conjunction with ginseng Fig. 2, Fig. 3 has shown the cutaway view of semiconductor device behind the completing steps S11, and is as shown in the figure, and step S11 has formed grid 14 and resistance 15.
Then continue step S12; Resistance area is mixed; Its detailed process is: at first be coated with photoresist and make the figure of resistance by lithography, carry out ion implantation technology afterwards, confirm the implanted dopant and the implantation dosage of ion implantation technology in this expection resistance according to resistance.
Referring to Fig. 4, in conjunction with ginseng Fig. 2 and Fig. 3, Fig. 4 has shown the cutaway view of semiconductor device behind the completing steps S12, and is as shown in the figure, and through the ion implantation technology impurity that in resistance 15, mixed, the resistance of resistance 15 can reach the expection resistance.
Then continue step S13, the deposition side wall medium layer, said side wall medium layer is silicon oxide layer or silicon nitride layer.In the present embodiment, said side wall medium layer is a silicon oxide layer, and its thickness range is 100 to 500 dusts.
Referring to Fig. 5, in conjunction with ginseng Fig. 2 and Fig. 4, Fig. 5 has shown the cutaway view of semiconductor device behind the completing steps S13, and as shown in the figure, side wall medium layer 16 is deposited on the silicon substrate 1 and cover gate 14 and resistance 15.
Then continue step S14, the coating photoresist also makes the metal silicide district by lithography.In the present embodiment, also made fleet plough groove isolation structure between metal silicide district and metal silicide blocking area by lithography near half zone in metal silicide district.
Referring to Fig. 6; In conjunction with ginseng Fig. 2 and Fig. 5; Fig. 6 has shown the cutaway view of semiconductor device behind the completing steps S14; As shown in the figure, said photoresist 2 covers on the metal silicide blocking area SAB, and has covered fleet plough groove isolation structure 10 between metal silicide district SA and metal silicide blocking area SAB near half zone of metal silicide blocking area SAB.
Then continue step S15, form grid curb wall through dry etch process.
Referring to Fig. 7, in conjunction with ginseng Fig. 2 and Fig. 6, Fig. 7 has shown the cutaway view of semiconductor device behind the completing steps S15, and as shown in the figure, grid curb wall 17 is formed on grid 14 both sides.
Then continue step S16, remove photoresist and carry out the source and leak ion implantation technology.
Referring to Fig. 8, in conjunction with ginseng Fig. 2 and Fig. 7, Fig. 8 has shown the cutaway view of semiconductor device behind the completing steps S16, and as shown in the figure, source electrode 18 is formed in the silicon substrate 1 with drain electrode 19, and lays respectively at grid curb wall 17 both sides.
Then continue step S17; Depositing metal layers is also heat-treated with the grid source-drain electrode formation metal silicide at metal-oxide-semiconductor; Wherein, said metal level is titanium layer, nickel dam or cobalt layer, and it forms through sputter coating process; Said heat treatment comprises phase I heat treatment and second stage heat treatment, and said metal silicide is titanium silicide, nickle silicide or cobalt silicide.In the present embodiment, said metal level is a nickel dam, and said metal silicide is a nickle silicide, and the temperature range of said first and second phase heat treatment is respectively 450 to 550 and 700 to 850 degrees centigrade.
Referring to Fig. 9; In conjunction with ginseng Fig. 2 and Fig. 8; Fig. 9 has shown the cutaway view of semiconductor device behind the completing steps S17; As shown in the figure, metal level 30 covers on the silicon substrate 1, and is grid 14, source electrode 18 and drains and generate metal silicide 31 with silicon generation silicification reaction on 19 in no side wall medium layer 16 or grid curb wall 17 region covered.
Then continue step S18, remove the not metal level of silicification reaction through wet-etching technology, the etching liquid of said wet-etching technology is the mixed solution of chloroazotic acid or ammoniacal liquor, hydrogen peroxide solution and water or the mixed solution of sulfuric acid and hydrogen peroxide solution.
Referring to Figure 10; In conjunction with ginseng Fig. 2 and Fig. 9, Figure 10 has shown the cutaway view of semiconductor device behind the completing steps S18, and is as shown in the figure; Remove grid 14, source electrode 18 and the metal silicide 31 on 19 of draining, other regional metal level 30 is all removed by wet-etching technology fully.
In sum; The method, semi-conductor device manufacturing method of optimizing technology of the present invention is when to be the metal-oxide-semiconductor manufacturing district in the metal silicide district through etching technics form grid curb wall; The side wall medium layer of metal silicide blocking area is protected through photoresist; The said side wall medium layer that is protected can be avoided follow-up and also form metal silicide on the said metal silicide blocking area when on leak in metal-oxide-semiconductor grid source, forming metal silicide; So will optimize technology significantly, reduce the consumption of silicon and oxide, can reduce the electric leakage of semiconductor device in addition greatly.
Claims (9)
1. the method, semi-conductor device manufacturing method that can optimize technology; It is manufactured on the silicon substrate and has metal-oxide-semiconductor and resistance; This metal-oxide-semiconductor and resistance are produced in metal silicide district and metal silicide blocking area, and this method may further comprise the steps: a, manufacturing gate oxide layers and polysilicon layer on silicon substrate; B, remove gate regions and outer gate oxide and the polysilicon layer of resistance area, form grid and resistance through etching technics; C, resistance area is mixed; D, deposition side wall medium layer; It is characterized in that this method is further comprising the steps of after steps d: e, coating photoresist also make the metal silicide district by lithography at the metal-oxide-semiconductor manufacturing district, make photoresist cover on the metal silicide blocking area; F, form grid curb wall in the both sides of grid through the metal silicide district being carried out dry etch process; Photoresist on g, the removal metal silicide blocking area also carries out source leakage ion implantation technology; H, depositing metal layers are also heat-treated with the grid source-drain electrode formation metal silicide at metal-oxide-semiconductor; I, remove the not metal level of silicification reaction through wet-etching technology.
2. the method, semi-conductor device manufacturing method of optimizing technology as claimed in claim 1 is characterized in that, this metal level is titanium layer, nickel dam or cobalt layer, and correspondingly this metal silicide is titanium silicide, nickle silicide or cobalt silicide.
3. the method, semi-conductor device manufacturing method of optimizing technology as claimed in claim 1 is characterized in that, this side wall medium layer is silicon oxide layer or silicon nitride layer.
4. the method, semi-conductor device manufacturing method of optimizing technology as claimed in claim 1 is characterized in that, in step h, this heat treatment comprises phase I heat treatment and second stage heat treatment.
5. the method, semi-conductor device manufacturing method of optimizing technology as claimed in claim 4 is characterized in that, heat treated temperature range of this phase I is 450 to 550 degrees centigrade.
6. the method, semi-conductor device manufacturing method of optimizing technology as claimed in claim 4 is characterized in that, the heat treated temperature range of this second stage is 700 to 850 degrees centigrade.
7. the method, semi-conductor device manufacturing method of optimizing technology as claimed in claim 1 is characterized in that, in step h, through the sputter coating process depositing metal layers.
8. the method, semi-conductor device manufacturing method of optimizing technology as claimed in claim 1 is characterized in that, in step I, the etching liquid of this wet-etching technology is a chloroazotic acid.
9. the method, semi-conductor device manufacturing method of optimizing technology as claimed in claim 1 is characterized in that, in step I, the etching liquid of this wet-etching technology is the mixed solution of ammoniacal liquor, hydrogen peroxide solution and water or the mixed solution of sulfuric acid and hydrogen peroxide solution.
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102087998B (en) * | 2009-12-04 | 2014-03-19 | 无锡华润上华半导体有限公司 | Dual polycrystalline structure device and manufacturing method thereof |
| CN102222599B (en) * | 2010-04-13 | 2013-03-27 | 中芯国际集成电路制造(上海)有限公司 | Method and device for optimizing technological process |
| CN104347373B (en) * | 2013-07-30 | 2018-03-13 | 北大方正集团有限公司 | The manufacture method of lateral double-diffused metal-oxide-semiconductor transistor |
| CN104183482B (en) * | 2014-07-24 | 2017-10-27 | 上海华力微电子有限公司 | Increase the method that wet method removes the process window of unreacted nickel Platinum Silicide |
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| CN1725490A (en) * | 2004-07-22 | 2006-01-25 | 松下电器产业株式会社 | Semiconductor device and manufacturing method thereof |
| CN1815715A (en) * | 2005-02-04 | 2006-08-09 | 富士通株式会社 | Manufacturing method of semiconductor device |
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| CN1725490A (en) * | 2004-07-22 | 2006-01-25 | 松下电器产业株式会社 | Semiconductor device and manufacturing method thereof |
| CN1815715A (en) * | 2005-02-04 | 2006-08-09 | 富士通株式会社 | Manufacturing method of semiconductor device |
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