CN101866849A - Method for preparing oxide film at bottom of trench - Google Patents
Method for preparing oxide film at bottom of trench Download PDFInfo
- Publication number
- CN101866849A CN101866849A CN200910057075A CN200910057075A CN101866849A CN 101866849 A CN101866849 A CN 101866849A CN 200910057075 A CN200910057075 A CN 200910057075A CN 200910057075 A CN200910057075 A CN 200910057075A CN 101866849 A CN101866849 A CN 101866849A
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- silicon nitride
- oxide
- film
- trench
- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 39
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- 238000005516 engineering process Methods 0.000 claims description 18
- 238000006396 nitration reaction Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims 1
- 230000007797 corrosion Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 210000003323 beak Anatomy 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 2
- 102000013275 Somatomedins Human genes 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 239000012148 binding buffer Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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Abstract
The invention discloses a method for preparing an oxide film at the bottom of a trench. The method comprises the following steps of: after the trench is etched on a substrate, 1) growing a gasket oxide film in the trench; 2) depositing silicon nitride on the whole substrate to ensure that silicon nitride layers are deposited on both the upper surface of the substrate and the inner wall of the trench; 3) etching back the silicon nitride layers to remove the silicon nitride from the bottom of the trench, forming a silicon nitride side wall on the side wall of the trench, removing the gasket oxide film from the bottom of the trench by wet etching and etching the gasket oxide film positioned at the bottom of the silicon nitride side wall at the same time; 4) performing an oxidation process to grow a bottom oxide film at the bottom of the trench; and 5) completely removing the silicon nitride layers from the substrate, the silicon nitride side wall and the gasket oxide film from the side wall of the trench by using an etching process and performing an ordinary process of growing gate oxide and filling the trench. By the method, a thicker oxide film can be formed at the bottom of the trench to greatly reduce the grid-drain capacitance of a device, so that the switch characteristic of a trench power device is improved.
Description
Technical field
The present invention relates to a kind ofly prepare the method for deielectric-coating at channel bottom, particularly a kind of method of making oxide-film at channel bottom.
Background technology
In the existing groove manufacturing technology; no matter utilize photoresist to do mask protection or utilize deielectric-coating to do mask protection; finish at etching groove, obtain (gash depth, width and pattern) after the needed groove shape, the heat oxide film of just growing is done the gate oxidation films of device.Again by the growing polycrystalline silicon filling groove, and by polysilicon being returned quarter or cmp the polysilicon of silicon face is removed, carried out trap again and inject, the injection in source injection and P+ district obtains device architecture as shown in Figure 1.In this structure, the gate oxide film thickness basically identical of the oxide thickness of channel bottom and trenched side-wall, so the overlap capacitance between grid-leakage is bigger, this problem when device cell density is high is more serious.But pursuing little cellar area, be high cell density, can reduce the conducting resistance of device, reduce the power consumption of device, is one of power device effort target always.Therefore it is big how to solve grid-leakage overlap capacitance under high density, the affected problem of switching speed, and just making slot type power device can reduce power consumption can have good switching characteristic again just highly significant.In order to reduce the overlap capacitance between grid-leakage, first growth silica grow up plain polysilicon or indefinite form silicon are taked in some suggestion again, again by cmp, mode that return to carve, reoxidize forms a medium that encases plain silicon in the groove bottom with silica, and then carry out gate oxidation, the polycrystalline grid growth technique of general technology, but this method complex process, production cost is very high.Another kind of suggestion is to fill up to carry out cmp again behind the medium or return carving, then the groove medium being carried out the bottom dielectric that etching stays up to needs in groove.But the getable bottom dielectric film thickness of this suggestion lack of homogeneity, the oxide-film on the side wall limit can not be etched etc. in the same plane at needs, all make it can not satisfy the needs of batch process.Therefore so far, most slot type power device is still structure shown in Figure 1.
Summary of the invention
The technical problem to be solved in the present invention provides and a kind ofly prepares the method for oxide-film at channel bottom, and it can make thicker oxide-film at channel bottom.
For solving the problems of the technologies described above, of the present inventionly prepare the method for oxide-film at channel bottom, etching forms after the groove on substrate, comprises the steps:
1) grow liners oxide-film in groove;
2) deposit silicon nitride on entire substrate makes substrate top surface and trench wall all be deposited with silicon nitride layer;
3) silicon nitride layer is returned the silicon nitride of carving with the removal channel bottom, form the silicon nitride side wall at trenched side-wall, the liner oxide film of wet etching channel bottom is corroded the liner oxide film that is positioned at silicon nitride side wall bottom simultaneously afterwards;
4) carry out oxidation technology in described channel bottom growth bottom oxide film;
5) utilize etching technics to remove silicon nitride layer, silicon nitride side wall on the substrate and the liner oxide film that is positioned at trenched side-wall fully, carry out conventional growth of gate oxide layer and trench fill technology afterwards.
The method for preparing oxide-film at channel bottom of the present invention, etching forms after the groove on substrate, by somatomedin film and time quarter, the undercut etch of silica under the side wall is exposed the silicon of channel bottom, by thermal oxidation technology channel bottom is carried out oxidation then, the deielectric-coating that will block usefulness removes at last, thereby obtain the thick oxide-film that needs at channel bottom, the gate-to-drain electric capacity of device is reduced significantly, improve the switching characteristic of slot type power device.It has, and technical process is simple and clear, the characteristics at the relative end of production cost, goes for producing in batches.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the schematic cross-section of the slot type power device of existing prepared;
Fig. 2 to Fig. 6 is for preparing the corresponding a plurality of schematic cross-sections of step in the method for oxide-film with of the present invention at channel bottom;
Fig. 7 is the schematic cross-section of prepared according to the methods of the invention slot type power device.
Embodiment
The method for preparing oxide-film at channel bottom of the present invention, be used at the thicker oxide-film of channel bottom preparation, utilize existing technology (see figure 2) after substrate (can be silicon chip, also can be the silicon epitaxy layer on the silicon chip) is gone up etching formation groove, comprising following steps:
1) in groove the grow liners oxide-film as the resilient coating of the following deielectric-coating that will grow, this liner oxide film is used to prevent that deielectric-coating may be to the stress damage of silicon substrate on it, generally thinner, it is influential to the beak length of step 4 back bottom oxide film, this film is thick more, beak long more (100-500 dust usually).
2) somatomedin film and then on silicon chip, specifically can be silicon nitride layer, make substrate top surface and trench wall all be deposited with silicon nitride layer, the thickness of this silicon nitride film is also influential to the beak length of step 4 back bottom oxide film, this film is thin more, beak long more (1000-3000 dust usually) (see figure 3).
3) utilize back quarter that the silicon nitride layer of channel bottom is removed (in returning the process of carving, the silicon nitride in step 2 deposit that is arranged in the substrate top is removed simultaneously), form the silicon nitride side wall at trenched side-wall, wet etching (utilizes sulfuric acid afterwards, or hydrofluoric acid etc.) liner oxide film of channel bottom is removed, utilize isotropic characteristics of wet etching, the liner oxide film that channel bottom is positioned between silicon nitride side wall-silicon substrate is also removed (this phenomenon also can be described as undercutting), this undercutting is influential to the beak shape and the length of step 4 rear oxidation film, undercutting is many more, beak big more (100-300 dust usually) is referring to Fig. 4.The Hui Keke of silicon nitride layer uses dry etch process.
4) carry out oxidation technology in channel bottom growth bottom oxide film (see figure 5), bottom oxide film can be utilized the thermal oxidation technology growth.Can carry out primary ions at channel bottom as required before thermal oxidation this moment injects, after making channel bottom accept some ions, oxidation rate is accelerated, according to control to oxidization time, can form the oxide layer that needs thickness at channel bottom, because the undercutting of oxide-film is arranged in step 3), therefore it is thicker to be easy to obtain both sides, long beak, not only obtain thick bottom oxide film after making technology finish, and in certain zone of bottom sidewall, obtain the oxide-film thicker than channel region, more a step reduces to make grid-drain capacitance.
5) utilize etching technics to remove the liner oxide film of silicon nitride layer, monox lateral wall and trenched side-wall on the substrate fully, obtaining channel bottom has the structure (see figure 6) of thick bottom oxide film, carry out conventional growth of gate oxide layer and trench fill technology and subsequent technique afterwards, the final structure that forms as shown in Figure 7.
After the etching groove among the present invention, can be deposited with hard mask layer (thickness of the superiors' film of this hard mask layer should be able to guarantee at least also surplus 500 dusts after the oxidizing process of step 4) is finished) on the substrate earlier, can comprise lower floor's oxide layer and upper strata nitration case, in Fig. 3 as seen in step 2) in deposit silicon nitride layer with combine as the upper strata nitration case of hard mask layer.Step 2) silicon nitride layer in can be other deielectric-coating, as long as it can stop beneath substrate oxidation in the thermal oxidation of step 4), and the effect of binding buffer layer, can on silicon substrate, not cause defective to get final product.In the example specific to hard mask layer position lower floor's oxide layer and upper strata nitration case; in the step 4) oxidation technology in the channel bottom silicon oxidation oxygen also enter the nitration case that makes the top layer in the nitration case of upper strata and be oxidized to the nitrogen oxide layer; after oxidation was finished, it was not oxidized with the silicon substrate under protecting to guarantee that at least the upper strata nitration case also remains more than 500 dusts.Silica undercut etch in the step 3) can realize by wet etching, also can realize by isotropic oxide-film dry etching after silicon nitride side wall etching.Thermal oxidation in the step 4) can realize in high temperature furnace pipe, also can be as realizing in the fast oxidative equipment by other.If carrying out ion before the oxidation in step 4) injects, because this injection ion can become a part of device drain at the nubbin of silicon substrate, therefore its inject ionic species (N or P type) will be consistent with prepared device corresponding drain electrode ionic species (be that this injection ion of N type device is N type such as phosphorus, arsenic etc.), its ion injection rate also to guarantee to allow final residual in drain electrode doping content and the concentration of N extension in same magnitude, in order to avoid cause the decline of device BV, and in order to reduce implanted dopant residual in silicon, the ion here injects the general low energy that adopts and injects.As for NMOSFET, the injection energy is 20KEV, the about 10*10 of dosage
12The phosphonium ion of/CM2, the impurity major part of these injections be the thermal oxidation technology silicon that will be consumed below, thereby make the ion that left behind few, and after the subsequent thermal process, its residual fraction does not impact device BV or do not have a substantial influence.Described silicon nitride layer on the substrate in the step 5), silicon nitride side wall and the removal that is positioned at the liner oxide film of trenched side-wall can realize in a step or multistep wet etching, also can be by realizing, or the combination of wet etching and dry etching realize in a step or multistep dry etching.
Claims (6)
1. one kind prepares the method for oxide-film at channel bottom, and etching forms after the groove on substrate, it is characterized in that, comprises the steps:
1) grow liners oxide-film in described groove;
2) deposit silicon nitride on entire substrate makes substrate top surface and trench wall all be deposited with silicon nitride layer;
3) described silicon nitride layer is returned the silicon nitride of carving with the removal channel bottom, form the silicon nitride side wall at described trenched side-wall, wet etching is removed the liner oxide film of described channel bottom afterwards, and corrosion simultaneously is positioned at the liner oxide film of silicon nitride side wall bottom;
4) carry out oxidation technology in described channel bottom growth bottom oxide film;
5) utilize etching technics to remove described silicon nitride layer, silicon nitride side wall on the substrate and the liner oxide film that is positioned at trenched side-wall fully, carry out conventional growth of gate oxide layer and trench fill technology afterwards.
2. as claimed in claim 1ly prepare the method for oxide-film at channel bottom, it is characterized in that: the growth of the bottom oxide film in the described step 4 adopts hot oxygen technology to make.
3. the method for preparing oxide-film at channel bottom as claimed in claim 2, it is characterized in that: before the hot oxide growth bottom oxide film of described step 4, carry out earlier carrying out the step that ion injects at described channel bottom, the ionic type that is injected is identical with the drain region ionic type of the device of manufacturing.
4. as claimed in claim 1ly prepare the method for oxide-film at channel bottom, it is characterized in that: described step 3 is carved returning of silicon nitride layer and is adopted dry etch process.
5. as the described method for preparing oxide-film at channel bottom of each claim in the claim 1 to 4, it is characterized in that: before etching forms groove, be deposited with hard mask layer on the described substrate, the superiors' film in the described hard mask layer at least also remains the thickness of 500 dusts after the oxidation technology of step 4 is finished.
6. as claimed in claim 5ly prepare the method for oxide-film at channel bottom, it is characterized in that: described hard mask layer comprises lower floor's oxide layer and upper strata nitration case.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100570752A CN101866849B (en) | 2009-04-16 | 2009-04-16 | Method for preparing oxide film at bottom of trench |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100570752A CN101866849B (en) | 2009-04-16 | 2009-04-16 | Method for preparing oxide film at bottom of trench |
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| Publication Number | Publication Date |
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| CN101866849A true CN101866849A (en) | 2010-10-20 |
| CN101866849B CN101866849B (en) | 2012-06-27 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633008A (en) * | 2012-08-20 | 2014-03-12 | 中国科学院微电子研究所 | Shallow trench isolation manufacturing method |
| CN103839807A (en) * | 2012-11-20 | 2014-06-04 | 北大方正集团有限公司 | Trench DMOS transistor manufacturing method and trench DMOS transistor |
| CN103972101A (en) * | 2013-02-06 | 2014-08-06 | 英飞凌科技奥地利有限公司 | Method for producing semiconductor device with vertical dielectric layer |
| CN112551481A (en) * | 2020-12-07 | 2021-03-26 | 山东大学 | Method for preventing undercut etching of side wall of three-dimensional microstructure in micro-electromechanical manufacturing process |
| CN114999917A (en) * | 2022-05-05 | 2022-09-02 | 上海朕芯微电子科技有限公司 | Preparation method of low Cgd capacitance power MOSFET |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291298B1 (en) * | 1999-05-25 | 2001-09-18 | Advanced Analogic Technologies, Inc. | Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses |
| US6437386B1 (en) * | 2000-08-16 | 2002-08-20 | Fairchild Semiconductor Corporation | Method for creating thick oxide on the bottom surface of a trench structure in silicon |
| US6709930B2 (en) * | 2002-06-21 | 2004-03-23 | Siliconix Incorporated | Thicker oxide formation at the trench bottom by selective oxide deposition |
| US8115252B2 (en) * | 2005-05-12 | 2012-02-14 | M-Mos Sdn.Bhd | Elimination of gate oxide weak spot in deep trench |
-
2009
- 2009-04-16 CN CN2009100570752A patent/CN101866849B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103633008A (en) * | 2012-08-20 | 2014-03-12 | 中国科学院微电子研究所 | Shallow trench isolation manufacturing method |
| CN103839807A (en) * | 2012-11-20 | 2014-06-04 | 北大方正集团有限公司 | Trench DMOS transistor manufacturing method and trench DMOS transistor |
| CN103972101A (en) * | 2013-02-06 | 2014-08-06 | 英飞凌科技奥地利有限公司 | Method for producing semiconductor device with vertical dielectric layer |
| CN103972101B (en) * | 2013-02-06 | 2017-04-12 | 英飞凌科技奥地利有限公司 | Method for producing semiconductor device with vertical dielectric layer |
| CN112551481A (en) * | 2020-12-07 | 2021-03-26 | 山东大学 | Method for preventing undercut etching of side wall of three-dimensional microstructure in micro-electromechanical manufacturing process |
| CN112551481B (en) * | 2020-12-07 | 2025-01-07 | 山东大学 | A method for preventing undercutting and etching of three-dimensional microstructure sidewalls in microelectronic machinery manufacturing process |
| CN114999917A (en) * | 2022-05-05 | 2022-09-02 | 上海朕芯微电子科技有限公司 | Preparation method of low Cgd capacitance power MOSFET |
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| Publication number | Publication date |
|---|---|
| CN101866849B (en) | 2012-06-27 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |