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CN101866849B - Method for preparing oxide film at bottom of trench - Google Patents

Method for preparing oxide film at bottom of trench Download PDF

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Publication number
CN101866849B
CN101866849B CN2009100570752A CN200910057075A CN101866849B CN 101866849 B CN101866849 B CN 101866849B CN 2009100570752 A CN2009100570752 A CN 2009100570752A CN 200910057075 A CN200910057075 A CN 200910057075A CN 101866849 B CN101866849 B CN 101866849B
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silicon nitride
oxide
film
trench
oxide film
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CN101866849A (en
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肖胜安
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses a method for preparing an oxide film at the bottom of a trench. The method comprises the following steps of: after the trench is etched on a substrate, 1) growing a gasket oxide film in the trench; 2) depositing silicon nitride on the whole substrate to ensure that silicon nitride layers are deposited on both the upper surface of the substrate and the inner wall of the trench; 3) etching back the silicon nitride layers to remove the silicon nitride from the bottom of the trench, forming a silicon nitride side wall on the side wall of the trench, removing the gasket oxide film from the bottom of the trench by wet etching and etching the gasket oxide film positioned at the bottom of the silicon nitride side wall at the same time; 4) performing an oxidation process to grow a bottom oxide film at the bottom of the trench; and 5) completely removing the silicon nitride layers from the substrate, the silicon nitride side wall and the gasket oxide film from the side wall of the trench by using an etching process and performing an ordinary process of growing gate oxide and filling the trench. By the method, a thicker oxide film can be formed at the bottom of the trench to greatly reduce the grid-drain capacitance of a device, so that the switch characteristic of a trench power device is improved.

Description

The method for preparing oxide-film at channel bottom
Technical field
The present invention relates to a kind ofly prepare the method for deielectric-coating at channel bottom, particularly a kind of method of making oxide-film at channel bottom.
Background technology
In the existing groove manufacturing technology; No matter utilize photoresist to do mask protection or utilize deielectric-coating to do mask protection; Accomplish at etching groove, obtain (gash depth, width and pattern) after the needed groove shape, the heat oxide film of just growing is done the gate oxidation films of device.Again through the growing polycrystalline silicon filling groove, and through polysilicon being returned quarter or cmp the polysilicon of silicon face is removed, carried out trap again and inject, the injection in source injection and P+ district obtains device architecture as shown in Figure 1.In this structure, the gate oxide film thickness basically identical of the oxide thickness of channel bottom and trenched side-wall, so the overlap capacitance between grid-leakage is bigger, this problem when device cell density is high is more serious.But pursuing little cellar area, be high cell density, can reduce the conducting resistance of device, reduce the power consumption of device, is one of power device effort target always.Therefore it is big under high density, how to solve grid-leakage overlap capacitance, the affected problem of switching speed, and just making slot type power device can reduce power consumption can have good switching characteristic again just highly significant.In order to reduce the overlap capacitance between grid-leakage; First growth silica grow up plain polysilicon or indefinite form silicon are taked in some suggestion again; Again through cmp, mode that return to carve, reoxidize forms a medium that encases plain silicon in the groove bottom with silica; And then carry out gate oxidation, the polycrystalline grid growth technique of general technology, but this method complex process, production cost is very high.Another kind of suggestion is in groove, to fill up to carry out cmp again behind the medium or return carving, then the groove medium being carried out the bottom dielectric that etching stays up to needs.But the getable bottom dielectric film thickness of this suggestion lack of homogeneity, the oxide-film on the side wall limit can not be etched etc. in the same plane at needs, all make it can not satisfy the needs of batch process.Therefore so far, most slot type power device is still structure shown in Figure 1.
Summary of the invention
The technical problem that the present invention will solve provides and a kind ofly prepares the method for oxide-film at channel bottom, and it can make thicker oxide-film at channel bottom.
For solving the problems of the technologies described above, of the present inventionly prepare the method for oxide-film at channel bottom, etching forms after the groove on substrate, comprises the steps:
1) grow liners oxide-film in groove;
2) deposit silicon nitride on entire substrate makes substrate top surface and trench wall all be deposited with silicon nitride layer;
3) silicon nitride layer is returned the silicon nitride of carving with the removal channel bottom, form the silicon nitride side wall at trenched side-wall, the liner oxide film of wet etching channel bottom is corroded the liner oxide film that is positioned at silicon nitride side wall bottom simultaneously afterwards;
4) carry out oxidation technology in said channel bottom growth bottom oxide film;
5) utilize etching technics to remove silicon nitride layer, silicon nitride side wall on the substrate and the liner oxide film that is positioned at trenched side-wall fully, carry out conventional growth of gate oxide layer and trench fill technology afterwards.
Of the present inventionly prepare the method for oxide-film at channel bottom, etching forms after the groove on substrate, carves with returning through the somatomedin film; The undercut etch of silica under the side wall is exposed the silicon of channel bottom, through thermal oxidation technology channel bottom is carried out oxidation then; The deielectric-coating that will block usefulness at last removes; Thereby the thick oxide-film that obtains at channel bottom needing, the gate-to-drain electric capacity of device is reduced significantly, improve the switching characteristic of slot type power device.It has, and technical process is simple and clear, the characteristics at the relative end of production cost, goes for producing in batches.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the schematic cross-section of the slot type power device of existing prepared;
Fig. 2 to Fig. 6 is for preparing the corresponding a plurality of schematic cross-sections of step in the method for oxide-film with of the present invention at channel bottom;
Fig. 7 is the schematic cross-section of prepared according to the methods of the invention slot type power device.
Embodiment
Of the present inventionly prepare the method for oxide-film, be used at the thicker oxide-film of channel bottom preparation at channel bottom, utilize existing technology substrate (can be silicon chip, also can be the silicon epitaxy layer on the silicon chip) go up etching form groove after (see figure 2), comprise following steps:
1) in groove the grow liners oxide-film as the resilient coating of the following deielectric-coating that will grow; This liner oxide film is used to prevent that deielectric-coating maybe be to the stress damage of silicon substrate on it; Generally thinner; It is influential to the beak length of step 4 back bottom oxide film, and this film is thick more, beak longer (100-500 dust usually).
2) somatomedin film and then on silicon chip; Specifically can be silicon nitride layer; Make substrate top surface and trench wall all be deposited with silicon nitride layer; The thickness of this silicon nitride film is also influential to the beak length of step 4 back bottom oxide film, and this film is thin more, beak longer (1000-3000 dust usually) (see figure 3).
3) utilize back the silicon nitride layer removal (in returning the process of carving, the silicon nitride in step 2 deposit that is arranged in the substrate top is removed simultaneously) of carving, form the silicon nitride side wall at trenched side-wall with channel bottom; Wet etching (utilizes sulfuric acid afterwards; Or hydrofluoric acid etc.) liner oxide film of channel bottom is removed, utilize isotropic characteristics of wet etching, the liner oxide film that channel bottom is positioned between silicon nitride side wall-silicon substrate is also removed (this phenomenon also can be described as undercutting); This undercutting is influential to the beak shape and the length of step 4 rear oxidation film; Undercutting is many more, and beak bigger (100-300 dust usually) is referring to Fig. 4.The Hui Keke of silicon nitride layer uses dry etch process.
4) carry out oxidation technology in channel bottom growth bottom oxide film (see figure 5), bottom oxide film thermal oxidation technology growth capable of using.Can be before thermal oxidation carry out primary ions at channel bottom as required this moment and inject, make channel bottom accept some ions after, oxidation rate is accelerated; According to control to oxidization time; The oxide layer that can need thickness in channel bottom formation, because the undercutting of oxide-film is arranged in step 3), it is thicker therefore to be easy to obtain both sides; Long beak; Not only obtain thick bottom oxide film after making technology accomplish, and in certain zone of side walls, obtain the oxide-film thicker than channel region, more a step reduces to make grid-drain capacitance.
5) utilize etching technics to remove the liner oxide film of silicon nitride layer, monox lateral wall and trenched side-wall on the substrate fully; Obtaining channel bottom has the structure (see figure 6) of thick bottom oxide film; Carry out conventional growth of gate oxide layer and trench fill technology and subsequent technique afterwards, finally form structure as shown in Figure 7.
After the etching groove among the present invention; Can be deposited with hard mask layer (thickness of the superiors' film of this hard mask layer should be able to guarantee at least also surplus 500 dusts after the oxidizing process of step 4) is accomplished) on the substrate earlier; Can comprise lower floor's oxide layer and upper strata nitration case, visible in step 2 in Fig. 3) in the silicon nitride layer of deposit combine with the upper strata nitration case that is used as hard mask layer.Step 2) silicon nitride layer in can be other deielectric-coating, as long as it can stop beneath substrate oxidation in the thermal oxidation of step 4), and the effect of binding buffer layer, can on silicon substrate, not cause defective to get final product.In the instance specific to hard mask layer position lower floor's oxide layer and upper strata nitration case; In the step 4) oxidation technology in the channel bottom silicon oxidation oxygen also get into the nitration case that makes the top layer in the nitration case of upper strata and be oxidized to the nitrogen oxide layer; After oxidation was accomplished, it was not oxidized with the silicon substrate under protecting to guarantee that at least the upper strata nitration case also remains more than 500 dusts.Silica undercut etch in the step 3) can realize through wet etching, also can after silicon nitride side wall etching, realize through isotropic oxide-film dry etching.Thermal oxidation in the step 4) can realize in high temperature furnace pipe, also can be as realizing in the fast oxidative equipment through other.If carrying out ion before the oxidation in step 4) injects; Because this injection ion can become a part of device drain at the nubbin of silicon substrate; Therefore its inject ionic species (N or P type) will be consistent with prepared device corresponding drain electrode ionic species (be that this injection ion of N type device is N type such as phosphorus; Arsenic etc.), its ion injection rate also will guarantee to let the concentration of doping content and the N extension of final residual in drain electrode in same magnitude, in order to avoid cause the decline of device BV; And in order to reduce implanted dopant residual in silicon, the ion here injects the general low energy that adopts and injects.As for NMOSFET, the injection energy is 20KEV, the about 10*10 of dosage 12The phosphonium ion of/CM2, the impurity major part of these injections be the thermal oxidation technology silicon that will be consumed below, thereby make the ion that left behind few, and after the subsequent thermal process, its residual fraction does not impact device BV or do not have a substantial influence.Said silicon nitride layer on the substrate in the step 5), silicon nitride side wall and the removal that is positioned at the liner oxide film of trenched side-wall can realize in a step or multistep wet etching; Also can be through realizing, or the combination of wet etching and dry etching realize in a step or multistep dry etching.

Claims (6)

1. one kind prepares the method for oxide-film at channel bottom, and etching forms after the groove on substrate, it is characterized in that, comprises the steps:
1) grow liners oxide-film in said groove;
2) deposit silicon nitride on entire substrate makes substrate top surface and trench wall all be deposited with silicon nitride layer;
3) said silicon nitride layer is returned the silicon nitride of carving with the removal channel bottom, form the silicon nitride side wall at said trenched side-wall, wet etching is removed the liner oxide film of said channel bottom afterwards, and corrosion simultaneously is positioned at the liner oxide film of silicon nitride side wall bottom;
4) carry out oxidation technology in said channel bottom growth bottom oxide film;
5) utilize etching technics to remove said silicon nitride layer, silicon nitride side wall on the substrate and the liner oxide film that is positioned at trenched side-wall fully, carry out conventional growth of gate oxide layer and trench fill technology afterwards.
2. as claimed in claim 1ly prepare the method for oxide-film at channel bottom, it is characterized in that: the growth of the bottom oxide film in the said step 4) adopts hot oxygen technology to make.
3. the method for preparing oxide-film at channel bottom as claimed in claim 2; It is characterized in that: before the hot oxide growth bottom oxide film of said step 4); Carry out earlier carrying out the step that ion injects at said channel bottom, the ionic type that is injected is identical with the drain region ionic type of the device of manufacturing.
4. as claimed in claim 1ly prepare the method for oxide-film at channel bottom, it is characterized in that: said step 3) is carved returning of silicon nitride layer and is adopted dry etch process.
5. like the described method for preparing oxide-film at channel bottom of each claim in the claim 1 to 4; It is characterized in that: before etching forms groove; Be deposited with hard mask layer on the said substrate, the superiors' film in the said hard mask layer at least also remains the thickness of 500 dusts after the oxidation technology of step 4) is accomplished.
6. as claimed in claim 5ly prepare the method for oxide-film at channel bottom, it is characterized in that: said hard mask layer comprises lower floor's oxide layer and upper strata nitration case.
CN2009100570752A 2009-04-16 2009-04-16 Method for preparing oxide film at bottom of trench Active CN101866849B (en)

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103633008B (en) * 2012-08-20 2018-03-30 中国科学院微电子研究所 shallow trench isolation manufacturing method
CN103839807A (en) * 2012-11-20 2014-06-04 北大方正集团有限公司 Trench DMOS transistor manufacturing method and trench DMOS transistor
US8999783B2 (en) * 2013-02-06 2015-04-07 Infineon Technologies Austria Ag Method for producing a semiconductor device with a vertical dielectric layer
CN112551481B (en) * 2020-12-07 2025-01-07 山东大学 A method for preventing undercutting and etching of three-dimensional microstructure sidewalls in microelectronic machinery manufacturing process
CN114999917A (en) * 2022-05-05 2022-09-02 上海朕芯微电子科技有限公司 Preparation method of low Cgd capacitance power MOSFET

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291298B1 (en) * 1999-05-25 2001-09-18 Advanced Analogic Technologies, Inc. Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses
US6437386B1 (en) * 2000-08-16 2002-08-20 Fairchild Semiconductor Corporation Method for creating thick oxide on the bottom surface of a trench structure in silicon
US6709930B2 (en) * 2002-06-21 2004-03-23 Siliconix Incorporated Thicker oxide formation at the trench bottom by selective oxide deposition
CN1893111A (en) * 2005-05-12 2007-01-10 谢福渊 Elimination of gate oxide weak spot in deep trench

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291298B1 (en) * 1999-05-25 2001-09-18 Advanced Analogic Technologies, Inc. Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses
US6437386B1 (en) * 2000-08-16 2002-08-20 Fairchild Semiconductor Corporation Method for creating thick oxide on the bottom surface of a trench structure in silicon
US6709930B2 (en) * 2002-06-21 2004-03-23 Siliconix Incorporated Thicker oxide formation at the trench bottom by selective oxide deposition
CN1893111A (en) * 2005-05-12 2007-01-10 谢福渊 Elimination of gate oxide weak spot in deep trench

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