CN103208510B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device, which comprises: a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The first epitaxial layer is stacked on a substrate and has a first conductive type. Each first epitaxial layer is internally provided with at least one first doped region and at least one second doped region adjacent to the first doped region, the first doped region is provided with a second conductive type, and the second doped region is provided with the first conductive type. The second epitaxial layer is disposed on the first epitaxial layer and has a first conductivity type. The second epitaxial layer has a trench therein, and a third doped region adjacent to a sidewall of the trench and having the second conductivity type. The gate structure is disposed on the second epitaxial layer above the second doped region. The invention also discloses a method for manufacturing the semiconductor device. According to the semiconductor device and the manufacturing method thereof provided by the embodiment of the invention, the increase of the on-resistance can be avoided, the process can be simplified, and the manufacturing cost can be reduced.

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device, in particular to a semiconductor device with a superjunction structure and a manufacturing method thereof.

Background technique

FIG. 1 shows a schematic cross-sectional view of a conventional N-type vertical double-diffused MOSFET (VDMOSFET). The N-type vertical diffused metal oxide semiconductor field effect transistor 10 includes: a semiconductor substrate and a gate structure located thereon. The semiconductor substrate has an N-type epitaxy drift region 100 and a P-type base region 102 above it to form a P-N junction. Furthermore, there is a drain region 106 under the N-type epitaxial drift region 100 , which is connected to a drain electrode 114 . The P-type body region 102 has a source region 104 connected to a source electrode 112 . The gate structure is composed of a gate dielectric layer 108 and a gate electrode 110 thereon.

In order to increase the withstand voltage of the P-N junction in the N-type VMOSFET 10 , it is necessary to reduce the doping concentration and/or increase the thickness of the N-type epitaxial drift region 100 . However, when the withstand voltage of the P-N junction is increased in the above manner, the on-resistance (Ron) of the N-type VMOSFET 10 will also be increased at the same time. That is, the on-resistance is limited by the doping concentration and thickness of the N-type epitaxial drift region.

The vertical diffused metal oxide semi-field effect transistor with super-junction structure can increase the dopant concentration in the N-type epitaxial drift region, thereby increasing the withstand voltage of the P-N junction, and at the same time avoiding the increase of the on-resistance . However, since the current superjunction structure requires multiple epitaxial growths, and the number of epitaxial growths depends on the withstand voltage of the P-N junction, the fabrication of the above superjunction structure has disadvantages such as complicated process and high manufacturing cost. .

Therefore, it is necessary to seek a semiconductor device with a superjunction structure, which can improve or solve the above-mentioned problems.

Contents of the invention

An embodiment of the present invention provides a semiconductor device, including: a plurality of first epitaxial layers stacked on a substrate, and the first epitaxial layers and the substrate have a first conductivity type, wherein each first epitaxial layer has a at least one first doped region and at least one second doped region adjacent thereto, the first doped region has a second conductivity type, and the second doped region has a first conductivity type; a second epitaxial layer, It is arranged on the first epitaxial layer and has the first conductivity type, wherein there is a trench in the second epitaxial layer, exposing the first doped region below; a third doped region, adjacent to the side wall of the trench , and has a second conductivity type, wherein the doping concentration of the second epitaxial layer and the first, second, and third doped regions is greater than that of the first epitaxial layer; and a gate structure is arranged on the second on the second epitaxial layer above the doped region.

Another embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a plurality of stacked first epitaxial layers on a substrate, and forming at least one first doped region and At least one second doped region adjacent to it, wherein the first epitaxial layer, the substrate and the second doped region have a first conductivity type, and the first doped region has a second conductivity type; in the first epitaxial layer Form a second epitaxial layer with the first conductivity type; form a trench in the second epitaxial layer to expose the first doped region below; form a third doped region on the side wall of the trench a region having a second conductivity type, wherein the doping concentration of the second epitaxial layer and the first, second, and third doped regions is greater than the doping concentration of each of the first epitaxial layer; and in the second doped region A gate structure is formed on the upper second epitaxial layer.

According to the semiconductor device and the manufacturing method of the embodiments of the present invention, the increase of the on-resistance can be avoided, and the process can be simplified and the manufacturing cost can be reduced.

Description of drawings

The drawings described here are used to provide further understanding of the present invention, constitute a part of the application, and do not limit the present invention. In the attached picture:

FIG. 1 shows a schematic cross-sectional view of a conventional N-type vertical diffused metal oxide half field effect transistor.

2A to 2G are schematic cross-sectional views illustrating a manufacturing method of a semiconductor device according to an embodiment of the present invention.

3A to 3C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

4A to 4C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

5A to 5C are schematic cross-sectional views illustrating a manufacturing method of a semiconductor device according to another embodiment of the present invention.

Figure number:

current technology:

10~N type vertical diffused metal oxide half field effect transistor;

100 ~ N-type epitaxial drift region;

102～P-type matrix region;

104～source region;

106～drain region;

108～gate electrode layer;

110～gate electrode;

112～source electrode;

114 ~ drain electrode.

Example:

20, 20’, 20”, 20”’～semiconductor device;

200～base;

200a to the fourth doped region;

200b to the fifth doped region;

201, 203, 408～doping process;

201a～sixth doped region;

203a～the seventh doped region;

204～the first epitaxial layer;

204a～the first doped region;

204b～the second doped region;

206～the second epitaxial layer;

206a～groove;

208～hard mask;

208a～opening;

210～insulation liner layer;

212, 212', 212", 212"'～the third doped region;

308～doped layer;

310～dielectric material layer;

228～gate dielectric layer;

230～gate electrode;

232～well area;

234～source region;

A～Active area;

B ~ interface.

Detailed ways

The semiconductor device and its manufacturing method according to the embodiment of the present invention will be described below. However, it can be easily understood that the embodiments provided in the present invention are only used to illustrate the making and use of the present invention in a specific way, and are not intended to limit the scope of the present invention.

Please refer to FIG. 2G , which shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. The semiconductor device 20 of the embodiment of the present invention includes a vertical diffused metal oxide half field effect transistor (VDMOSFET) having a super junction structure. In this embodiment, the semiconductor device 20 includes: a plurality of first epitaxial layers 204 , a second epitaxial layer 206 and at least one gate structure. The first epitaxial layer 204 is stacked on a substrate 200 , and each of the first epitaxial layer 204 and the substrate 200 has a first conductivity type. As shown in FIG. 2G , the substrate 200 may include an active region A and a termination region (not shown) surrounding the active region A. Referring to FIG. In one embodiment, the active region A provides semiconductor devices to be formed thereon, and the terminal region serves as insulation between different semiconductor devices.

Each first epitaxial layer 204 has a plurality of first doped regions 204a and a plurality of second doped regions 204b alternately arranged with the first doped regions 204a, so that each second doped region 204b and at least one first doped region One doped region 204a is adjacent, or each first doped region 204a is adjacent to at least one second doped region 204b. Here, to simplify the drawing, only one second doped region 204b and two adjacent first doped regions 204a are shown. Moreover, the first doped region 204a has a second conductivity type different from the first conductivity type, and the second doped region 204b has the first conductivity type.

The second epitaxial layer 206 is disposed on the stacked first epitaxial layer 204 and has the first conductivity type. The second epitaxial layer 206 has a plurality of trenches 206a, and each trench 206a corresponds to each first doped region 204a below, and the bottom of each trench 206a exposes the corresponding first doped region 204a. Furthermore, the plurality of third doped regions 212 correspond to the trench 206a, and each third doped region 212 is adjacent to a sidewall of the corresponding trench 206a. In this embodiment, the third doped region 212 is located in the corresponding trench 206 a and includes an epitaxial layer or a polysilicon layer. Moreover, the doping concentration of the second epitaxial layer 206 and the first doped region 204 a , the second doped region 204 b and the third doped region 212 is greater than that of each first epitaxial layer 204 .

In this embodiment, the substrate 200 has a fourth doped region 200a and a fifth doped region 200b thereon, wherein an interface B exists between the fourth doped region 200a and the fifth doped region 200b. In one embodiment, the fourth doped region 200a is formed of a semiconductor material, and the fifth doped region 200b is formed of an epitaxial layer. In another embodiment, the fourth doped region 200 a and the fifth doped region 200 b with different doping concentrations are formed in the substrate 200 made of the same semiconductor material.

In this embodiment, the fourth doped region 200a and the fifth doped region 200b have the first conductivity type, and the fourth doped region 200a may be a heavily doped region, and the fifth doped region 200b may be a lightly doped region. doped region. Furthermore, the fifth doped region 200b has a plurality of sixth doped regions 201a and a plurality of seventh doped regions 203a arranged alternately with the sixth doped regions 201a, so that each seventh doped region 203a is compatible with at least A sixth doped region 201a is adjacent, or each sixth doped region 201a is adjacent to at least one seventh doped region 203a. Here, to simplify the drawing, only a seventh doped region 203a and two adjacent sixth doped regions 201a are shown.

In this embodiment, the sixth doped region 201a corresponds to the first doped region 204a and the seventh doped region 203a corresponds to the second doped region 204b. Furthermore, the doping concentration of the first epitaxial layer 204 can be substantially the same as that of the fifth doped region 200b, and the second epitaxial layer 206 is the same as that of the first doped region 204a, the second doped region 204b, and the third doped region 212. , the doping concentration of the sixth doping region 201a and the seventh doping region 203a is greater than the doping concentration of the fifth doping region 200b, and smaller than the doping concentration of the fourth doping region 200a.

In this embodiment, the first conductivity type is N type, and the second conductivity type is P type. However, in other embodiments, the first conductivity type can also be P-type, and the second conductivity type is N-type. Therefore, the second doped region 204b and the seventh doped region 203a having the first conductivity type and the first doped region 204a and the sixth doped region 201a having the second conductivity type are in the fifth doped region 200b and A super junction structure is formed in the first epitaxial layer 204 . Similarly, the second epitaxial layer 206 with the first conductivity type and the third doped region 212 with the second conductivity type also form a super junction structure.

A gate structure is disposed on the second epitaxial layer 206 and corresponding to the second doped region 204 b in each first epitaxial layer 204 , including a gate dielectric layer 228 and a gate electrode 230 thereon. Furthermore, a well region 232 of the second conductivity type is formed in the upper half of each third doped region 212 and extends in the second epitaxial layer 206 outside the trench 206 a. The source region 234 with the first conductivity type is formed in each well region 232 on both sides of the gate structure, and forms a vertical diffused metal oxide with the gate structure and the fourth doped region (serving as the drain region) 200a Half Field Effect Transistor.

Please refer to FIG. 3C , which shows a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention, wherein components identical to those in FIG. 2G use the same reference numerals and their descriptions are omitted. In this embodiment, the semiconductor device 20' is similar to the semiconductor device 20 shown in FIG. 2G, except that each third doped region 212', such as an epitaxial layer, is conformably disposed in the corresponding trench 206a. side walls and bottom. Furthermore, a dielectric material layer 310 is disposed in the trench 206a to fill up the trench 206a. In this embodiment, the dielectric material layer 310 may include silicon oxide or undoped polysilicon. Furthermore, in this embodiment, the well region 232 is formed in the second epitaxial layer 206 outside the upper half of each third doped region 212'. The source region 234 with the first conductivity type is formed in each well region 232 on both sides of the gate structure, and forms a vertical diffused metal oxide with the gate structure and the first doped region (serving as the drain region) 200a Half Field Effect Transistor. The third doped region 212' can be formed by an epitaxial growth process.

Please refer to FIG. 4C , which shows a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention, wherein components identical to those in FIG. 2G use the same reference numerals and their descriptions are omitted. In this embodiment, the semiconductor device 20" is similar to the semiconductor device 20 shown in FIG. 2G, except that each third doped region 212" is located in the second epitaxial layer adjacent to the sidewall of each trench 206a Within 206. Moreover, each trench 206 a includes a dielectric material layer 310 and a doped layer 308 between the dielectric material layer 310 and the second epitaxial layer 206 . In this embodiment, the dielectric material layer 310 may include silicon oxide or undoped polysilicon. Furthermore, the third doped region 212 ″ can be formed by performing a drive-in process on the doped layer 308 .

In this embodiment, the well region 232 is formed in the upper half of each third doped region 212″, and extends in the second epitaxial layer 206 outside the trench 206a. The source region 234 having the first conductivity type It is formed in each well region 232 on both sides of the gate structure, and together with the gate structure and the first doped region (serving as the drain region) 200a constitutes a vertical diffused metal oxide half field effect transistor.

Please refer to FIG. 5C , which shows a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present invention, wherein components that are the same as those in FIG. 4C use the same reference numerals and their descriptions are omitted. In this embodiment, the semiconductor device 20"' is similar to the semiconductor device 20" shown in FIG. 4C, except that each third doped region 212"' can be doped by vapor phase doping) or ion implantation (ion implantation) process.

2A to 2G are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device 20 according to an embodiment of the present invention. 2A, a substrate 200 is provided, which has a fourth doped region 200a and a fifth doped region 200b thereon, wherein there is a gap between the fourth doped region 200a and the fifth doped region 200b. Interface B, and the fourth doped region 200a and the fifth doped region 200b have the first conductivity type. The substrate 200 may include an active area A and a terminal area (not shown) surrounding the active area A. Referring to FIG. In one embodiment, the fourth doped region 200a can be made of a doped semiconductor material, and the fifth doped region 200b is grown by epitaxy, and the doped semiconductor material (ie, the fourth doped region 200a) A doped epitaxial layer is formed on it. In another embodiment, different doping processes may be performed on the substrate 200 made of a semiconductor material, so as to form the fourth doped region 200a and the fifth doped region 200b with different doping concentrations therein, The doping process for forming the fourth doped region 200a can be performed after the transistor structure is subsequently formed. In this embodiment, the fourth doped region 200a and the fifth doped region 200b have a first conductivity type, and the fourth doped region 200a can be a heavily doped region, and the fifth doped region 200b can be a lightly doped region.

Next, perform a doping process 201, such as an ion implantation process, to form a plurality of sixth doped regions 201a having a second conductivity type in the fifth doped region 200b of the active region A, wherein the sixth doped regions 201a The doping concentration of is greater than the doping concentration of the fifth doping region 200b, and smaller than the doping concentration of the fourth doping region 200a.

Referring to FIG. 2B, a doping process 203, such as an ion implantation process, is performed to form a plurality of seventh doped regions 203a with the first conductivity type in the fifth doped region 200b of the active region A, wherein the seventh doped regions The impurity regions 203a are alternately arranged with the sixth doped regions 201a. Here, to simplify the drawing, only a seventh doped region 203a and two adjacent sixth doped regions 201a are shown. The doping concentration of the seventh doping region 203a is greater than that of the fifth doping region 200b and smaller than that of the fourth doping region 200a. However, it should be noted that in other embodiments, the doping process 203 may be performed before the doping process 201 is performed.

Referring to FIG. 2C , a plurality of stacked first epitaxial layers 204 are formed on the substrate 200 , and a plurality of first doped regions 204 a and a plurality of second doped regions 204 b are formed in each first epitaxial layer 204 . In this embodiment, the first epitaxial layer 204 has the first conductivity type and has a doping concentration substantially the same as that of the fifth doped region 200b. Furthermore, the first doped regions 204a and the second doped regions 204b are alternately arranged, and respectively correspond to the sixth doped regions 201a and the seventh doped regions 203a below. Here, to simplify the drawing, only a second doped region 204b adjacent to the two first doped regions 204a is shown. The first doped region 204a has the second conductivity type, and the second doped region 204b has the first conductivity type. Furthermore, the fabrication of the first doped region 204a and the second doped region 204b can be similar or identical to the fabrication of the sixth doped region 201a and the seventh doped region 203a, so that the first doped region 204a and the second doped region The doping concentration of the doping region 204b is greater than that of the fifth doping region 200b and smaller than that of the fourth doping region 200a. It should be noted that the number of the first epitaxial layer 204 can be adjusted according to design requirements, not limited to the second layer (as shown in FIG. 2C ).

Referring to FIG. 2D, a second epitaxial layer 206 with a first conductivity type can be formed on the uppermost first epitaxial layer 204 by epitaxial growth, and has a doping concentration greater than that of the fifth doped region 200b. Concentration, and less than the doping concentration of the fourth doping region 200a. A hard mask (hard mask, HM) 208 can be formed on the second epitaxial layer 206 of the active region A by chemical vapor deposition (chemical vapor deposition, CVD), and then a photolithography process and an etching process are performed to form a hard mask on the hard layer 206. A plurality of openings 208a corresponding to the first doped regions 204a are formed in the mask 202 .

Referring to FIG. 2E, an anisotropic etching process is performed to form a plurality of trenches 206a in the second epitaxial layer 206 below the opening 208a. In this embodiment, the trench 206a exposes the underlying first doped region 204a. Next, after removing the hard mask 208, an insulating liner (insulating liner) 210, such as an oxide liner, is conformally formed on the sidewall and bottom of each trench 206a by CVD or thermal oxidation, It can reduce the stress in the second epitaxial layer 206, and can be used as a shielding oxide layer (pre-implant oxide) in the subsequent doping process to reduce the channel effect.

Referring to FIG. 2F , after the insulating liner layer 210 is removed, a third doped region 212 of the second conductivity type may be formed on the sidewall of each trench 206 a. In one embodiment, an epitaxial layer with a second conductivity type can be formed on the second epitaxial layer 206 and in each trench 206a by epitaxial growth. Afterwards, the epitaxial layer above the second epitaxial layer 206 is removed through a polishing process, such as chemical mechanical polishing (CMP). In another embodiment, a polysilicon layer with a second conductivity type can be formed on the second epitaxial layer 206 and in each trench 206 a through an existing deposition process, such as CVD. Afterwards, the polysilicon layer above the second epitaxial layer 206 is removed by a polishing process, such as CMP.

In this embodiment, the doping concentration of the second epitaxial layer 206 , the first doped region 204 a , the second doped region 204 b and the third doped region 212 is greater than the doping concentration of each first epitaxial layer 204 . Furthermore, the doping concentration of the second epitaxial layer 206 and the first doped region 204a, the second doped region 204b, the third doped region 212, the sixth doped region 201a and the seventh doped region 203a is greater than that of the fifth The doping concentration 200b of the doping region is smaller than the doping concentration of the fourth doping region 200a.

In this embodiment, the first conductivity type is N type, and the second conductivity type is P type. However, in other embodiments, the first conductivity type can also be P-type, and the second conductivity type is N-type. Therefore, the second doped region 204b and the seventh doped region 203a having the second conductivity type and the first doped region 204a and the sixth doped region 201a having the first conductivity type are in the fifth doped region 200b and A super junction structure is formed in the first epitaxial layer 204 . Similarly, the second epitaxial layer 206 with the second conductivity type and the third doped region 212 with the first conductivity type also form a super junction structure.

Referring to FIG. 2G , a plurality of gate structures can be formed on the second epitaxial layer 206 through an existing MOS process, and each gate structure is located above the second doped region 204b in the first epitaxial layer 204 . Each gate structure includes a gate dielectric layer 228 and a gate electrode 230 thereon. Furthermore, a well region 232 with the second conductivity type can be formed in the upper half of the third doped region 212 and extend in the second epitaxial layer 206 outside the third doped region 212 . A source region 234 with the first conductivity type is formed in each well region 232 on both sides of the gate structure to complete the manufacture of the semiconductor device 20, wherein the source region 234, the gate structure and the first doped region (as The drain region) 200a constitutes a vertical diffused metal oxide semiconductor field effect transistor.

3A to 3C are cross-sectional schematic diagrams illustrating a manufacturing method of a semiconductor device according to another embodiment of the present invention, wherein components that are the same as those in FIGS. 2A to 2G use the same reference numerals and their descriptions are omitted. Referring to FIG. 3A , the process steps shown in FIG. 2A to FIG. 2E are performed to form the structure shown in FIG. 2E . Next, after removing the insulating liner layer 210, a third doped region 212', such as an epitaxial layer, having the second conductivity type can be formed conformally on the sidewall and bottom of each trench 206a by epitaxial growth. .

Referring to FIG. 3B , a dielectric material layer 310 is filled in each trench 206 a. For example, a dielectric material layer 310, such as silicon oxide or undoped polysilicon, can be formed on the second epitaxial layer 206 and in each trench 206a by a chemical vapor deposition (CVD) process, so that the trench 206a The inner third doped region 212 ′ is located between the dielectric material layer 310 and the second epitaxial layer 206 . After that, the dielectric material layer 310 on the second epitaxial layer 206 is removed by a chemical mechanical polishing (CMP) process, so that the third doped region 212' in the trench 206a is located between the dielectric material layer 310 and the second epitaxial layer 206 between.

3C, a gate structure can be formed on the second epitaxial layer 206 above the second doped region 204b of the first epitaxial layer 204 through the existing MOS process, which includes a gate dielectric layer 228 and The gate electrode 230 thereon. Furthermore, a well region 232 of the second conductivity type can be formed in the second epitaxial layer 206 outside the upper half of each third doped region 212'. A source region 234 with the first conductivity type is formed in each well region 232 on both sides of the gate structure to complete the manufacture of the semiconductor device 20', wherein the source region 234, the gate structure and the fifth doped region ( As the drain region) 200a constitutes a vertical diffused metal oxide half field effect transistor.

4A to 4C are cross-sectional schematic diagrams illustrating a manufacturing method of a semiconductor device according to another embodiment of the present invention, wherein the components that are the same as those in FIGS. 2A to 2G use the same reference numerals and their descriptions are omitted. Referring to FIG. 4A , the process steps shown in FIG. 2A to FIG. 2E are performed to form the structure shown in FIG. 2E . Next, after removing the insulating liner layer 210, a doped layer 308, such as doped silicon glass, having the second conductivity type is formed on the sidewall of each trench 206a. Afterwards, the doped layer 308 is driven in and diffused to form a third doped region 212 ″ in the second epitaxial layer 206 outside the trench 206 a.

Referring to FIG. 4B, a dielectric material layer 310 is filled in each trench 206a. For example, a dielectric material layer 310, such as silicon oxide or undoped polysilicon, can be formed on the second epitaxial layer 206 and in each trench 206a by a chemical vapor deposition (CVD) process, so that the trench 206a The inner doped layer 308 is located between the dielectric material layer 310 and the second epitaxial layer 206 . Afterwards, the dielectric material layer 310 on the second epitaxial layer 206 is removed by a chemical mechanical polishing (CMP) process.

Referring to FIG. 4C, a gate structure can be formed on the second epitaxial layer 206 above the second doped region 204b of the first epitaxial layer 204 through the existing MOS process, which includes a gate dielectric layer 228 and The gate electrode 230 thereon. Furthermore, a well region 232 of the second conductivity type can be formed in the upper half of each third doped region 212 ″, and extends in the second epitaxial layer 206 outside the third doped region 212 ″. Form a source region 234 with the first conductivity type in each well region 232 on both sides of the gate structure, and complete the manufacture of the semiconductor device 20", wherein the source region 234, the gate structure and the fifth doped region ( As the drain region) 200a constitutes a vertical diffused metal oxide half field effect transistor.

5A to 5C are cross-sectional schematic diagrams illustrating a manufacturing method of a semiconductor device according to another embodiment of the present invention, wherein components identical to those in FIGS. 2A to 2G and FIGS. 4A to 4C use the same reference numerals and their descriptions are omitted. Referring to FIG. 5A , the process steps shown in FIG. 2A to FIG. 2E are performed to form the structure shown in FIG. 2E . Next, after removing the insulating liner layer 210, a doping process 408, such as vapor phase doping or ion implantation, is performed on the sidewall of each trench 206a, so that the second epitaxial layer adjacent to the sidewall of the trench 206a 206 to form a third doped region 212"'.

Afterwards, the process steps described in FIG. 4B to FIG. 4C are performed to fill a dielectric material layer 310 (as shown in FIG. 5B ) in each trench 206a, and the second doped A gate structure (including a gate dielectric layer 228 and a gate electrode 230 thereon) is formed on the second epitaxial layer 206 above the impurity region 204b. Furthermore, a well region 232 with the second conductivity type is formed in the upper half of each third doped region 212"', and extends in the second epitaxial layer 206 outside the third doped region 21'2". . A source region 234 having a first conductivity type is formed in each well region 232 on both sides of the gate structure to complete the fabrication of the semiconductor device 20"', as shown in FIG. 5C. The source region 234, the gate structure and The fifth doped region (serving as the drain region) 200a constitutes a vertical diffused metal oxide semiconductor field effect transistor.

According to the above-mentioned embodiment, since the N-type region and the P-type region in the super junction structure formed by the first doped region 204a, the second doped region 204b, the sixth doped region 201a and the seventh doped region 203a can be controlled The doping concentration of the region is used to achieve charge balance, so the above-mentioned superjunction structure can be formed in the lightly doped region (ie, the first epitaxial layer 204 and the fifth doped region 200b), thereby improving the vertical diffusion The withstand voltage of the P-N junction in the metal oxide half field effect transistor can avoid the increase of the on-resistance at the same time.

Moreover, according to the above-mentioned embodiment, since an additional superjunction structure can be formed in the second epitaxial layer 206 on the first epitaxial layer 204, the number of layers of the first epitaxial layer 204 can be reduced, so the process can be simplified and the reduction can be reduced. manufacturing cost.

In addition, according to the above-mentioned embodiment, since the first epitaxial layer 204 has a superjunction structure, the withstand voltage of the P-N junction can be further improved without increasing the depth of the trench in the second epitaxial layer 206, and the corrosion resistance of the P-N junction will not be affected. Deep trenches increase the process difficulty.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined by the claims.

Claims (28)

1. A semiconductor device, characterized in that, comprising: A plurality of first epitaxial layers stacked on a substrate, and the first epitaxial layer and the substrate have a first conductivity type, wherein each first epitaxial layer has at least one first doped region and its Adjacent to at least one second doped region, the first doped region has a second conductivity type, and the second doped region has the first conductivity type; A second epitaxial layer, disposed on the first epitaxial layer, and having the first conductivity type, wherein a groove is formed in the second epitaxial layer, exposing the first doped region below; a third doped region, adjacent to a sidewall of the trench, and having the second conductivity type, wherein the second epitaxial layer and the first, the second, and the third The doping concentration of the doped region is greater than the doping concentration of each first epitaxial layer; and A gate structure is disposed on the second epitaxial layer above the second doped region. 2. The semiconductor device according to claim 1, wherein the substrate has a fourth doped region and a fifth doped region thereon, and there is at least one doped region in the fifth doped region The sixth doped region corresponds to the first doped region and at least one seventh doped region is adjacent to the sixth doped region and corresponds to the second doped region, and wherein the fourth, The fifth and seventh doped regions have the first conductivity type, and the sixth doped region has the second conductivity type. 3. The semiconductor device according to claim 2, wherein the second epitaxial layer and the first, the second, the third, the sixth and the seventh doped regions The doping concentration is greater than the doping concentration of the fifth doping region and smaller than the doping concentration of the fourth doping region. 4. The semiconductor device according to claim 2, wherein the fifth doped region comprises an epitaxial layer. 5. The semiconductor device according to claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type. 6. The semiconductor device according to claim 1, wherein the third doped region is located in the trench. 7. The semiconductor device according to claim 6, wherein the third doped region comprises an epitaxial layer or a polysilicon layer. 8. The semiconductor device according to claim 6, wherein the third doped region comprises an epitaxial layer and is conformably disposed on a sidewall and a bottom of the trench. 9. The semiconductor device as claimed in claim 8, further comprising a dielectric material layer disposed in the trench. 10. The semiconductor device according to claim 9, wherein the dielectric material layer comprises silicon oxide or undoped polysilicon. 11. The semiconductor device according to claim 1, wherein the third doped region is located in the second epitaxial layer. 12. The semiconductor device as claimed in claim 11, further comprising a dielectric material layer disposed in the trench. 13. The semiconductor device according to claim 12, wherein the dielectric material layer comprises silicon oxide or undoped polysilicon. 14. The semiconductor device of claim 12, further comprising a doped layer disposed in the trench and between the dielectric material layer and the second epitaxial layer. 15. A method of manufacturing a semiconductor device, comprising: A plurality of stacked first epitaxial layers are formed on a substrate, and at least one first doped region and at least one second doped region adjacent to it are formed in each first epitaxial layer, wherein the first epitaxial the layer, the substrate and the second doped region have a first conductivity type, and the first doped region has a second conductivity type; forming a second epitaxial layer having the first conductivity type on the first epitaxial layer; forming a trench in the second epitaxial layer to expose the underlying first doped region; A third doped region having the second conductivity type is formed on one sidewall of the trench, wherein the second epitaxial layer is connected to the first, the second, and the third The doping concentration of the doped region is greater than the doping concentration of each first epitaxial layer; and A gate structure is formed on the second epitaxial layer above the second doped region. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the substrate has a fourth doped region and a fifth doped region thereon, and in the fifth doped region having at least one sixth doped region corresponding to the first doped region and at least one seventh doped region adjacent to the sixth doped region and corresponding to the second doped region, and wherein the Fourth, the fifth and seventh doped regions have the first conductivity type, and the sixth doped region has the second conductivity type. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the second epitaxial layer is in contact with the first, the second, the third, the sixth, and the seventh epitaxial layers. The doping concentration of the doping region is greater than that of the fifth doping region and smaller than that of the fourth doping region. 18. The method of manufacturing a semiconductor device according to claim 16, wherein the fifth doped region comprises an epitaxial layer. 19. The method of manufacturing a semiconductor device according to claim 15, wherein the first conductivity type is N-type, and the second conductivity type is P-type. 20. The method of manufacturing a semiconductor device according to claim 15, wherein the step of forming the third doped region comprises filling an epitaxial layer or a polysilicon layer in the trench. 21. The method of manufacturing a semiconductor device according to claim 15, wherein the step of forming the third doped region comprises conformally forming an epitaxial layer on a sidewall and a bottom of the trench. 22. The method of manufacturing a semiconductor device as claimed in claim 21, further comprising filling a dielectric material layer in the trench. 23. The method for manufacturing a semiconductor device according to claim 22, wherein the dielectric material layer comprises silicon oxide or undoped polysilicon. 24. The method for manufacturing a semiconductor device according to claim 15, wherein the step of forming the third doped region comprises: forming a doped layer of the second conductivity type on the sidewalls of the trench; and Driving-in diffusion is performed on the doped layer to form the third doped region in the second epitaxial layer. 25. The method for manufacturing a semiconductor device according to claim 24, further comprising forming a dielectric material layer in the trench, so that the doped layer is located between the dielectric material layer and the Between the second epitaxial layer. 26. The method for manufacturing a semiconductor device according to claim 15, wherein the step of forming the third doped region comprises performing vapor phase doping or ion implantation on the sidewall of the trench to The third doped region is formed in the second epitaxial layer. 27. The method of manufacturing a semiconductor device as claimed in claim 26, further comprising forming a dielectric material layer in the trench. 28. The method of manufacturing a semiconductor device as claimed in claim 15, further comprising forming an insulating liner layer in the trench before forming the third doped region.