CN103208510A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN103208510A CN103208510A CN2012100138455A CN201210013845A CN103208510A CN 103208510 A CN103208510 A CN 103208510A CN 2012100138455 A CN2012100138455 A CN 2012100138455A CN 201210013845 A CN201210013845 A CN 201210013845A CN 103208510 A CN103208510 A CN 103208510A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000003989 dielectric material Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 12
- 230000005669 field effect Effects 0.000 description 16
- 229910044991 metal oxide Inorganic materials 0.000 description 16
- 150000004706 metal oxides Chemical class 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a semiconductor device, which comprises: a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The first epitaxial layer is stacked on a substrate and has a first conductive type. Each first epitaxial layer is internally provided with at least one first doped region and at least one second doped region adjacent to the first doped region, the first doped region is provided with a second conductive type, and the second doped region is provided with the first conductive type. The second epitaxial layer is disposed on the first epitaxial layer and has a first conductivity type. The second epitaxial layer has a trench therein, and a third doped region adjacent to a sidewall of the trench and having the second conductivity type. The gate structure is disposed on the second epitaxial layer above the second doped region. The invention also discloses a method for manufacturing the semiconductor device. According to the semiconductor device and the manufacturing method thereof provided by the embodiment of the invention, the increase of the on-resistance can be avoided, the process can be simplified, and the manufacturing cost can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly have super semiconductor device and a manufacture method thereof that connects face (super junction) structure relevant for a kind of.
Background technology
Fig. 1 shows the rectilinear diffuse metal oxide of existing N-type half field effect transistor (vertical double-diffused MOSFET, VDMOSFET) generalized section.The rectilinear diffuse metal oxide of N-type half field effect transistor 10 comprises: semiconductor substrate and a grid structure that is located thereon.Have P mold base (base) district 102 of a N-type extension (epitaxy) drift (drift region) district 100 and the side of being located thereon at semiconductor-based the end and form P-N and connect face.Moreover 100 belows, N-type extension drift region have a drain region 106, and it is connected to a drain electrode 114.Have one source pole district 104 in the P mold base district 102, it is connected to one source pole electrode 112.Grid structure is made of a gate dielectric 108 and the gate electrode 110 that is located thereon.
In order to promote withstand voltage (the withstand voltage) that P-N in the rectilinear diffuse metal oxide of the N-type half field effect transistor 10 connects face, must reduce the doping content of N-type extension drift region 100 and/or promote its thickness.Yet, when promoting P-N in the above described manner and connecing face withstand voltage, also can increase the conducting resistance (Ron) of the rectilinear diffuse metal oxide of N-type half field effect transistor 10 simultaneously.That is conducting resistance can be subjected to the doping content of N-type extension drift region and the restriction of thickness.
Have the super rectilinear diffuse metal oxide half field effect transistor that connects face (Super-junction) structure and can improve the dopant concentration of N-type extension drift region, and then promote P-N and connect the withstand voltage of face, can avoid the increase of conducting resistance simultaneously.Yet because existing super contact structure need carry out repeatedly epitaxial growth, and the number of times of epitaxial growth depends on that P-N connects the withstand voltage size of face, and therefore, the manufacturing of above-mentioned super contact structure has shortcomings such as the complicated and manufacturing cost height of technology.
Therefore, be necessary to seek a kind of semiconductor device with super contact structure, it can improve or address the above problem.
Prior art:
The rectilinear diffuse metal oxide of 10～N-type half field effect transistor;
100～N-type extension drift region;
102～P mold base district;
104～source area;
106～drain region;
108～grid electrode layer;
110～gate electrode;
112～source electrode;
114～drain electrode.
Summary of the invention
One embodiment of the invention provides a kind of semiconductor device, comprise: a plurality of first epitaxial loayers, be stacked and placed in the substrate, and first epitaxial loayer and substrate have one first conduction type, at least one second doped region that has at least one first doped region in each first epitaxial loayer and be adjacent wherein, first doped region has one second conduction type, and second doped region has first conduction type; One second epitaxial loayer is arranged on first epitaxial loayer, and has first conduction type, wherein has a groove in second epitaxial loayer, exposes first doped region of below; One the 3rd doped region is adjacent to a sidewall of groove, and has second conduction type, wherein second epitaxial loayer and first, second, and the doping content of the 3rd doped region greater than the doping content of first epitaxial loayer; And a grid structure, be arranged on second epitaxial loayer of second doped region top.
Another embodiment of the present invention provides a kind of manufacture method of semiconductor device, comprise: form stacked a plurality of first epitaxial loayers in a substrate, and at least one second doped region that in each first epitaxial loayer, forms at least one first doped region and be adjacent, wherein first epitaxial loayer, substrate and second doped region have one first conduction type, and first doped region has one second conduction type; Form one second epitaxial loayer at first epitaxial loayer, it has first conduction type; In second epitaxial loayer, form a groove, to expose first doped region of below; Form one the 3rd doped region at a sidewall of groove, it has second conduction type, wherein second epitaxial loayer with first, second, reach the doping content of the 3rd doped region greater than the doping content of each first epitaxial loayer; And second epitaxial loayer above second doped region forms a grid structure.
According to semiconductor device and the manufacture method of the embodiment of the invention, can avoid the increase of conducting resistance, and can simplify technology and reduce manufacturing cost.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, does not constitute limitation of the invention.In the accompanying drawings:
Fig. 1 shows the rectilinear diffuse metal oxide of existing N-type half field effect transistor generalized section.
Fig. 2 A to Fig. 2 G shows the manufacture method generalized section of semiconductor device according to an embodiment of the invention.
Fig. 3 A to Fig. 3 C shows the manufacture method generalized section of semiconductor device according to another embodiment of the present invention.
Fig. 4 A to Fig. 4 C shows the manufacture method generalized section of semiconductor device according to another embodiment of the present invention.
Fig. 5 A to Fig. 5 C shows the manufacture method generalized section of semiconductor device according to another embodiment of the present invention.
Drawing reference numeral:
Embodiment:
20,20 ', 20 ", 20 " '～semiconductor device;
200～substrate;
200a～the 4th doped region;
200b～the 5th doped region;
201,203,408～doping process;
201a～the 6th doped region;
203a～the 7th doped region;
204～the first epitaxial loayers;
204a～first doped region;
204b～second doped region;
206～the second epitaxial loayers;
206a～groove;
208～hard mask;
208a～opening;
210～insulation liner layer;
212,212 ', 212 ", 212 " '～the 3rd doped region;
308～doped layer;
310～dielectric materials layer;
228～gate dielectric;
230～gate electrode;
232～wellblock;
234～source area;
A～active region;
B～interface.
Embodiment
Semiconductor device and the manufacture method thereof of the embodiment of the invention below are described.Yet, can understand embodiment provided by the present invention easily and only be used for explanation with the ad hoc approach making and use the present invention, be not in order to limit to scope of the present invention.
Please refer to Fig. 2 G, it shows semiconductor device generalized section according to an embodiment of the invention.The semiconductor device 20 of the embodiment of the invention comprises the rectilinear diffuse metal oxide half field effect transistor (VDMOSFET) with super contact structure.In the present embodiment, semiconductor device 20 comprises: a plurality of first epitaxial loayers 204, one second epitaxial loayer 206 and at least one grid structure.First epitaxial loayer 204 is stacked and placed in the substrate 200, and each first epitaxial loayer 204 and substrate 200 have one first conduction type.Shown in Fig. 2 G, substrate 200 can comprise an active region (active region) A and distinguish (not illustrating) around the terminal (termination) of active region A.In one embodiment, active region A provides semiconductor element formed thereon, and the termination environment is as the insulation between the different semiconductor devices.
The a plurality of second doped region 204b that have a plurality of first doped region 204a in each first epitaxial loayer 204 and alternately arrange with the first doped region 204a, make each second doped region 204b adjacent with at least one first doped region 204a, perhaps each first doped region 204a is adjacent with at least one second doped region 204b.Herein, for simplicity of illustration, two first doped region 204a that only show one second doped region 204b and be adjacent.Moreover the first doped region 204a has one second conduction type that is different from first conduction type, and the second doped region 204b has first conduction type.
Second epitaxial loayer 206 is arranged on the first stacked epitaxial loayer 204, and has first conduction type.Have a plurality of groove 206a in second epitaxial loayer 206, and each groove 206a is corresponding to each first doped region 204a of below, and the first corresponding doped region 204a is exposed in the bottom of each groove 206a.Moreover a plurality of the 3rd doped regions 212 are corresponding to groove 206a, and each the 3rd doped region 212 is adjacent to the sidewall of corresponding groove 206a.In the present embodiment, the 3rd doped region 212 is positioned at corresponding groove 206a, and comprises an epitaxial loayer or a polysilicon layer.Moreover the doping content of second epitaxial loayer 206 and the first doped region 204a, the second doped region 204b and the 3rd doped region 212 is greater than the doping content of each first epitaxial loayer 204.
In the present embodiment, one the 5th doped region 200b that substrate 200 has one the 4th doped region 200a and is located thereon wherein has an interface B between the 4th assorted district 200a and the 5th doped region 200b.In one embodiment, the 4th doped region 200a can be made of the semiconductor material, and the 5th doped region 200b then is made of epitaxial loayer.In another embodiment, having the 4th doped region 200a of different levels of doping and the 5th doped region 200b is formed in the substrate 200 that same semi-conducting material constitutes.
In the present embodiment, the 4th doped region 200a and the 5th doped region 200b have first conduction type, and the 4th doped region 200a can be a heavily doped region, and the 5th doped region 200b can be a light doping section.Moreover, a plurality of the 7th doped region 203a that have a plurality of the 6th doped region 201a in the 5th doped region 200b and alternately arrange with the 6th doped region 201a, make each the 7th doped region 203a adjacent with at least one the 6th doped region 201a, perhaps each the 6th doped region 201a is adjacent with at least one the 7th doped region 203a.Herein, for simplicity of illustration, two the 6th doped region 201a that only show one the 7th doped region 203a and be adjacent.
In the present embodiment, the 6th doped region 201a corresponding to the first doped region 204a and the 7th doped region 203a corresponding to the second doped region 204b.Moreover, the doping content of first epitaxial loayer 204 can be same as the 5th doped region 200b substantially, and the doping content of second epitaxial loayer 206 and the first doped region 204a, the second doped region 204b, the 3rd doped region 212, the 6th doped region 201a and the 7th doped region 203a is greater than the doping content of the 5th doped region 200b, and less than the doping content of the 4th doped region 200a.
In the present embodiment, first conduction type is N-type, and second conduction type is the P type.Yet in other embodiments, first conduction type also can be the P type, and second conduction type is N-type.Therefore, has the second doped region 204b of first conduction type and the 7th doped region 203a and the first doped region 204a with second conduction type and the 6th doped region 201a super contact structure of formation in the 5th doped region 200b and in first epitaxial loayer 204.Similarly, second epitaxial loayer 206 with first conduction type also forms super contact structure with the 3rd doped region 212 with second conduction type.
One grid structure is arranged on second epitaxial loayer 206 and corresponding to the second doped region 204b in each first epitaxial loayer 204, comprises a gate dielectric 228 and the gate electrode 230 that is located thereon.Moreover the wellblock 232 with second conduction type is formed at the first half of each the 3rd doped region 212, and extends in second epitaxial loayer 206 in the groove 206a outside.Source area 234 with first conduction type is formed in each wellblock 232, grid structure both sides, and constitutes a rectilinear diffuse metal oxide half field effect transistor with grid structure and the 4th doped region (as the drain region) 200a.
Please refer to Fig. 3 C, it shows semiconductor device generalized section according to another embodiment of the present invention, and the parts that wherein are same as Fig. 2 G use identical label and omit its explanation.In the present embodiment, semiconductor device 20 ' is similar in appearance to the semiconductor device 20 shown in Fig. 2 G, and difference is each the 3rd doped region 212 ', epitaxial loayer for example, compliance be arranged at corresponding groove 206a sidewall and bottom.Moreover a dielectric materials layer 310 is arranged in the groove 206a, to fill up groove 206a.In the present embodiment, dielectric materials layer 310 can comprise silica or unadulterated polysilicon.Moreover in the present embodiment, wellblock 232 is formed in second epitaxial loayer 206 in the first half outside of each the 3rd doped region 212 '.Source area 234 with first conduction type is formed in each wellblock 232, grid structure both sides, and constitutes a rectilinear diffuse metal oxide half field effect transistor with grid structure and first doped region (as the drain region) 200a.The 3rd doped region 212 ' can form by epitaxial growth technology.
Please refer to Fig. 4 C, it shows semiconductor device generalized section according to another embodiment of the present invention, and the parts that wherein are same as Fig. 2 G use identical label and omit its explanation.In the present embodiment, semiconductor device 20 " similar in appearance to the semiconductor device 20 shown in Fig. 2 G, difference is each the 3rd doped region 212 " be positioned at second epitaxial loayer 206 of the sidewall of contiguous each groove 206a.Moreover, comprise a dielectric materials layer 310 and the doped layer 308 between dielectric materials layer 310 and second epitaxial loayer 206 in each groove 206a.In the present embodiment, dielectric materials layer 310 can comprise silica or unadulterated polysilicon.Moreover, the 3rd doped region 212 " can form into diffusion (drive in) technology by doped layer 308 is become.
In the present embodiment, wellblock 232 is formed at each the 3rd doped region 212 " the first half, and extend in second epitaxial loayer 206 in the groove 206a outside.Source area 234 with first conduction type is formed in each wellblock 232, grid structure both sides, and constitutes a rectilinear diffuse metal oxide half field effect transistor with grid structure and first doped region (as the drain region) 200a.
Please refer to Fig. 5 C, the semiconductor device generalized section that it shows according to the present invention again another embodiment, the parts that wherein are same as Fig. 4 C use identical label and omit its explanation.In the present embodiment, semiconductor device 20 " ' similar in appearance to the semiconductor device 20 shown in Fig. 4 C ", difference is each the 3rd doped region 212 " ' can form by groove being carried out vapour phase doping (vapor phase doping) or ion injection (ion implantation) technology.
Fig. 2 A to Fig. 2 G shows the manufacture method generalized section of semiconductor device 20 according to an embodiment of the invention.Please refer to Fig. 2 A, one substrate 200 is provided, one the 5th doped region 200b that it has one the 4th doped region 200a and is located thereon wherein has an interface B between the 4th doped region 200a and the 5th doped region 200b, and the 4th doped region 200a and the 5th doped region 200b have first conduction type.Substrate 200 can comprise an active region A and center on the termination environment (not illustrating) of active region A.In one embodiment, the 4th doped region 200a can be made of a semi-conducting material that mixes, and the 5th doped region 200b is then by epitaxial growth, goes up the epitaxial loayer that forms a doping and constitutes at the semi-conducting material (that is the 4th doped region 200a) that mixes.In another embodiment, can carry out different doping processs to the substrate 200 that is constituted by the semiconductor material, to form the 4th doped region 200a and the 5th doped region 200b with different levels of doping within it, the doping process that wherein is used to form the 4th doped region 200a can carry out after follow-up formation transistor arrangement.In the present embodiment, the 4th doped region 200a and the 5th doped region 200b have one first conduction type, and the 4th doped region 200a can be a heavily doped region, and the 5th doped region 200b can be a light doping section.
Then, carry out a doping process 201, ion implantation technology for example, in the 5th doped region 200b of active region A, to form a plurality of the 6th doped region 201a with second conduction type, wherein the doping content of the 6th doped region 201a is greater than the doping content of the 5th doped region 200b, and less than the doping content of the 4th doped region 200a.
Please refer to Fig. 2 B, carry out a doping process 203, ion implantation technology for example is to form a plurality of the 7th doped region 203a with first conduction type, wherein alternately arrangement of the 7th doped region 203a and the 6th doped region 201a in the 5th doped region 200b of active region A.Herein, for simplicity of illustration, two the 6th doped region 201a that only show one the 7th doped region 203a and be adjacent.The doping content of the 7th doped region 203a is greater than the doping content of the 5th doped region 200b, and less than the doping content of the 4th doped region 200a.Yet, be noted that in other embodiments, can before carrying out doping process 201, carry out doping process 203.
Please refer to Fig. 2 C, form stacked a plurality of first epitaxial loayers 204 in substrate 200, and in each first epitaxial loayer 204, form a plurality of first doped region 204a and a plurality of second doped region 204b.In the present embodiment, first epitaxial loayer 204 has first conduction type and has a doping content and is same as the 5th doped region 200b substantially.Moreover the first doped region 204a and the second doped region 204b alternately arrange, and correspond respectively to the 6th doped region 201a and the 7th doped region 203a of below.Herein, for simplicity of illustration, only show and two one second doped region 204b that the first doped region 204a is adjacent.The first doped region 204a has second conduction type, and the second doped region 204b has first conduction type.Moreover, manufacturing of the first doped region 204a and the second doped region 204b can be similar or be same as the making of the 6th doped region 201a and the 7th doped region 203a, make the doping content of the first doped region 204a and the second doped region 204b greater than the doping content of the 5th doped region 200b, and less than the doping content of the 4th doped region 200a.Be noted that and adjust the quantity of first epitaxial loayer 204 according to design requirement, and be not limited to two layers (shown in Fig. 2 C).
Please refer to Fig. 2 D, can pass through epitaxial growth, first epitaxial loayer 204 in the superiors forms one second epitaxial loayer 206 with first conduction type, and it has a doping content greater than the doping content of the 5th doped region 200b, and less than the doping content of the 4th doped region 200a.Can be by chemical vapour deposition (CVD) (chemical vapor deposition, CVD), above second epitaxial loayer 206 of active region A, form a hard mask (hard mask, HM) 208, then carry out photoetching process and etching technics, in hard mask 202, to form a plurality of opening 208a of the corresponding first doped region 204a.
Please refer to Fig. 2 E, carry out an anisotropic etching technics, to form a plurality of groove 206a in second epitaxial loayer 206 below opening 208a.In the present embodiment, groove 206a exposes the first doped region 204a of below.Then, can be after removing hard mask 208, by CVD or thermal oxidation method, sidewall and bottom compliance at each groove 206a form an insulation liner layer (insulating liner) 210, oxide liner layer for example, it can reduce the stress in second epitaxial loayer 206, and can be as the screen oxide (pre-implant oxide) of follow-up doping process, to reduce channelling effect.
Please refer to Fig. 2 F, after removing insulation liner layer 210, can form the 3rd doped region 212 with second conduction type at the sidewall of each groove 206a.In one embodiment, can pass through epitaxial growth, form the epitaxial loayer with one second conduction type above second epitaxial loayer 206 and in each groove 206a.Afterwards, by grinding technics, for example (chemical mechanical polishing CMP), removes the epitaxial loayer of second epitaxial loayer, 206 tops to cmp again.In another embodiment, can be by existing depositing operation, for example CVD forms the polysilicon layer with one second conduction type above second epitaxial loayer 206 and in each groove 206a.Afterwards, again by grinding technics, CMP for example removes the polysilicon layer of second epitaxial loayer, 206 tops.
In the present embodiment, the doping content of second epitaxial loayer 206 and the first doped region 204a, the second doped region 204b and the 3rd doped region 212 is greater than the doping content of each first epitaxial loayer 204.Moreover, the doping content of second epitaxial loayer 206 and the first doped region 204a, the second doped region 204b, the 3rd doped region 212, the 6th doped region 201a and the 7th doped region 203a is greater than the doping content 200b of the 5th doped region, and less than the doping content of the 4th doped region 200a.
In the present embodiment, first conduction type is N-type, and second conduction type is the P type.Yet in other embodiments, first conduction type also can be the P type, and second conduction type is N-type.Therefore, has the second doped region 204b of second conduction type and the 7th doped region 203a and the first doped region 204a with first conduction type and the 6th doped region 201a super contact structure of formation in the 5th doped region 200b and in first epitaxial loayer 204.Similarly, second epitaxial loayer 206 with second conduction type also forms super contact structure with the 3rd doped region 212 with first conduction type.
Please refer to Fig. 2 G, can form a plurality of grid structures at second epitaxial loayer 206 by existing MOS technology, and each grid structure is positioned at the second doped region 204b top of first epitaxial loayer 204.Each grid structure comprises a gate dielectric 228 and the gate electrode 230 that is located thereon.Moreover, can have a wellblock 232 of second conduction type in the first half formation of the 3rd doped region 212, and extend in second epitaxial loayer 206 in the 3rd doped region 212 outsides.In each wellblock 232, grid structure both sides, form the source area 234 with first conduction type, and finish manufacturing of semiconductor device 20, wherein source area 234, grid structure and first doped region (as the drain region) 200a constitute a rectilinear diffuse metal oxide half field effect transistor.
Fig. 3 A to Fig. 3 C shows the manufacture method generalized section of semiconductor device according to another embodiment of the present invention, and the parts that wherein are same as Fig. 2 A to Fig. 2 G use identical label and omit its explanation.Please refer to Fig. 3 A, carry out the processing step as Fig. 2 A to Fig. 2 E, to form the structure shown in Fig. 2 E.Then, after removing insulation liner layer 210, can pass through epitaxial growth, form one the 3rd doped region 212 ' in sidewall and the bottom compliance of each groove 206a, an epitaxial loayer for example, it has second conduction type.
Please refer to Fig. 3 B, in each groove 206a, insert a dielectric materials layer 310.For instance, can pass through chemical vapor deposition (CVD) technology, in second epitaxial loayer 206 and each groove 206a, form a dielectric materials layer 310, for example silica or unadulterated polysilicon make the 3rd interior doped region 212 ' of groove 206a between dielectric materials layer 310 and second epitaxial loayer 206.Afterwards, remove dielectric materials layer 310 on second epitaxial loayer 206 with cmp (CMP) technology, make the 3rd doped region 212 ' in the groove 206a between dielectric materials layer 310 and second epitaxial loayer 206.
Please refer to Fig. 3 C, can be by existing MOS technology, second epitaxial loayer 206 above the second doped region 204b of first epitaxial loayer 204 forms a grid structure, and it comprises a gate dielectric 228 and the gate electrode 230 that is located thereon.Moreover, can form the wellblock 232 with second conduction type in second epitaxial loayer 206 outside the first half of each the 3rd doped region 212 '.In each wellblock 232, grid structure both sides, form the source area 234 with first conduction type, and finish manufacturing of semiconductor device 20 ', wherein source area 234, grid structure and the 5th doped region (as the drain region) 200a constitute a rectilinear diffuse metal oxide half field effect transistor.
Fig. 4 A to Fig. 4 C shows the manufacture method generalized section of semiconductor device according to another embodiment of the present invention, and the parts that wherein are same as Fig. 2 A to Fig. 2 G use identical label and omit its explanation.Please refer to Fig. 4 A, carry out the processing step as Fig. 2 A to Fig. 2 E, to form the structure shown in Fig. 2 E.Then, after removing insulation liner layer 210, form a doped layer 308 at the sidewall of each groove 206a, the silex glass of Can Zaing for example, it has second conduction type.Afterwards, doped layer 308 is driven in diffusion, in second epitaxial loayer 206 in the groove 206a outside, to form the 3rd doped region 212 ".
Please refer to Fig. 4 B, in each groove 206a, insert a dielectric materials layer 310.For instance, can pass through chemical vapor deposition (CVD) technology, form a dielectric materials layer 310 in second epitaxial loayer 206 and each groove 206a, for example silica or unadulterated polysilicon make the interior doped layer 308 of groove 206a between dielectric materials layer 310 and second epitaxial loayer 206.Afterwards, remove dielectric materials layer 310 on second epitaxial loayer 206 with cmp (CMP) technology.
Please refer to Fig. 4 C, can be by existing MOS technology, second epitaxial loayer 206 above the second doped region 204b of first epitaxial loayer 204 forms a grid structure, and it comprises a gate dielectric 228 and the gate electrode 230 that is located thereon.Moreover, can be at each the 3rd doped region 212 " the first half form and have a wellblock 232 of second conduction type, and extend the 3rd doped region 212 " in second epitaxial loayer 206 in the outside.In each wellblock 232, grid structure both sides, form the source area 234 with first conduction type, and finish semiconductor device 20 " manufacture, wherein source area 234, grid structure and the 5th doped region (as the drain region) 200a constitute a rectilinear diffuse metal oxide half field effect transistor.
Fig. 5 A to Fig. 5 C shows the manufacture method generalized section of semiconductor device according to another embodiment of the present invention, and the parts that wherein are same as Fig. 2 A to Fig. 2 G and Fig. 4 A to Fig. 4 C use identical label and omit its explanation.Please refer to Fig. 5 A, carry out the processing step as Fig. 2 A to Fig. 2 E, to form the structure shown in Fig. 2 E.Then, after removing insulation liner layer 210, the sidewall of each groove 206a is carried out a doping process 408, for example vapour phase is mixed or ion injects, with formation the 3rd doped region 212 in second epitaxial loayer 206 of the sidewall of adjacent trenches 206a " '.
Afterwards, carry out the described processing step as Fig. 4 B to Fig. 4 C, inserting a dielectric materials layer 310 (shown in Fig. 5 B) in each groove 206a, and second epitaxial loayer 206 above the second doped region 204b of first epitaxial loayer 204 forms grid structures (it comprises a gate dielectric 228 and the gate electrode 230 that is located thereon).Moreover, at each the 3rd doped region 212 " ' the first half form and to have a wellblock 232 of second conduction type, and extend the 3rd doped region 21 ' 2 " in second epitaxial loayer 206 in the outside.In each wellblock 232, grid structure both sides, form and have the source area 234 of first conduction type, and finish semiconductor device 20 " ' manufacture, shown in Fig. 5 C.Source area 234, grid structure and the 5th doped region (as the drain region) 200a constitute a rectilinear diffuse metal oxide half field effect transistor.
According to above-described embodiment, because can the doping content in N-type zone and p type island region territory reaches charge balance (charge balance) in the super contact structure that the first doped region 204a, the second doped region 204b, the 6th doped region 201a and the 7th doped region 203a constitute by controlling, therefore above-mentioned super contact structure can be formed at light doping section (namely, first epitaxial loayer 204 and the 5th doped region 200b) in, and then promote that P-N connects the withstand voltage of face in the rectilinear diffuse metal oxide half field effect transistor, can avoid the increase of conducting resistance simultaneously.
Moreover, according to above-described embodiment, owing to can form extra super contact structure in second epitaxial loayer 206 on first epitaxial loayer 204, therefore can reduce the number of plies of first epitaxial loayer 204, therefore can simplify technology and reduce manufacturing cost.
Therefore in addition, according to above-described embodiment, owing to have super contact structure in first epitaxial loayer 204, need not to increase gash depths in second epitaxial loayer 206 and just can further promote P-N and connect the withstand voltage of face, and can not increase the difficulty in process degree because of the etching deep trench.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is as the criterion when looking the claim scope person of defining.
Claims (28)
1. a semiconductor device is characterized in that, comprising:
A plurality of first epitaxial loayers, be stacked and placed in the substrate, and described first epitaxial loayer and described substrate have one first conduction type, at least one second doped region that has at least one first doped region in each first epitaxial loayer and be adjacent wherein, described first doped region has one second conduction type, and described second doped region has described first conduction type;
One second epitaxial loayer is arranged on described first epitaxial loayer, and has described first conduction type, has a groove in wherein said second epitaxial loayer, exposes described first doped region of below;
One the 3rd doped region is adjacent to a sidewall of described groove, and has described second conduction type, wherein said second epitaxial loayer and described first, described second, and the doping content of described the 3rd doped region greater than the doping content of each first epitaxial loayer; And
One grid structure is arranged on described second epitaxial loayer of described second doped region top.
2. semiconductor device as claimed in claim 1, it is characterized in that, one the 5th doped region that described substrate has one the 4th doped region and is located thereon, and have in described the 5th doped region at least one the 6th doped region corresponding to described first doped region and at least one the 7th doped region adjacent to described the 6th doped region and corresponding to described second doped region, and the wherein said the 4th, the described the 5th and described the 7th doped region have described first conduction type, and described the 6th doped region and have described second conduction type.
3. semiconductor device as claimed in claim 2, it is characterized in that, described second epitaxial loayer and described first, described second, the described the 3rd, the described the 6th and the doping content of described the 7th doped region greater than the doping content of described the 5th doped region, and less than the doping content of described the 4th doped region.
4. semiconductor device as claimed in claim 2 is characterized in that, described the 5th doped region comprises an epitaxial loayer.
5. semiconductor device as claimed in claim 1 is characterized in that, described first conduction type is N-type, and described second conduction type is the P type.
6. semiconductor device as claimed in claim 1 is characterized in that, described the 3rd doped region is positioned at described groove.
7. semiconductor device as claimed in claim 6 is characterized in that, described the 3rd doped region comprises an epitaxial loayer or a polysilicon layer.
8. semiconductor device as claimed in claim 6 is characterized in that, described the 3rd doped region comprises that an epitaxial loayer and compliance are arranged on the sidewall and a bottom of described first groove.
9. semiconductor device as claimed in claim 8 is characterized in that, more comprises a dielectric materials layer, is arranged in the described groove.
10. semiconductor device as claimed in claim 9 is characterized in that, described dielectric materials layer comprises silica or unadulterated polysilicon.
11. semiconductor device as claimed in claim 1 is characterized in that, described the 3rd doped region is positioned at described second epitaxial loayer.
12. semiconductor device as claimed in claim 11 is characterized in that, more comprises a dielectric materials layer, is arranged in the described groove.
13. semiconductor device as claimed in claim 12 is characterized in that, described dielectric materials layer comprises silica or unadulterated polysilicon.
14. semiconductor device as claimed in claim 12 is characterized in that, more comprises a doped layer, be arranged in the described groove, and between described dielectric materials layer and described second epitaxial loayer.
15. the manufacture method of a semiconductor device is characterized in that, comprising:
At least one second doped region that forms stacked a plurality of first epitaxial loayers and in each first epitaxial loayer, form at least one first doped region and be adjacent in a substrate, wherein said first epitaxial loayer, described substrate and described second doped region have one first conduction type, and described first doped region has one second conduction type;
Form one second epitaxial loayer at described first epitaxial loayer, it has described first conduction type;
In described second epitaxial loayer, form a groove, to expose described first doped region of below;
Form one the 3rd doped region at a sidewall of described groove, it has described second conduction type, wherein said second epitaxial loayer with described first, described second, reach the doping content of described the 3rd doped region greater than the doping content of each first epitaxial loayer; And
Described second epitaxial loayer above described second doped region forms a grid structure.
16. the manufacture method of semiconductor device as claimed in claim 15, it is characterized in that, one the 5th doped region that described substrate has one the 4th doped region and is located thereon, and have in described the 5th doped region at least one the 6th doped region corresponding to described first doped region and at least one the 7th doped region adjacent to described the 6th doped region and corresponding to described second doped region, and the wherein said the 4th, the described the 5th and described the 7th doped region have described first conduction type, and described the 6th doped region and have described second conduction type.
17. the manufacture method of semiconductor device as claimed in claim 16, it is characterized in that, described second epitaxial loayer and described first, described second, the described the 3rd, the described the 6th and the doping content of described the 7th doped region greater than the doping content of described the 5th doped region, and less than the doping content of described the 4th doped region.
18. the manufacture method of semiconductor device as claimed in claim 16 is characterized in that, described the 5th doped region comprises an epitaxial loayer.
19. the manufacture method of semiconductor device as claimed in claim 15 is characterized in that, described first conduction type is N-type, and described second conduction type is the P type.
20. the manufacture method of semiconductor device as claimed in claim 15 is characterized in that, the step that forms described the 3rd doped region is included in and inserts an epitaxial loayer or a polysilicon layer in the described groove.
21. the manufacture method of semiconductor device as claimed in claim 15 is characterized in that, the step that forms described the 3rd doped region is included in that compliance forms an epitaxial loayer on a sidewall of described groove and the bottom.
22. the manufacture method of semiconductor device as claimed in claim 21 is characterized in that, more is included in and inserts a dielectric materials layer in the described groove.
23. the manufacture method of semiconductor device as claimed in claim 22 is characterized in that, described dielectric materials layer comprises silica or unadulterated polysilicon.
24. the manufacture method of semiconductor device as claimed in claim 15 is characterized in that, the step that forms described the 3rd doped region comprises:
Described sidewall at described groove forms a doped layer, and it has described second conduction type; And
Described doped layer is driven in diffusion, in described second epitaxial loayer, to form described the 3rd doped region.
25. the manufacture method of semiconductor device as claimed in claim 24 is characterized in that, more is included in to form a dielectric materials layer in the described groove, makes described doped layer between described dielectric materials layer and described second epitaxial loayer.
26. the manufacture method of semiconductor device as claimed in claim 15, it is characterized in that, the step that forms described the 3rd doped region comprises that the described sidewall to described groove carries out vapour phase doping or ion injection, to form described the 3rd doped region in described second epitaxial loayer.
27. the manufacture method of semiconductor device as claimed in claim 26 is characterized in that, more is included in and forms a dielectric materials layer in the described groove.
28. the manufacture method of semiconductor device as claimed in claim 15 is characterized in that, more is included in to form before described the 3rd doped region, forms an insulation liner layer in described groove.
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| CN101308875A (en) * | 2007-05-14 | 2008-11-19 | 株式会社电装 | Semiconductor device with super junction structure and manufacturing method thereof |
| US20090140330A1 (en) * | 2007-12-04 | 2009-06-04 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN101471264A (en) * | 2007-12-28 | 2009-07-01 | 万国半导体股份有限公司 | High voltage structures and methods for vertical power devices with improved manufacturability |
| CN102117830A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Semi-insulating column super-junction MOSFET structure |
| US20110298045A1 (en) * | 2010-06-02 | 2011-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned contact for trench mosfet |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308875A (en) * | 2007-05-14 | 2008-11-19 | 株式会社电装 | Semiconductor device with super junction structure and manufacturing method thereof |
| US20090140330A1 (en) * | 2007-12-04 | 2009-06-04 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN101471264A (en) * | 2007-12-28 | 2009-07-01 | 万国半导体股份有限公司 | High voltage structures and methods for vertical power devices with improved manufacturability |
| CN102117830A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Semi-insulating column super-junction MOSFET structure |
| US20110298045A1 (en) * | 2010-06-02 | 2011-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned contact for trench mosfet |
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