CN103208509B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, the semiconductor device comprises: a substrate, first and second epitaxial layers, and a gate structure. The substrate has a first doped region and a second doped region located thereon, wherein the first and second doped regions have a first conductivity type, and the second doped region has at least one first trench therein and at least one second trench adjacent thereto. The first epitaxial layer is arranged in the first groove and has a second conductive type. The second epitaxial layer is arranged in the second groove and has the first conductive type, wherein the second epitaxial layer has a doping concentration which is greater than that of the second doping region and is less than that of the first doping region. The gate structure is disposed above the second trench.

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device, in particular to a semiconductor device with a superjunction structure and a manufacturing method thereof.

Background technique

FIG. 1 is a schematic cross-sectional view of a conventional N-type vertical double-diffused MOSFET (VDMOSFET). The N-type VMOS field effect transistor 10 includes: a semiconductor substrate and a gate structure thereon. The semiconductor substrate has an N-type epitaxy drift region 100 and a P-type base region 102 above it to form a P-N junction. Furthermore, there is a drain region 106 under the N-type epitaxial drift region 100 , which is connected to a drain electrode 114 . The P-type body region 102 has a source region 104 connected to a source electrode 112 . The gate structure is composed of a gate dielectric layer 108 and a gate electrode 110 thereon.

In order to increase the withstand voltage of the P-N junction in the N-type vertical diffused MOSFET 10 , it is necessary to reduce the doping concentration and/or increase the thickness of the N-type epitaxial drift region 100 . However, when the withstand voltage of the P-N junction is increased in the above manner, the on-resistance (Ron) of the N-type vertical diffused MOSFET 10 will also be increased at the same time. That is, the on-resistance is limited by the doping concentration and thickness of the N-type epitaxial drift region.

The vertical diffused metal oxide semiconductor field effect transistor with a super-junction structure can increase the dopant concentration of the N-type epitaxial drift region, thereby increasing the withstand voltage of the P-N junction, and at the same time avoiding the increase of the on-resistance . In a prior art, the superjunction structure is formed by using multi-epitaxial technology. The above-mentioned multi-epitaxial technology requires epitaxial growth, P-type doping process and high temperature diffusion process, and the above processes are repeated. Therefore, the above-mentioned multi-layer epitaxial technology has disadvantages such as complicated process, high manufacturing cost, and difficulty in shrinking the device size.

Therefore, it is necessary to seek a semiconductor device with a superjunction structure, which can improve or solve the above-mentioned problems.

Contents of the invention

An embodiment of the present invention provides a semiconductor device, including: a substrate having a first doped region and a second doped region thereon, wherein the first and second doped regions have a first conductivity type , and wherein there is at least one first trench and at least one second trench adjacent thereto in the second doped region; a first epitaxial layer is disposed in the first trench and has a second conductivity type; A second epitaxial layer is disposed in the second trench and has the first conductivity type, wherein the second epitaxial layer has a doping concentration greater than that of the second doping region and less than that of the first doping region doping concentration; and a gate structure disposed above the second trench.

Another embodiment of the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate with a first doped region and a second doped region thereon, wherein the first and second doped regions have A first conductivity type; at least one first trench is formed in the second doped region; a first epitaxial layer is filled in the first trench, wherein the first epitaxial layer has a second conductivity type; At least one second trench adjacent to the first trench is formed in the doped region; a second epitaxial layer is filled in the second trench, wherein the second epitaxial layer has the first conductivity type, and the second epitaxial layer having a doping concentration greater than that of the second doping region and less than that of the first doping region; and forming a gate structure above the second trench.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a conventional N-type vertical diffused MOSFET.

2A to 2G are schematic cross-sectional views illustrating a manufacturing method of a semiconductor device according to an embodiment of the present invention.

3A to 3E are schematic cross-sectional views illustrating a manufacturing method of a semiconductor device according to another embodiment of the present invention.

4A to 4F are schematic cross-sectional views illustrating a manufacturing method of a semiconductor device according to yet another embodiment of the present invention.

Figure number:

existing

10~N type vertical diffused metal oxide semiconductor field effect transistor;

100 ~ N-type epitaxial drift region;

102～P-type matrix region;

104～source region;

106～drain region;

108～gate electrode layer;

110～gate electrode;

112～source electrode;

114 ~ drain electrode.

Example

20, 20’, 20”～semiconductor device;

200～base;

200a～the first doped region;

200b～the second doped region;

201～interface;

202, 210, 218～hard mask;

202a, 210a, 218a～opening;

204～the first groove;

206, 214, 222 ~ insulating liner layer;

208, 208'～the first epitaxial layer;

209, 217, 226～dielectric material layer;

212～the second groove;

216, 216'～the second epitaxial layer;

216a～extended part;

220～the third groove;

224～doping process;

224a～the third doped region;

228～gate dielectric layer;

230～gate electrode;

232～well area;

234～source region;

A ~ active area.

Detailed ways

The semiconductor device and its manufacturing method according to the embodiment of the present invention will be described below. However, it can be easily understood that the embodiments provided in the present invention are only used to illustrate the making and use of the present invention in a specific way, and are not intended to limit the scope of the present invention.

Please refer to FIG. 2G , which shows a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. The semiconductor device 20 of the embodiment of the present invention includes a vertical diffused metal oxide semiconductor field effect transistor (VDMOSFET) having a super junction structure. The semiconductor device 20 includes a substrate 200 having a first doped region 200a and a second doped region 200b thereon, wherein an interface 201 is formed between the first doped region 200a and the second doped region 200b . As shown in FIG. 2G , the substrate 200 may include an active region A and a termination region (not shown) surrounding the active region A. Referring to FIG. In one embodiment, the active region A is provided for semiconductor devices to be formed thereon, and the terminal region serves as insulation between different semiconductor devices. In one embodiment, the first doped region 200a is formed of a doped semiconductor material, and the second doped region 200b is formed of a doped epitaxial layer. In another embodiment, the first doped region 200 a and the second doped region 200 b with different doping concentrations are formed in the substrate 200 made of the same semiconductor material. In this embodiment, the first doped region 200a and the second doped region 200b have a first conductivity type, and the first doped region 200a can be a heavily doped region, and the second doped region 200b can be a lightly doped region.

There are a plurality of first trenches 204 and a plurality of second trenches 212 arranged alternately with the first trenches 204 in the second doped region 200b, so that each second trench 212 is in phase with at least one first trench 204 or each first trench 204 is adjacent to at least one second trench 212 . Here, to simplify the drawing, only one second trench 212 and two adjacent first trenches 204 are shown. In this embodiment, the bottoms of the first trench 204 and the second trench 212 are located above the interface 201 between the first doped region 200a and the second doped region 200b. However, in other embodiments, the first trench 204 and the second trench 212 may also expose the interface 201 between the first doped region 200a and the second doped region 200b.

A first epitaxial layer 208 is disposed in each first trench 204 and has a second conductivity type, wherein the first epitaxial layer 208 has a doping concentration greater than that of the second doping region 200b and less than The doping concentration of the first doped region 200a. A second epitaxial layer 216 is disposed in each second trench 212 and has the first conductivity type, wherein the second epitaxial layer 216 has a doping concentration higher than that of the second doping region 200b and lower than that of the first doping region 200b. A doping concentration of the doped region 200a.

In this embodiment, the first conductivity type is N type, and the second conductivity type is P type. However, in other embodiments, the first conductivity type can also be P-type, and the second conductivity type is N-type. Therefore, the first epitaxial layer 208 with the second conductivity type and the second epitaxial layer 216 with the first conductivity type form a super junction structure in the second doped region 200b.

A gate structure is disposed above each second trench 212 and includes a gate dielectric layer 228 and a gate electrode 230 thereon. Furthermore, a well region 232 with the second conductivity type is formed on the upper half of each first epitaxial layer 208 and extends in the second doped region 200 b outside the first epitaxial layer 208 . The source region 234 with the first conductivity type is formed in each well region 232 on both sides of the gate structure, and forms a vertical diffused metal oxide with the gate structure and the first doped region (serving as the drain region) 200a Semiconductor Field Effect Transistor.

Please refer to FIG. 3E , which shows a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention, wherein components identical to those in FIG. 2G use the same reference numerals and their descriptions are omitted. In this embodiment, the second epitaxial layer 216 in the semiconductor device 20' further includes an extension portion 216a located on the substrate 200 and covering the second doped region 200b. In particular, a third trench 220 corresponding to each of the first trenches 204 is formed in the extension portion 216 a of the second epitaxial layer 216 to expose the first epitaxial layer 208 . Moreover, a third doped region 224a adjacent to a sidewall of each third trench 220 is disposed in the extension portion 216a of the second epitaxial layer 216, wherein the third doped region 224a has the second conductivity type. In this embodiment, the doping concentration of the third doping region 224 a is greater than that of the second doping region 200 b and smaller than that of the first doping region 200 a. Therefore, the third doped region 224 a of the second conductivity type and the extension portion 216 a of the first conductivity type also form a super junction structure.

An insulating liner layer 222 and a dielectric material layer 226 are disposed in each third trench 220 . In one embodiment, the insulating liner layer 222 may include silicon oxide, and the dielectric material layer 226 may include silicon oxide or undoped polysilicon.

In this embodiment, the gate structure is disposed on the extension portion 216 a and corresponds to each second trench 212 . Moreover, the well region 232 is formed in the upper half of each third doped region 224a, and extends in the extension portion 216a outside the third doped region 224a. The source region 234 with the first conductivity type is formed in each well region 232 on both sides of the gate structure, and forms a vertical diffused metal oxide with the gate structure and the first doped region (serving as the drain region) 200a Semiconductor Field Effect Transistor.

Please refer to FIG. 4F , which shows a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present invention, wherein components identical to those in FIG. 2G use the same reference numerals and their descriptions are omitted. In this embodiment, the first epitaxial layer 208' and the second epitaxial layer 216' in the semiconductor device 20" are respectively filled into the local first trench 204 and the second trench 212. For example, the first epitaxial The layer 208' is conformably disposed on the sidewall and bottom of the first trench 204, and the second epitaxial layer 216' is conformably disposed on the sidewall and bottom of the second trench 212. Moreover, the dielectric material layer 209 and 217 are respectively disposed in the first trench 204 and the second trench 212 to fill the first trench 204 and the second trench 212. In one embodiment, the dielectric material layers 209 and 217 may include oxide Silicon or undoped polysilicon. Therefore, the first epitaxial layer 208' of the second conductivity type and the second epitaxial layer 216' of the first conductivity type form a superjunction structure in the second doped region 200b.

In this embodiment, the well region 232 is formed in the upper half of each first epitaxial layer 208', and extends in the second doped region 200b outside the first epitaxial layer 208'. The source region 234 with the first conductivity type is formed in each well region 232 on both sides of the gate structure, and forms a vertical diffused metal oxide with the gate structure and the first doped region (serving as the drain region) 200a Semiconductor Field Effect Transistor.

2A to 2G are schematic cross-sectional views illustrating a manufacturing method of the semiconductor device 20 according to an embodiment of the present invention. 2A, a substrate 200 is provided, which has a first doped region 200a and a second doped region 200b located thereon, wherein there is a Interface 201. The substrate 200 may include an active area A and a terminal area (not shown) surrounding the active area A. Referring to FIG. In one embodiment, the first doped region 200a may be formed of a doped semiconductor material, and the second doped region 200b is grown by epitaxial growth in the doped semiconductor material (ie, the first doped region 200a ) formed by forming a doped epitaxial layer. In another embodiment, different doping processes may be performed on the substrate 200 made of a semiconductor material, so as to form the first doped region 200a and the second doped region 200b with different doping concentrations therein, The doping process for forming the first doped region 200a can be performed after the transistor structure is subsequently formed. In this embodiment, the first doped region 200a and the second doped region 200b have a first conductivity type, and the first doped region 200a can be a heavily doped region, and the second doped region 200b can be a lightly doped region.

Next, please refer to FIG. 2A and FIG. 2B , which illustrate the formation method of the first trench 204 . A hard mask (hard mask, HM) 202 can be formed on the substrate 200 through chemical vapor deposition (chemical vapor deposition, CVD), and then a lithography process and an etching process are performed to form a hard mask in the active region A A plurality of openings 202 a defining the first trench 204 are formed in the opening 202 . Afterwards, an anisotropic etching process is performed to form a plurality of first trenches 204 in the second doped region 200b below the opening 202a. In this embodiment, the bottom of the first trench 204 is located above the interface 201 between the first doped region 200 a and the second doped region 200 b (eg, close to the interface 201 ). However, in other embodiments, the first trench 204 and the second trench 212 may also expose the interface 201 between the first doped region 200a and the second doped region 200b.

In this embodiment, after removing the hard mask 202, an insulating liner (insulating liner) 206 can be conformably formed on the sidewall and bottom of each first trench 204 by CVD or thermal oxidation. . In an embodiment of the invention, the insulating liner layer 206 can be an oxide liner layer, which can reduce the stress in the second doped region 200b.

Referring to FIG. 2C , after removing the insulating liner layer 206 , a first epitaxial layer 208 having a second conductivity type can be filled in each first trench 204 . The first epitaxial layer 208 has a doping concentration higher than that of the second doping region 200b and lower than that of the first doping region 200a. For example, the first epitaxial layer 208 can be formed on the substrate 200 and within each first trench 204 through epitaxial growth. After that, the first epitaxial layer 208 above the substrate 200 is removed through a polishing process, such as chemical mechanical polishing (CMP). In this embodiment, the first conductivity type is N type, and the second conductivity type is P type. However, in other embodiments, the first conductivity type can also be P-type, and the second conductivity type is N-type.

Next, please refer to FIG. 2D and FIG. 2E , which illustrate the formation method of the second trench 212 . A hard mask 210 is formed on the substrate 200, and its material and fabrication may be similar or identical to the hard mask 210 (shown in FIG. 2A ). A plurality of openings 210a for defining the second trenches 212 are then formed in the hard mask 210 of the active region A. Referring to FIG. After that, an anisotropic etching process is performed to form a plurality of second trenches 212 in the second doped region 200b under the opening 210a. The second grooves 212 are alternately arranged with the first grooves 204, so that each second groove 212 is adjacent to at least one first groove 204, or each first groove 204 is adjacent to at least one second groove 212 adjacent. Here, to simplify the drawing, only a second trench 212 adjacent to the two first trenches 204 is shown, as shown in FIG. 2D .

In this embodiment, after removing the hard mask 210, an insulating liner layer 214 is conformably formed on the sidewall and bottom of each second trench 212 to reduce the stress in the second doped region 200b. , as shown in Figure 2E. The material and fabrication of the insulating liner layer 214 may be similar or identical to the insulating liner layer 206 (shown in FIG. 2B ).

Referring to FIG. 2F , after the insulating liner layer 214 is removed, a second epitaxial layer 216 of the first conductivity type can be filled in each second trench 212 . The second epitaxial layer 216 has a doping concentration greater than that of the second doping region 200b and less than that of the first doping region 200a. The fabrication of the second epitaxial layer 216 may be similar or identical to that of the first epitaxial layer 208 (shown in FIG. 2C ). Therefore, the first epitaxial layer 208 with the second conductivity type and the second epitaxial layer 216 with the first conductivity type form a super junction structure in the second doped region 200b.

Referring to FIG. 2G , a gate structure including a gate dielectric layer 228 and a gate electrode 230 thereon may be formed above each second trench 212 through an existing MOS process. Furthermore, a well region 232 of the second conductivity type can be formed in the upper half of each first epitaxial layer 208 and extend in the second doped region 200 b outside the first epitaxial layer 208 . A source region 234 with the first conductivity type is formed in each well region 232 on both sides of the gate structure to complete the fabrication of the semiconductor device 20, wherein the source region 234, the gate structure and the first doped region (serving as the drain Pole region) 200a constitutes a vertical diffused metal oxide semiconductor field effect transistor.

3A to 3E are schematic cross-sectional views illustrating a manufacturing method of a semiconductor device according to another embodiment of the present invention, wherein the same components as those in FIGS. 2A to 2G use the same reference numerals and their descriptions are omitted. Referring to FIG. 3A , a substrate 200 is provided, which may include an active area A and a termination area (not shown) surrounding the active area A. Referring to FIG. Moreover, the substrate 200 has a first doped region 200a and a second doped region 200b thereon, and the first doped region 200a and the second doped region 200b have the first conductivity type. There is an interface 201 between the first doped region 200a and the second doped region 200b. There are a plurality of first trenches 204 and a plurality of second trenches 212 arranged alternately with the first trenches 204 in the second doped region 200b, so that each second trench 212 is in phase with at least one first trench 204 or each first trench 204 is adjacent to at least one second trench 212 . Here, to simplify the drawing, only one second trench 212 and two adjacent first trenches 204 are shown. A first epitaxial layer 208 of the second conductivity type is disposed in each first trench 204 . In an embodiment, the above-mentioned structure can be formed by performing the manufacturing process as shown in FIG. 2A to FIG. 2E .

Then, through epitaxial growth, a second epitaxial layer 216 with the first conductivity type is filled in each second trench 212, and the second epitaxial layer 216 is extended from the second trench 212 on the substrate 200. , to form an extension 216a covering the second doped region 200b, as shown in FIG. 3A.

Next, please refer to FIG. 3A and FIG. 3B , which illustrate the formation method of the third trench 220 . A hard mask 218 is formed above the extension portion 216a, and its material and fabrication may be similar or identical to the hard mask 210 (shown in FIG. 2A ). A plurality of openings 218 a for defining the third trenches 220 are then formed in the hard mask 218 of the active region A. Referring to FIG. Afterwards, an anisotropic etching process is performed to form a plurality of third trenches 220 in the second epitaxial layer 216 (ie, the extension portion 216 a ) under the opening 218 a. The third trench 220 is substantially aligned with the first trench 204 and exposes the first epitaxial layer 208 within the first trench 204 , as shown in FIG. 3B .

Please refer to FIG. 3B again. In this embodiment, after the hard mask 218 is removed, an insulating liner layer 222 is conformably formed on the sidewall and bottom of each third trench 220 to reduce the extension portion 216a. Internal stress, and can be used as a shielding oxide layer (pre-implant oxide) in the subsequent doping process to reduce the channel effect. The material and fabrication of the insulating liner layer 222 may be similar or identical to the insulating liner layer 206 (shown in FIG. 2B ).

3C, a doping process 224, such as ion implantation, can be performed to form a plurality of third doped regions 224a in the extension 216a of the second epitaxial layer 216, wherein each third doped region 224a is adjacent to on a sidewall of each third trench 220 and has the second conductivity type. In this embodiment, the doping concentration of the third doping region 224 a is greater than that of the second doping region 200 b and smaller than that of the first doping region 200 a. Therefore, the third doped region 224 a of the second conductivity type and the extension portion 216 a of the second epitaxial layer 216 of the first conductivity type form a super junction structure.

Referring to FIG. 3D , a dielectric material layer 226 is filled in each third trench 220 . For example, a dielectric material layer 226, such as silicon oxide or undoped silicon oxide, can be formed on the extension portion 216a of the second epitaxial layer 216 and in each third trench 220 through a chemical vapor deposition (CVD) process. of polysilicon. Afterwards, the dielectric material layer 226 on the extension portion 216 a of the second epitaxial layer 216 is removed by a chemical mechanical polishing (CMP) process.

Referring to FIG. 3E, a gate structure can be formed on the extension 216a of the second epitaxial layer 216 above each second trench 212 through the existing MOS process, which includes a gate dielectric layer 228 and a gate dielectric layer 228 located thereon. on the gate electrode 230 . Furthermore, a well region 232 of the second conductivity type may be formed in the upper half of each third doped region 224a, and extend in the extension portion 216a outside the third doped region 224a. A source region 234 having a first conductivity type is formed in each well region 232 on both sides of the gate structure to complete the fabrication of the semiconductor device 20', wherein the source region 234, the gate structure and the first doped region (as The drain region) 200a constitutes a vertical diffused MOSFET.

4A to 4F are schematic cross-sectional views illustrating a manufacturing method of a semiconductor device according to another embodiment of the present invention, wherein the same components as those in FIG. 2A to FIG. 2G use the same reference numerals and their descriptions are omitted. Referring to FIG. 4A , a substrate 200 is provided, which may include an active area A and a terminal area (not shown) surrounding the active area A. Referring to FIG. Moreover, the substrate 200 has a first doped region 200a and a second doped region 200b thereon, and the first doped region 200a and the second doped region 200b have the first conductivity type. There is an interface 201 between the first doped region 200a and the second doped region 200b. There are a plurality of first trenches 204 in the second doped region 200b. In an embodiment, the above-mentioned structure can be formed by performing the manufacturing process shown in FIG. 2A to FIG. 2B . Then, a first epitaxial layer 208' of the second conductivity type can be formed conformally on the sidewall and bottom of each first trench 204 through epitaxial growth.

Referring to FIG. 4B , a dielectric material layer 209 is filled in each first trench 204 . For example, a dielectric material layer 209 , such as silicon oxide or undoped polysilicon, can be formed on the substrate 200 and within each first trench 204 through a chemical vapor deposition (CVD) process. Afterwards, the dielectric material layer 209 on the substrate 200 is removed by a chemical mechanical polishing (CMP) process.

Referring to FIG. 4C , the manufacturing process described in FIG. 2D is performed, and a plurality of second trenches 212 are formed in the second doped region 200 b under the opening 210 a of the hard mask 210 . The second grooves 212 are arranged alternately with the first grooves 204 . Here, to simplify the drawing, only a second trench 212 adjacent to the two first trenches 204 is shown.

Referring to FIG. 4D , the manufacturing process as shown in FIG. 2E is performed, and an insulating liner layer 214 is conformally formed on the sidewall and bottom of each second trench 212 to reduce the stress in the second doped region 200 b.

Referring to FIG. 4E , a second epitaxial layer 216 ′ having the first conductivity type can be formed conformably on the sidewall and bottom of each second trench 212 through epitaxial growth, and its fabrication method can be similar or identical to that of the first trench. Epitaxial layer 208'. Afterwards, a dielectric material layer 217 is filled in each first trench 204 , and its material and manufacturing method may be similar or identical to those of the dielectric material layer 209 .

Referring to FIG. 4F , a gate structure including a gate dielectric layer 228 and a gate electrode 230 thereon may be formed above each second trench 212 through an existing MOS process. Furthermore, a well region 232 of the second conductivity type can be formed in the second doped region 200b outside the upper half of each first epitaxial layer 208'. A source region 234 having a first conductivity type is formed in each well region 232 on both sides of the gate structure to complete the fabrication of the semiconductor device 20", wherein the source region 234, the gate structure and the first doped region (as The drain region) 200a constitutes a vertical diffused MOSFET.

According to the above-mentioned embodiment, since the charge balance can be achieved by controlling the doping concentration of the N-type region and the P-type region in the superjunction structure formed by the first epitaxial layer 208 or 208' and the second epitaxial layer 216 or 216' (charge balance), so the above-mentioned super junction structure can be formed in the lightly doped region (that is, the second doped region 200b), thereby improving the withstand voltage of the P-N junction in the vertical diffused metal oxide semiconductor field effect transistor, At the same time, an increase in on-resistance can be avoided.

Furthermore, according to the above-mentioned embodiment, only two epitaxial growths are required to form alternately arranged P-N columnar superjunction structures in a plurality of trenches in the lightly doped region, thereby simplifying the process and reducing the manufacturing cost. cost and shrink component size.

In addition, according to the above-mentioned embodiments, since additional superjunction structures can be formed above a plurality of trenches, the withstand voltage of the P-N junction can be further improved without increasing the depth of the trenches, and it will not be damaged by etching deep trenches. Increased crafting difficulty.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The protection scope of the invention should be defined by the claims.

Claims (18)

1. a semiconductor device, is characterized in that, described semiconductor device comprises:

One substrate, one second doped region that there is one first doped region and be located thereon, wherein said first and described second doped region there is one first conduction type, and at least one second groove that there is in wherein said second doped region at least one first groove and be adjacent;

One first epitaxial loayer, is arranged in described first groove, and has one second conduction type;

One second epitaxial loayer, be arranged in described second groove, and there is described first conduction type, wherein said second epitaxial loayer has the doping content that a doping content is greater than described second doped region, and be less than the doping content of described first doped region, described second epitaxial loayer more comprises an extension, be positioned in described substrate and cover described second doped region, described extension has one the 3rd groove and exposes described first epitaxial loayer, and there is the sidewall that one the 3rd doped region is adjacent to described 3rd groove, described 3rd doped region has described second conduction type; And

One grid structure, is arranged at above described second groove.

2. semiconductor device as claimed in claim 1, it is characterized in that, the doping content of described 3rd doped region is greater than the doping content of described second doped region, and is less than the doping content of described first doped region.

3. semiconductor device as claimed in claim 1, it is characterized in that, described semiconductor device more comprises a dielectric materials layer, is arranged in described 3rd groove.

4. semiconductor device as claimed in claim 3, it is characterized in that, described dielectric materials layer comprises silica or unadulterated polysilicon.

5. semiconductor device as claimed in claim 1, it is characterized in that, described first conduction type is N-type, and described second conduction type is P type.

6. semiconductor device as claimed in claim 1, it is characterized in that, described second doped region is made up of an epitaxial loayer.

7. semiconductor device as claimed in claim 1, it is characterized in that, described first groove and described second groove expose the interface between described first doped region and described second doped region.

8. semiconductor device as claimed in claim 1, it is characterized in that, described first epitaxial loayer has the doping content that a doping content is greater than described second doped region, and is less than the doping content of described first doped region.

9. a manufacture method for semiconductor device, is characterized in that, the manufacture method of described semiconductor device comprises:

There is provided a substrate, one second doped region that there is one first doped region and be located thereon, wherein said first and described second doped region there is one first conduction type;

At least one first groove is formed in described second doped region;

In described first groove, insert one first epitaxial loayer, wherein said first epitaxial loayer has one second conduction type;

At least one second groove adjacent with described first groove is formed in described second doped region;

One second epitaxial loayer is inserted in described second groove, wherein said second epitaxial loayer has described first conduction type, and described second epitaxial loayer has the doping content that a doping content is greater than described second doped region, and be less than the doping content of described first doped region;

In described second groove, extend described second epitaxial loayer cover described second doped region in described substrate;

Form one the 3rd groove in described second epitaxial loayer on the substrate and expose described first epitaxial loayer;

In described second epitaxial loayer, form one the 3rd doped region, wherein said 3rd doped region is adjacent to a sidewall of described 3rd groove, and has described second conduction type; And

A grid structure is formed above described second groove.

10. the manufacture method of semiconductor device as claimed in claim 9, it is characterized in that, the doping content of described 3rd doped region is greater than the doping content of described second doped region, and is less than the doping content of described first doped region.

The manufacture method of 11. semiconductor devices as claimed in claim 9, is characterized in that, the manufacture method of described semiconductor device forms an insulation liner layer before being more included in and forming described 3rd doped region in described 3rd groove.

The manufacture method of 12. semiconductor devices as claimed in claim 9, is characterized in that, the manufacture method of described semiconductor device is more included in described 3rd groove inserts a dielectric materials layer.

The manufacture method of 13. semiconductor devices as claimed in claim 12, it is characterized in that, described dielectric materials layer comprises silica or unadulterated polysilicon.

The manufacture method of 14. semiconductor devices as claimed in claim 9, it is characterized in that, described first conduction type is N-type, and described second conduction type is P type.

The manufacture method of 15. semiconductor devices as claimed in claim 9, it is characterized in that, described second doped region is made up of an epitaxial loayer.

The manufacture method of 16. semiconductor devices as claimed in claim 9, is characterized in that, described first groove and described second groove expose the interface between described first doped region and described second doped region.

The manufacture method of 17. semiconductor devices as claimed in claim 9, it is characterized in that, described first epitaxial loayer has the doping content that a doping content is greater than described second doped region, and is less than the doping content of described first doped region.

The manufacture method of 18. semiconductor devices as claimed in claim 9, it is characterized in that, before the manufacture method of described semiconductor device is more included in and inserts described first epitaxial loayer, an insulation liner layer is formed in described first groove, or before inserting described second epitaxial loayer, in described second groove, form an insulation liner layer.