CN111213241B - Semiconductor device, semiconductor apparatus, and method of manufacturing the same - Google Patents

Abstract

The application relates to the field of semiconductors, and particularly discloses a semiconductor device, semiconductor equipment and a manufacturing method thereof. A semiconductor apparatus includes a plurality of semiconductor devices having a single substrate and a plurality of trench regions, each trench region including a trench, wherein the single substrate includes a substrate layer, a first epitaxial layer of a first conductivity type disposed on the substrate layer, and a second epitaxial layer of a second conductivity type disposed on the first epitaxial layer, wherein each trench of the plurality of trench regions extends into the first epitaxial layer through the second epitaxial layer, thereby isolating an adjacent semiconductor device of the plurality of semiconductor devices. Through the embodiment, the application can reduce parasitic inductance, avoid back gate problem and provide avalanche tolerance.

Description

Semiconductor devices, semiconductor equipment and manufacturing methods thereof

Cross-references to related applications

This application claims priority from U.S. Provisional Application 62/692,780, filed on June 30, 2018, entitled "III-nitride power devices and high-voltage integrated circuit platforms based on III-nitride power devices." The entire disclosures of the applications cited above are hereby incorporated by reference in their entirety for all purposes.

Technical field

The present invention relates generally to the field of semiconductors and, more particularly, to semiconductor devices, semiconductor devices and methods of manufacturing the same.

Background technique

The following background information may present examples of particular aspects of the prior art (such as, but not limited to, methods, facts, or common knowledge), and although it is expected that they will help further teach the reader about other aspects of the prior art, they should not be construed as Limit this invention or any other embodiment to anything stated or implied therein or inferred on the basis thereof.

Generally, III-nitrides have high band gaps suitable for high voltage power applications. Group III nitride semiconductor devices can be fabricated by forming a Group III nitride heterojunction on a silicon substrate according to known designs. It is known in the art that wide bandgap semiconductor GaN devices switch faster than traditional silicon-based semiconductor devices. Application engineers can take advantage of this feature to increase the operating frequency of power systems, thereby reducing system size and weight.

However, although GaN devices can operate at much higher frequencies than silicon-based semiconductor devices, the switching frequency of power systems is sometimes limited by parasitic inductances in the power loop. Those skilled in the art will appreciate that when the semiconductor device switches at high speeds, these parasitic inductances may produce high voltage spikes on the semiconductor device, causing device and system failure.

In general, monolithic integration of semiconductor devices can significantly reduce parasitic inductance. The lateral structure of typical GaN devices facilitates monolithic integration of multiple devices. In power switching applications such as bridge circuits, there are high-side devices and low-side devices. However, in order to integrate high-side GaN devices with low-side GaN devices, there are technical challenges related to the electrical connection of the conductive substrate.

Generally speaking, when a high-side GaN device and a low-side GaN device are monolithically integrated, the substrate can be connected to the source of the low-side GaN device or the source of the high-side GaN device. In both cases, the substrate creates a backgate effect on devices whose sources are not connected to the substrate. Additionally, in power switching applications, semiconductor devices often need to be resistant to avalanche events. Traditional GaN devices have insufficient avalanche capabilities, so they cannot be used in certain fields.

Other proposals involve GaN and Group III nitride semiconductor devices. The problem with these semiconductor devices is that they cannot overcome the back gate and they are not strong enough to survive an avalanche event. Furthermore, these semiconductor devices cannot overcome the parasitic inductance in the power loop. Even though the GaN and III-nitride semiconductor devices cited above satisfy some market needs, there is still a need for integrated III-nitride semiconductor devices that can operate as switches in the design and implementation of power conversion circuits and are capable of overcoming avalanche capabilities Insufficiency, back gate and parasitic inductance in the power loop.

Contents of the invention

The purpose of embodiments of the present invention is to provide a semiconductor device, a semiconductor device and a manufacturing method thereof, which can reduce parasitic inductance, avoid back gate problems and provide avalanche withstand capability.

An example embodiment provides a semiconductor device. The semiconductor device includes: a substrate layer having a first surface and a second surface; a first epitaxial layer of a first conductivity type, disposed on the first surface of the substrate layer; and a second epitaxial layer of a second conductivity type, disposed on the first surface of the substrate layer. On an epitaxial layer, the second conductivity type is different from the first conductivity type; a transition layer disposed on the second epitaxial layer; a channel layer disposed on the transition layer; a barrier layer disposed on the channel layer; and a contact barrier layer and electrically connected to the first electrode of the second epitaxial layer.

Other example embodiments will be explained herein.

Description of the drawings

The invention will now be described by way of example with reference to the accompanying drawing, in which:

1 shows a schematic structure of a semiconductor device according to a first embodiment;

2 shows a schematic structure of a semiconductor device according to a second embodiment;

3 shows a partial structure of a semiconductor device in which two transistors are separated by a trench according to an embodiment;

4 shows a partial structure of a semiconductor device in which two diodes are separated by a trench according to an embodiment;

5 illustrates a partial structure of a semiconductor device in which transistors and diodes are separated by trenches according to an embodiment; and

Like reference characters refer to like parts throughout the various views of the drawings.

Detailed ways

The following detailed description is merely exemplary in nature and is not intended to limit the described embodiments or the application and uses of the described embodiments. As used herein, the word "exemplary" or "illustrative" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" or "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments. All embodiments described below are exemplary embodiments provided to enable those skilled in the art to make or use the embodiments of the present disclosure, and are not intended to limit the scope of the disclosure, which is defined by the claims. For purposes of description herein, "upper", "lower", "left", "rear", "right", "front", "vertical", "horizontal" and their derivatives shall be as shown in Figure 1 invention related. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description. It will also be understood that the specific devices and processes illustrated in the drawings and described in the following specification are simply exemplary embodiments of the inventive concepts defined in the appended claims. Accordingly, specific dimensions and other physical characteristics related to the embodiments disclosed herein should not be construed as limiting unless the claims expressly provide otherwise.

One or more embodiments recognize one or more technical problems that exist in conventional devices and methods. Because GaN can carry large currents and support high voltages, Group III nitride semiconductor devices are highly efficient for power semiconductor devices. The semiconductor device also offers very low on-resistance and fast switching times. The semiconductor device is defined by GaN's multiple polarities, including Ga-polar, N-polar, semi-polar and non-polar. The semiconductor device is monolithically integrated into various components in order to control current flow, such as controlling LEDs. The semiconductor device also provides switching power supplies for power converters, power inverters, motor drives and motor soft starters.

Multiple semiconductor devices can be monolithically integrated on a single substrate. It is known in the art that monolithic integration of semiconductor devices can significantly reduce parasitic inductance. The lateral structure of typical GaN devices facilitates monolithic integration of multiple devices. In power switching applications such as bridge circuits, there are high-side devices and low-side devices. However, in order to integrate high-side GaN devices with low-side GaN devices, there are technical challenges related to the electrical connection of the conductive substrate, which can establish a back-gate effect under certain bias conditions. Furthermore, existing GaN semiconductor devices are not capable enough to withstand avalanche events.

As shown in the schematic diagram of FIG. 1 , the semiconductor device 150 according to the first embodiment includes a substrate layer 100 . Substrate layer 100 includes a conductive substrate such as silicon. The substrate layer 100 includes an n-type doped or p-type doped silicon substrate. Another layer used in semiconductor device 150 includes first epitaxial layer 101 covering substrate layer 100 . The first epitaxial layer 101 is defined by a first doping type, which may include n-type doping. In one non-limiting embodiment, first epitaxial layer 101 includes silicon.

The second epitaxial layer 102 also covers the substrate layer 100 . The second epitaxial layer 102 is defined by a second doping type, which may include p-type doping. The second epitaxial layer 102 forms a junction with the first epitaxial layer 101, whereby a specific voltage can be maintained through the junction formed by the first epitaxial layer 101 and the second epitaxial layer 102. In one non-limiting embodiment, second epitaxial layer 102 includes silicon.

The device of the present invention also includes a transition layer 201, a channel layer 202, a barrier layer 203, a source electrode 301, a gate electrode 302, a drain electrode 303 and a substrate contact electrode 306. The transition layer 201 and the second epitaxial layer 102 form a junction. In some embodiments, transition layer 201 includes at least one of: GaN, AIN, InN, AlGaN, InGaN, and AlInGaN. Yet another layer of semiconductor device 150 is channel layer 202 that forms a junction with transition layer 201 . Channel layer 202 is defined by the channel band gap. In some embodiments, channel layer 202 includes at least one of GaN, AIN, InN, AlGaN, InGaN, and AlInGaN.

Continuing with FIG. 1 , the barrier layer 203 and the channel layer 202 form a junction. The band gap of the barrier layer 203 is larger than the band gap of the channel layer 202 . In some embodiments, barrier layer 203 includes at least one of: GaN, AIN, InN, AlGaN, InGaN, and AlInGaN. In some embodiments, semiconductor device 150 includes source electrode 301 . The source electrode 301 is electrically connected to the second epitaxial layer 102 . There are multiple choices for the connection position between the source electrode 301 and the second epitaxial layer 102 . For example, the connection can be directly under source electrode 301, or it can be outside the active area of the device. In applications such as bridge circuits, substrate contact electrode 306 may be electrically connected to the drain of the high side device. In applications such as bridge circuits, the substrate contact electrode 306 may also be electrically connected to the cathode of the high side device. Substrate contact electrode 306 may also be floating.

In some embodiments, semiconductor device 150 includes gate electrode 302 . In one embodiment, a recessed region is formed under the gate electrode 302 . In another embodiment, a dielectric layer is formed under gate electrode 302 . In yet another embodiment, a p-type capping layer is formed under gate electrode 302 . In some embodiments, semiconductor device 150 also includes substrate contact electrode 306 . In one embodiment, substrate contact electrode 306 is electrically connected to drain electrode 303 . Therefore, a vertical breakdown voltage is formed from the drain electrode 303 to the second epitaxial layer 102 .

To provide the ability to survive an avalanche event, the breakdown voltage between the first epitaxial layer 101 and the second epitaxial layer 102 is lower than the lateral breakdown voltage between the drain electrode 303 and the source electrode 301 . In addition, the breakdown voltage between the first epitaxial layer 101 and the second epitaxial layer 102 is lower than the lateral breakdown voltage between the drain electrode 303 and the gate electrode 302 . In addition, the breakdown voltage between the first epitaxial layer 101 and the second epitaxial layer 102 is lower than the vertical breakdown voltage between the drain electrode 303 and the second epitaxial layer 102 . Therefore, when an avalanche event occurs, the junction between the first epitaxial layer 101 and the second epitaxial layer 102 can be utilized to release the avalanche current.

Turning now to FIG. 2 , a semiconductor device 250 according to another illustrative embodiment includes many of the same layers, including a substrate layer 100 , a first epitaxial layer 101 , a second epitaxial layer 102 , a transition layer 201 , a channel layer 202 and a potential. Barrier layer 203. Furthermore, the anode electrode 304 is connected to the second epitaxial layer 102 . Additionally, a cathode electrode 305 and a substrate contact electrode 306 are provided. As above, the transition layer 201 may include one or a combination of GaN, AIN, InN, AlGaN, InGaN, and AlInGaN. Channel layer 202 may be one or a combination of GaN, AIN, InN, AlGaN, InGaN, and AlInGaN. Barrier layer 203 may include one or a combination of GaN, AIN, InN, AlGaN, InGaN, and AlInGaN.

Semiconductor device 250 also includes substrate contact electrode 306 . In applications, substrate contact electrode 306 is electrically connected to cathode electrode 305 . In applications such as bridge circuits, substrate contact electrode 306 may be electrically connected to the drain of the high side device. In applications such as bridge circuits, the substrate contact electrode 306 may also be electrically connected to the cathode of the high side device. Substrate contact electrode 306 may also be floating. The junction between the first epitaxial layer 101 and the second epitaxial layer 102 is configured to have a lower breakdown voltage than the lateral breakdown voltage from the cathode electrode 305 to the anode electrode 304 . In another voltage difference, a vertical breakdown voltage is formed from the cathode electrode 305 to the second epitaxial layer 102 . Therefore, when an avalanche event occurs, the junction between the first epitaxial layer 101 and the second epitaxial layer 102 can be utilized to release the avalanche current.

In the second embodiment, the breakdown voltage between the first epitaxial layer 101 and the second epitaxial layer 102 is lower than the lateral breakdown voltage from the cathode electrode 305 to the anode electrode 304 . In another embodiment, the breakdown voltage between the first epitaxial layer 101 and the second epitaxial layer 102 is lower than the vertical breakdown voltage from the cathode electrode 305 to the second epitaxial layer 102 . In this way, the junction between the first epitaxial layer 101 and the second epitaxial layer 102 can be utilized to transfer avalanche current.

Essentially, the semiconductor device according to the embodiment includes a plurality of semiconductor devices having a single substrate including a substrate layer, a plurality of trench regions provided on the substrate layer, and each trench region includes a trench. A first epitaxial layer of a first conductivity type and a second epitaxial layer of a second conductivity type disposed on the first epitaxial layer, wherein each trench of the plurality of trench regions extends through the second epitaxial layer to a third epitaxial layer. in an epitaxial layer, thereby isolating adjacent semiconductor devices among the plurality of semiconductor devices.

FIG. 3 shows a partial structure of a semiconductor device 350 according to an embodiment. This example embodiment consists of two integrated transistors, but in actual practice more than two devices may be integrated in one chip. This embodiment includes a single substrate. The single substrate includes a substrate layer 100 , an epitaxial layer 101 having one doping type, and a second epitaxial layer 102 having an opposite doping type to that of the epitaxial layer 101 . The second epitaxial layer 102 is divided into regions 102a and 102b by trenches 401. The initial substrate layer 100 may be a silicon substrate, and it may be doped to n-type or p-type. Epitaxial layer 101 may be an n-type doped silicon layer. The second epitaxial layer 102 may be a p-type doped silicon layer. Device-1001 includes transition layer 201a, channel layer 202a, barrier layer 203a, source electrode 301a, gate electrode 302a, and drain electrode 303a. The transition layer 201a may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The channel layer 202a may be one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The barrier layer 203a may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. At least one of the barrier layers 203a has a larger band gap than the channel layer 202a. Source electrode 301a of device-1001 is electrically connected to second epitaxial layer 102a. Device-2002 includes transition layer 201b, channel layer 202b, barrier layer 203b, source electrode 301b, gate electrode 302b, and drain electrode 303b. The transition layer 201b may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The channel layer 202b may be one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The barrier layer 203b may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. At least one of the barrier layers 203b has a larger band gap than the channel layer 202b. The source electrode 301b of Device-2 is electrically connected to the second epitaxial layer 102b. Device-1001 and Device-2002 are separated by trench isolation region 003. Trench isolation region 003 includes trench 401 extending into epitaxial layer 101 . Trench 401 may be filled with an insulating material such as SiO ₂ , SiN _x , Al ₂ O ₃ , etc. Trench 401 may also be filled with a combination of insulating materials such as SiO ₂ , SiN _x , Al ₂ O _{3 ,} etc., and conductive materials such as metals, polysilicon, etc., but at least there should be insulating materials. The platform of the present invention has substrate contact electrodes 306. In applications such as bridge circuits, the substrate contact electrode 306 may be electrically connected to the drain of the high side device or the cathode of the high side device. Substrate contact electrode 306 may also be floating. According to the high-voltage integrated circuit platform of the present invention, devices in the platform are isolated from each other, thus avoiding back-gate problems. Additionally, the junction between epitaxial layer 101 and epitaxial layer 102 provides the ability to carry avalanche current.

Figure 4 shows a partial structure of a semiconductor device 450 in which two diodes are separated by a trench according to another embodiment. This example embodiment consists of two integrated diodes, but in actual practice more than two devices may be integrated in one chip. This embodiment includes a single substrate. The single substrate includes a substrate layer 100 , an epitaxial layer 101 having one doping type, and a second epitaxial layer 102 having an opposite doping type to that of the epitaxial layer 101 . The second epitaxial layer 102 is divided into regions 102a and 102b by trenches 401. The initial substrate layer 100 may be a silicon substrate, and it may be doped to n-type or p-type. Epitaxial layer 101 may be an n-type doped silicon layer. The second epitaxial layer 102 may be a p-type doped silicon layer. Device-1001 includes transition layer 201a, channel layer 202a, barrier layer 203a, anode electrode 304a, and cathode electrode 305a. The transition layer 201a may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The channel layer 202a may be one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The barrier layer 203a may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. At least one of the barrier layers 203a has a larger band gap than the channel layer 202a. Anode electrode 304a of device-1001 is electrically connected to second epitaxial layer 102a. Device-2002 includes transition layer 201b, channel layer 202b, barrier layer 203b, anode electrode 304b, and cathode electrode 305b. The transition layer 201b may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The channel layer 202b may be one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The barrier layer 203b may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. At least one of the barrier layers 203b has a larger band gap than the channel layer 202b. Anode electrode 304b of device-2002 is electrically connected to second epitaxial layer 102b. Device-1001 and Device-2002 are separated by trench isolation region 003. Trench isolation region 003 includes trench 401 extending into epitaxial layer 101 . Trench 401 may be filled with an insulating material such as SiO ₂ , SiN _x , Al ₂ O ₃ , etc. Trench 401 may also be filled with a combination of insulating materials such as SiO ₂ , SiN _x , Al ₂ O _{3 ,} etc., and conductive materials such as metals, polysilicon, etc., but at least there should be insulating materials. The platform of the present invention has substrate contact electrodes 306. In applications such as bridge circuits, the substrate contact electrode 306 may be electrically connected to the cathode of the high side device or the drain of the high side device. Substrate contact electrode 306 may also be floating. According to the high-voltage integrated circuit platform of the present invention, devices in the platform are isolated from each other, thus avoiding back-gate problems. Additionally, the junction between epitaxial layer 101 and epitaxial layer 102 provides the ability to carry avalanche current.

Figure 5 shows a partial structure of a semiconductor device 550 in which transistors and diodes are separated by trenches according to another embodiment. The example embodiment consists of one transistor and one diode, but in actual practice more than two devices may be integrated in one chip. The platform includes a substrate. The substrate includes an initial substrate layer 100 , an epitaxial layer 101 having one doping type, and a second epitaxial layer 102 having an opposite doping type to that of the epitaxial layer 101 . The second epitaxial layer 102 is divided into regions 102a and 102b by trenches 401. The initial substrate layer 100 may be a silicon substrate, and it may be doped to n-type or p-type. Epitaxial layer 101 may be an n-type doped silicon layer. The second epitaxial layer 102 may be a p-type doped silicon layer. Device-1001 includes transition layer 201a, channel layer 202a, barrier layer 203a, source electrode 301a, gate electrode 302a, and drain electrode 303a. The transition layer 201a may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The channel layer 202a may be one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The barrier layer 203a may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. At least one of the barrier layers 203a has a larger band gap than the channel layer 202a. Source electrode 301a of device-1001 is electrically connected to second epitaxial layer 102a. Device-2002 includes transition layer 201b, channel layer 202b, barrier layer 203b, anode electrode 304b, and cathode electrode 305b. The transition layer 201b may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The channel layer 202b may be one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. The barrier layer 203b may include one of GaN, AIN, InN, AlGaN, InGaN, AlInGaN, etc. or a combination thereof. At least one of the barrier layers 203b has a larger band gap than the channel layer 202b. Anode electrode 304b of device-2002 is electrically connected to second epitaxial layer 102b. Device-1001 and Device-2002 are separated by trench isolation region 003. Trench isolation region 003 includes trench 401 extending into epitaxial layer 101 . Trench 401 may be filled with an insulating material such as SiO ₂ , SiN _x , Al ₂ O ₃ , etc. The trench 401 can also be filled with a combination of insulating materials such as SiO ₂ , SiN _x , Al ₂ O ₃ , etc., and conductive materials such as metal, polysilicon, etc., but at least insulating materials are required. The platform of the present invention has substrate contact electrodes 306. In applications such as bridge circuits, substrate contact electrode 306 may be electrically connected to the drain or cathode of the high side device. Substrate contact electrode 306 may also be floating. According to the high-voltage integrated circuit platform of the present invention, devices in the platform are isolated from each other, thus avoiding back-gate problems. Additionally, the junction between epitaxial layer 101 and epitaxial layer 102 provides the ability to carry avalanche current.

Since many modifications, variations and alterations are possible in the described preferred embodiments of the invention, it is intended that all matter in the foregoing description and shown in the accompanying drawings be construed as illustrative and not restrictive. Accordingly, the scope of the invention should be determined by the appended claims and their legal equivalents.

Claims (11)

1. A semiconductor device, comprising:

a plurality of semiconductor devices having a single substrate; and

a plurality of trench regions, each trench region comprising a trench,

wherein the single substrate comprises a substrate layer, a first epitaxial layer of a first conductivity type disposed on the substrate layer, and a second epitaxial layer of a second conductivity type disposed on the first epitaxial layer such that the second epitaxial layer forms a PN junction with the first epitaxial layer;

wherein each trench of the plurality of trench regions extends through the second epitaxial layer into the first epitaxial layer, thereby isolating adjacent semiconductor devices of the plurality of semiconductor devices;

the plurality of semiconductor devices are group III nitride semiconductor devices, and a source electrode of each of the plurality of semiconductor devices is connected to the second epitaxial layer.

2. The semiconductor device according to claim 1, wherein the plurality of semiconductor devices are selected from diodes and/or transistors.

3. The semiconductor device of claim 1, wherein each trench of the plurality of trench regions is filled with an insulating material.

4. The semiconductor device of claim 3, wherein said insulating material is selected from the group consisting of SiO ₂ 、SiN _x And/or Al ₂ O ₃ 。

5. The semiconductor device of claim 3, wherein each trench is further filled with a conductive material.

6. The semiconductor apparatus of claim 1, wherein each of the plurality of semiconductor devices comprises:

a transition layer disposed on the second epitaxial layer;

a channel layer disposed on the transition layer;

a barrier layer disposed on the channel layer, the barrier layer comprising a material having a band gap greater than a band gap of the channel layer; and

the source electrode is in contact with the barrier layer and electrically connected to the second epitaxial layer.

7. The semiconductor device of claim 6, wherein the transition layer comprises one or more materials selected from GaN, alN, inN, alGaN, inGaN and AlInGaN.

8. The semiconductor device of claim 6, wherein the channel layer comprises one or more materials selected from GaN, alN, inN, alGaN, inGaN and AlInGaN.

9. The semiconductor device of claim 6, wherein the barrier layer comprises one or more materials selected from GaN, alN, inN, alGaN, inGaN and AlInGaN.

10. A method of manufacturing a semiconductor device, comprising:

providing a single substrate;

forming a plurality of semiconductor devices on the single substrate, the plurality of semiconductor devices being group III nitride semiconductor devices; and

isolating adjacent semiconductor devices by forming a plurality of trench regions such that the plurality of trench regions extend into the single substrate;

wherein providing a single substrate comprises:

providing a substrate;

forming a first epitaxial layer of a first conductivity type on the substrate; and

forming a second epitaxial layer of a second conductivity type on the first epitaxial layer such that the second epitaxial layer and the first epitaxial layer form a PN junction;

wherein a source electrode of each semiconductor device of the plurality of semiconductor devices is connected to the second epitaxial layer, and each trench of the plurality of trench regions extends through the second epitaxial layer into the first epitaxial layer, thereby isolating adjacent semiconductor devices of the plurality of semiconductor devices.

11. The method of claim 10, wherein forming the plurality of trench regions comprises:

etching is performed to form a trench in each trench region of the plurality of trench regions such that the trench passes through the second epitaxial layer and extends into the first epitaxial layer; and

the trench is filled with at least one insulating material.