CN102569094A - Method for reducing gate-induced drain leakage of semiconductor device - Google Patents
Method for reducing gate-induced drain leakage of semiconductor device Download PDFInfo
- Publication number
- CN102569094A CN102569094A CN201210047367XA CN201210047367A CN102569094A CN 102569094 A CN102569094 A CN 102569094A CN 201210047367X A CN201210047367X A CN 201210047367XA CN 201210047367 A CN201210047367 A CN 201210047367A CN 102569094 A CN102569094 A CN 102569094A
- Authority
- CN
- China
- Prior art keywords
- side wall
- semiconductor device
- drain
- ion
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 229910052724 xenon Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000011982 device technology Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 20
- 239000002019 doping agent Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 6
- 239000002800 charge carrier Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method for reducing gate-induced drain leakage of a semiconductor device. The method comprises the following steps of: growing a layer of side wall film on a substrate on which a shallow trench isolation process has been finished on the two sides; covering a drain of the semiconductor device by using photoresist; carrying out ion implantation on the side wall film of a source; removing the photoresist so as to etch the side wall film; forming a side wall on a gate of the semiconductor device; adjusting a side wall etching menu so that the etched side wall source is narrowed and the drain is widened; and carrying out a source and drain heavy doping and annealing process. According to the invention, without changing the effective length of the trench, the longitudinal electric field intensity of the drain end is reduced so that the gate-induced drain leakage current of the semiconductor device is reduced.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field, relate in particular to a kind of method that semiconductor device gate is induced drain leakage that reduces.
Background technology
Gate-induced drain leaks (GIDL; Gate-Induced Drain Leakage) is meant, when device is turn-offing under the situation of (off-state) (being Vg=0), if drain electrode links to each other with Vdd (being Vd=Vdd); Because the overlapping between grid and the drain electrode; Can there be highfield in overlapping region between grid and drain electrode, and band-to-band-tunneling effect (Band-to-band Tunneling) can take place under the highfield effect charge carrier, thereby causes the leakage current between the drain-to-gate.
The gate-induced drain leakage current has become the one of the main reasons of aspects such as influencing small size MOS device reliability, power consumption, and it also has material impact to the erasable operation of memory devices such as EEPROM simultaneously.When technology gets into sub-micro after the epoch, owing to device size dwindles day by day, numerous integrity problems of GIDL electric current initiation become serious further.
Chinese patent CN 101350301A discloses a kind of semiconductor device and manufacturing approach thereof; This manufacturing approach can comprise: on Semiconductor substrate, optionally form the oxide layer pattern; On identical substrate, form the insulating barrier pattern to cover the marginal portion of this oxide layer pattern; This oxide layer pattern of etching and this substrate are to form groove and corresponding to the first and second oxide layer patterns of this oxide layer pattern marginal portion; Form the 3rd oxide layer pattern on the substrate in groove and comprise the gate insulator of first, second and the 3rd oxide layer pattern, and in this groove, form the grid pattern with generation.This method technology is comparatively complicated.
Usually in the technology, the side wall etching technics at first is to carry out side wall film 1 deposition on 0 surface of the substrate with grid 3 shown in Figure 1A ~ 1C, and the cross section of deposition back device is shown in Figure 1A; Next adopt anisotropic dry etching, 2 one-tenth symmetrical structures of side wall of source-drain electrode top after the etching are shown in Figure 1B; Be that heavy doping and annealing process are leaked in the source then, the source is leaked the dopant ion that forms and is distributed shown in Fig. 1 C, and dopant ion is apart from the distance of device channel, is determined by the width of side wall 2.
Summary of the invention
Problem to above-mentioned existence; The purpose of this invention is to provide a kind of method that semiconductor device gate is induced drain leakage that reduces; Keeping under the constant situation of raceway groove effective length (Effective Channel Length); Reduced the longitudinal electric field intensity of drain terminal, caused drain leakage current thereby reduced semiconductor device gate, technology is simple.
The objective of the invention is to realize through following technical proposals:
A kind ofly reduce the method that semiconductor device gate is induced drain leakage, wherein, comprise the following steps:
Accomplished growth one deck side wall film on the substrate of both sides shallow ditch groove separation process one;
Cover the drain electrode of semiconductor device with photoresist, the side wall film of source electrode is carried out ion inject;
Remove photoresist, the side wall film is carried out etching, on the grid of semiconductor device, form side wall, regulate side wall etching menu so that the width of the side wall source electrode after the etching reduces, the width of drain electrode increases;
Carry out the source and leak heavy doping and annealing process.
In another embodiment of the present invention, the side wall film of source electrode top being carried out the ion that ion injects is xenon ion or germanium ion.
In yet another embodiment of the present invention, in 45nm cmos device technology, adopt Ge element that the side wall film above the source electrode is carried out ion before the side wall etching and inject in advance.
In another embodiment of the present invention, has the low doping source drain region respectively at the intersection of substrate source electrode and grid and the intersection of drain electrode and grid.
In yet another embodiment of the present invention, said side wall film is silica or silicon nitride film.
In another embodiment of the present invention, the side wall film is carried out etching and adopt dry etching.
Compared with present technology, beneficial effect of the present invention is:
1, after the side wall thin film growth process is accomplished; Before carrying out etching technics; Utilize the drain terminal of photoresist covering device; Adopt neutral element (like germanium, xenon etc.) that the side wall film of source end is carried out ion and inject, the effect of injection is to increase the part that the is injected into side wall etch rate with respect to remainder.
2, after the side wall etching, the distolateral wall width in source reduces, and the drain terminal lateral wall width increases, and after heavy doping injection and annealing process were leaked in the source, the dopant ion of source end and channel distance were furthered, and the dopant ion of drain terminal and channel distance are zoomed out.
3, at drain terminal; Because the distance between heavy doping ion and raceway groove is zoomed out, drain when gate turn-off when meeting Vdd, weaken in the electric field strength of grid and drain terminal overlapping region; Thereby reduced the band-to-band-tunneling effect of charge carrier, reduced semiconductor device gate and caused drain leakage current.
4, when the distance of the dopant ion of drain terminal and raceway groove is zoomed out; The dopant ion of source end and the distance of raceway groove are furthered; Therefore the length of effective channel (Effective Channel Length) of device remains unchanged basically, and other performances of device are able to keep.
Description of drawings
Figure 1A, Figure 1B and Fig. 1 C are the side wall etching technics step sketch mapes of traditional handicraft;
Fig. 2 is that the present invention reduces the schematic flow sheet that semiconductor device gate is induced the method for drain electrode leakage;
Fig. 3 A, Fig. 3 B and Fig. 3 C are that the present invention reduces the method step sketch map that semiconductor device gate is induced drain leakage.
Embodiment
Below in conjunction with schematic diagram and concrete operations embodiment the present invention is described further.
Referring to shown in Figure 2, the present invention reduces semiconductor device gate and induces the method for drain leakage specifically to comprise the following steps:
Accomplished growth one deck side wall film 1 on the substrate 0 of both sides shallow ditch groove separation process (STI) 4 one; Side wall film 1 can be silica or silicon nitride film; Has low doping source drain region (LDD) 8 respectively at the intersection of substrate source electrode and grid and the intersection of drain electrode and grid; Shown in Fig. 3 A, with photoresist 5 cover semiconductor device drain electrode 7, the side wall film 1 of source electrode 6 is carried out ion injects.In a specific embodiment of the present invention; It is xenon ion or germanium ion that the side wall film 1 of source electrode 6 tops is carried out the ion that ion injects; In 45nm cmos device technology; Adopt before the side wall etching Ge element that the side wall film 1 of source electrode top is carried out ion and inject in advance, the effect of injection is to increase the part that the is injected into side wall etch rate with respect to remainder.
Remove photoresist 5, side wall film 1 is carried out etching, side wall film 1 is carried out the etching employing have anisotropic dry etching; On the grid 3 of semiconductor device, form side wall 2, regulate side wall etching menu (recipe) so that the width of the side wall source electrode 6 after the etching reduces, the width of drain electrode 7 increases; Shown in Fig. 3 B; Because the etch rate of the distolateral wall film in source will be higher than the etch rate of drain terminal side wall film, suitably regulates side wall etching menu, the side wall 2 after the final etching; Width at source electrode 6 can reduce, and can increase at drain electrode 7 width.
Carry out the source and leak heavy doping and annealing process, the semiconductor sectional view after final the completion is shown in Fig. 3 C.Because the distance of dopant ion and device channel is determined by the width of side wall 2; Therefore after mixing; The dopant ion of source end and the distance of device channel are furthered; The dopant ion of drain electrode 7 and the distance of device channel are zoomed out, but owing to the width sum of source leakage side wall remains unchanged, so the distance that leak between the heavy doping ion in the source remains unchanged.
In drain electrode 7; Because the distance between heavy doping ion and raceway groove is zoomed out,, weaken in the electric field strength of grid 3 with drain electrode 7 overlapping regions when grid 3 turn-offs and drains 7 when meeting Vdd; Thereby reduced the band-to-band-tunneling effect of charge carrier, reduced semiconductor device gate and caused drain leakage current.In addition; Because when the distance of drain electrode 7 heavy doping ion and raceway groove is zoomed out; The heavy doping ion of source electrode 6 and the distance of raceway groove are furthered, and the distance that leak between the heavy doping ion in total source remains unchanged, so the length of effective channel of device remains unchanged basically; Other performances of device are able to keep, and technology is simple.
More than specific embodiment of the present invention is described in detail, but the present invention is not restricted to the specific embodiment of above description, it is just as example.To those skilled in the art, any equivalent modifications and alternative also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of having done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (6)
1. one kind reduces the method that semiconductor device gate is induced drain leakage, it is characterized in that, comprises the following steps:
Accomplished growth one deck side wall film on the substrate of both sides shallow ditch groove separation process one;
Cover the drain electrode of semiconductor device with photoresist, the side wall film of source electrode is carried out ion inject;
Remove photoresist, the side wall film is carried out etching, on the grid of semiconductor device, form side wall, regulate side wall etching menu so that the width of the side wall source electrode after the etching reduces, the width of drain electrode increases;
Carry out the source and leak heavy doping and annealing process.
2. the semiconductor device gate that reduces as claimed in claim 1 is induced the method that drains and reveal, and it is characterized in that, the ion that the side wall film above the source electrode is carried out the ion injection is xenon ion or germanium ion.
3. the semiconductor device gate that reduces as claimed in claim 2 is induced the method that drains and reveal, and it is characterized in that, in 45nm cmos device technology, adopts Ge element that the side wall film above the source electrode is carried out ion before the side wall etching and injects in advance.
4. the semiconductor device gate that reduces as claimed in claim 1 is induced the method that drains and reveal, and it is characterized in that having the low doping source drain region respectively at the intersection of substrate source electrode and grid and the intersection of drain electrode and grid.
5. induce the method that drains and reveal like any described semiconductor device gate that reduces in the claim 1 to 4, it is characterized in that said side wall film is silica or silicon nitride film.
6. induce the method that drains and reveal like any described semiconductor device gate that reduces in the claim 1 to 4, it is characterized in that, the side wall film is carried out etching adopt dry etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210047367XA CN102569094A (en) | 2012-02-28 | 2012-02-28 | Method for reducing gate-induced drain leakage of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210047367XA CN102569094A (en) | 2012-02-28 | 2012-02-28 | Method for reducing gate-induced drain leakage of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102569094A true CN102569094A (en) | 2012-07-11 |
Family
ID=46414198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210047367XA Pending CN102569094A (en) | 2012-02-28 | 2012-02-28 | Method for reducing gate-induced drain leakage of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102569094A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060281273A1 (en) * | 2005-06-09 | 2006-12-14 | Seiko Epson Corporation | Semiconductor device and manufacturing method of the semiconductor device |
| KR20070046459A (en) * | 2005-10-31 | 2007-05-03 | 삼성전자주식회사 | Semiconductor device including LD transistor and method for forming same |
| CN101641770A (en) * | 2007-03-28 | 2010-02-03 | 富士通微电子株式会社 | Semiconductor device and manufacturing method thereof |
-
2012
- 2012-02-28 CN CN201210047367XA patent/CN102569094A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060281273A1 (en) * | 2005-06-09 | 2006-12-14 | Seiko Epson Corporation | Semiconductor device and manufacturing method of the semiconductor device |
| KR20070046459A (en) * | 2005-10-31 | 2007-05-03 | 삼성전자주식회사 | Semiconductor device including LD transistor and method for forming same |
| CN101641770A (en) * | 2007-03-28 | 2010-02-03 | 富士通微电子株式会社 | Semiconductor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20140312393A1 (en) | Fin-fet transistor with punchthrough barrier and leakage protection regions | |
| US20080048217A1 (en) | Semiconductor device and method of fabricating the same | |
| CN105448916A (en) | Transistor and method of forming same | |
| US20160111322A1 (en) | Finfet semiconductor device having local buried oxide | |
| CN102074476B (en) | Forming method of N-channel metal oxide semiconductor (NMOS) transistor | |
| US9263345B2 (en) | SOI transistors with improved source/drain structures with enhanced strain | |
| CN102800595A (en) | NMOS (N-Channel Metal Oxide Semiconductor) transistor forming method and corresponding COMOS structure forming method | |
| CN104916540A (en) | Strain channel transistor and manufacturing method thereof | |
| CN104992943B (en) | The process for making of SONOS memories | |
| CN103094343A (en) | MOSFET structure with T-shaped epitaxial silicon channel | |
| CN102110636A (en) | Methods for improving reverse narrow channel effect and manufacturing metal oxide semiconductor (MOS) transistor | |
| KR101213723B1 (en) | Semiconductor device and Method for fabricating the same | |
| CN102903636B (en) | Manufacturing method of MOS (metal oxide semiconductor) transistor | |
| CN102593003B (en) | Method for reducing induction drain electrode leakage of semiconductor device gate | |
| CN102709162B (en) | Form the method for germanium-silicon groove and PMOS transistor | |
| KR101140060B1 (en) | semiconductor device and Method for fabricating the same | |
| CN102569094A (en) | Method for reducing gate-induced drain leakage of semiconductor device | |
| CN102903635B (en) | Manufacturing method of MOS (metal oxide semiconductor) transistor | |
| KR20120120038A (en) | Mos semiconductor device and methods for its fabrication | |
| CN102610528B (en) | Method for reducing grid induction drain leakage of semiconductor device and method for manufacturing metal oxide semiconductor (MOS) device | |
| CN102610506A (en) | Method for etching bi-grid oxide layer in BCD technology | |
| CN102005388B (en) | N-type metal oxide semiconductor source drain implantation method | |
| KR101068137B1 (en) | High voltage transistor manufacturing method | |
| KR20060027525A (en) | Method for manufacturing a semiconductor device having a recessed channel region | |
| CN102427062A (en) | Self-aligned channel doping suppression CMOS short channel effect and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120711 |