KR20060027525A - Method for manufacturing a semiconductor device having a recessed channel region - Google Patents

Abstract

A method of manufacturing a semiconductor device having a recessed channel region having a void-free gate electrode is disclosed. The disclosed invention forms a device isolation film on a semiconductor substrate including a cell region and a peripheral region, and then forms a trench in a selected region of a gate electrode predetermined region of the semiconductor substrate, and forms a gate insulating film on the surface of the semiconductor substrate. do. A first polycrystalline silicon film including N-type impurities is formed on the gate insulating layer so as to fill the trench, and the first polycrystalline silicon film is removed by a predetermined thickness. After forming a second polycrystalline silicon film on the first polycrystalline silicon film, the second polycrystalline silicon film is partially patterned to form transistor gate electrodes in the cell region and the peripheral region.

Recessed Channel (RCAT), Dual Poly,

Description

Method of manufacturing a semiconductor device having a recessed channel region {Method of forming a semiconductor device having a recessed transistor channel region}

1A to 1C are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device having a recessed channel region in the related art.

2 to 9 are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device having a recessed channel region according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 110 trench

120, 125: low concentration diffusion layer 130: first polycrystalline silicon film

135 second polycrystalline silicon film 170a, 170b, 170c: gate electrode

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a recessed channel region.

In general, a transistor includes a gate electrode (a word line in the case of a memory device) formed on a semiconductor substrate, and a source and a drain region formed in the semiconductor substrate so as to overlap both sides of the gate electrode. In addition, when a predetermined voltage is applied to the gate electrode, source and drain regions of the transistor, a channel is formed under the gate electrode, that is, between the source and drain regions.

Such widths and channel lengths of gate electrodes are gradually decreasing with decreasing design rules of semiconductor devices. However, when the width and channel length of the gate electrode are reduced as described above, the integration density of the semiconductor device is improved, but drain induced barrier lowering (DIBL), hot carrier effect, and punch-through ( Short channel effects such as punch through occur.

In order to solve the above short channel effect, a recessed channel structure has been proposed in which a gate electrode is embedded in a substrate. The gate electrode of a transistor having a recessed channel structure is formed in a trench formed in the substrate, and the channel is formed over the trench sidewalls and the bottom surface. As a result, the width of the gate electrode is relatively reduced, but the effective channel length is ensured to be greater than or equal to the gate electrode width. Accordingly, it is possible to control a problem such as a short channel effect of the planar type transistor of the highly integrated semiconductor device and a change in the threshold voltage Vt caused by the same. Here, a semiconductor device having a conventional recessed channel region can be controlled. A manufacturing method will be described with reference to FIGS. 1A to 1C.

First, as shown in FIG. 1A, the device isolation layer 20 is formed on a semiconductor substrate 10 including a cell region and a peripheral region peri by a known method. After that, a trench 30 is formed with a predetermined gate electrode line width to form a gate electrode recessed in the cell region. Next, a gate insulating film 40 is formed on the surface of the semiconductor substrate 10.

As shown in FIG. 1B, the polycrystalline silicon film 50 for the gate electrode is formed on the semiconductor substrate 10 formed with the gate insulating film 40. The polycrystalline silicon film 50 is a doped polysilicon film containing N-type impurities. In this case, as the N-type impurities, arsenic (Arsenic) or phosphorus (Phosphorus) and the like may be used. The polycrystalline silicon film 50 is deposited at a temperature range of 570 to 650 ° C., and the N-type impurity is introduced into the polycrystalline silicon film 50 simultaneously with the deposition of the polysilicon film 50.

At this time, using the polysilicon film doped with N-type impurities at the same time as the polycrystalline silicon film 50 is deposited, the thickness and the peripheral region of the polycrystalline silicon film 50 present in the trench 30 of the cell region (cell). Since the thicknesses of the polycrystalline silicon films 50 on the upper surface of the substrate 10 of peri are different from each other, it is not easy to set the proper ion implantation energy to the two regions in order to implant impurities by the ion implantation method. Thereafter, as shown in FIG. 1C, the photoresist pattern 75 is formed on the polycrystalline silicon film 50 so that the region PMOS on which the PMOS transistor is to be formed is exposed. Thereafter, in order to improve the driving capability of the PMOS transistor, a high concentration of P-type impurity is implanted into the polycrystalline silicon film 50 of the exposed PMOS transistor region (PMOS). In this case, as a high concentration of P-type impurities, boron (Boron) or boron fluoride (BF ₂ ) may be used. That is, in order to improve the driving capability of the PMOS transistor, it is preferable that the gate electrode of the PMOS transistor is made of a P-type polysilicon film. Accordingly, a high concentration of P-type impurities is counter-doped to the N-type polysilicon film 50 so that the polysilicon film of the PMOS transistor region PMOS may have a P-type.

However, in order to counter-dope a polysilicon film containing a high concentration of N-type impurities to P-type, P-type impurities having a high concentration of 5 예컨대 E ¹⁵ / cm ² or more, such as BF ₂ ions, must be implanted. However, when an ion such as BF ₂ is ion-implanted at such a high concentration, a large amount of voids 80 are generated in a region where an impurity doping concentration due to ion implantation energy peaks. That is, the void 80 is piled up with F (fluorine) of BF ₂ ions in a region where the impurity concentration of BF ₂ ions peaks, and the heat treatment process is performed in a state where the florin is piled up. As it proceeds, voids 80 such as fluorine bubbles are generated in the polycrystalline silicon film 50.

Such voids 80 are generated on the polycrystalline silicon film 50a (that is, the gate electrode of the PMOS transistor) in the PMOS transistor region into which the P-type impurities are ion-implanted, which causes a decrease in the driving capability of the PMOS transistor. It can also cause fatal defects.

Accordingly, a technical object of the present invention is to provide a method of manufacturing a semiconductor device having a recessed channel region having a void-free gate electrode.

In order to achieve the technical problem of the present invention, a method of manufacturing a semiconductor memory device having a recessed transistor channel according to an embodiment of the present invention is as follows.

First, an isolation layer is formed on a semiconductor substrate including a cell region and a peripheral region. Then, a trench is formed in a region selected from predetermined regions of the gate electrode of the semiconductor substrate, and a gate insulating layer is formed on the surface of the semiconductor substrate. A first polycrystalline silicon film including N-type impurities is formed on the gate insulating layer so as to fill the trench, and the first polycrystalline silicon film is removed by a predetermined thickness. After forming a second polycrystalline silicon film on the first polycrystalline silicon film, the second polycrystalline silicon film is partially patterned, and then a layer is patterned to form a transistor gate in the NMOS region of the cell region and the NMOS and PMOS regions of the peripheral region. Form an electrode.

The trench is formed in a cell region of the semiconductor substrate.

The removing of the first polycrystalline silicon layer may be performed by one of chemical mechanical polishing and etching back. In the removing of the first polycrystalline silicon film, the first polycrystalline silicon film may be removed so as to remain on the gate insulating film by a predetermined thickness. In the removing of the first polycrystalline silicon layer, chemical mechanical polishing or etch back may be performed until the surface of the device isolation layer is exposed.                     

The method may further include injecting impurities to control the threshold voltage of the peripheral region between the forming of the device isolation layer and the forming of the trench. The method may further include sequentially depositing a metal film and a hard mask film on the second polycrystalline silicon film between the forming of the second polycrystalline silicon film and the patterning of the second polycrystalline silicon film. The metal film and the hard mask film are simultaneously patterned when the second polycrystalline silicon film is patterned.

The second polycrystalline silicon film may be a polycrystalline silicon film that is not doped with impurities. In this case, between the forming of the second polycrystalline silicon film and the patterning of the second polycrystalline silicon film, a high concentration N is selectively added to the second polycrystalline silicon film corresponding to the NMOS transistor predetermined region of the cell region and the peripheral region. Doping may further comprise the step of doping. Alternatively, between the forming of the second polycrystalline silicon film and the patterning of the second polycrystalline silicon film, a high concentration P-type impurity is selectively doped into the second polycrystalline silicon film corresponding to a predetermined region of the PMOS transistor in the peripheral region. The second polycrystalline silicon film may be a doped polycrystalline silicon film doped with P-type impurities simultaneously with deposition. In this case, between the forming of the second polycrystalline silicon film and the patterning of the second polycrystalline silicon film, a high concentration is formed in the second polycrystalline silicon film of the NMOS transistor predetermined region of the cell region and the NMOS transistor predetermined region of the peripheral region. Selectively doping the N-type impurity.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape of the elements in the drawings are exaggerated in order to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. Figs. 2 to 9 are recessed according to an embodiment of the present invention. It is sectional drawing for each process for demonstrating the manufacturing method of the semiconductor element which has the channel area.

First, referring to FIG. 2, an isolation layer 105 is formed on a semiconductor substrate 100 in which a cell region and a peripheral region peri are defined. As is known, the device isolation layer 105 may be formed by forming a trench by dry etching a predetermined portion of the semiconductor substrate 100, gap filling the inside with an HDP (High Density Plasma) oxide film, and the like. The HDP oxide film can be obtained by a planarization process such as chemical mechanical polishing (CMP) or etch back process. Thereafter, in order to form a transistor having a channel region recessed in a cell region in which semiconductor elements are densely formed, the trench 110 is formed in a gate electrode predetermined region of the cell region by a known method. The gate insulating layer 115 is formed on the semiconductor substrate 100 on which the trench 110 is formed. In order to adjust the threshold voltage of the transistor formed in the peripheral region peri between the forming of the device isolation layer 105 and the forming of the trench 110, a low concentration in the peripheral region peri is selectively selected. The diffusion layer 120 may be formed. The low concentration diffusion layer 120 in the peripheral region is formed by ion implanting, for example, P-type impurities such as boron or boronprolide (BF ₂ ) at a concentration of 1.0E13 to 1.0E14 / cm ² and an energy of 10 to 30 KeV. . In addition, the low concentration diffusion layer 125 may be formed by selectively implanting threshold voltage adjusting ions into the cell region. In this case, since the transistor having the recessed channel is formed in the cell region, the transistor is formed to be relatively deeper than the peripheral region peri, that is, the low concentration diffusion layer 125 is disposed at the bottom of the trench 110. The low concentration diffusion layer 125 of the cell region may be formed by, for example, a plasma doping method recently developed or a method of controlling the energy of ion implantation according to the trench depth after deposition of a sacrificial layer. Since a variety of techniques known in the semiconductor device manufacturing method field is known, it will be omitted in the detailed description of the present invention.

Next, as shown in FIG. 3, a first polycrystalline silicon film 130 including high concentration N-type impurities is deposited on the gate insulating layer 115. The first polycrystalline silicon film 130 is formed to a thickness such that the trench 110 for the gate electrode of the cell region is sufficiently buried. As described above, the first polycrystalline silicon film 130 is doped with a high concentration N-type impurity at the same time as the deposition.

Referring to FIG. 4, the first polycrystalline silicon film 130 is removed by a predetermined thickness. The first polycrystalline silicon film 131 is removed by, for example, a partial CMP or etch back process. In order to prevent damage to the gate insulating layer 115, the first polycrystalline silicon layer 130 may be removed to remain on the gate insulating layer 115 and the device isolation layer 105 by a predetermined thickness. Alternatively, as shown in FIG. 5, the first polycrystalline silicon film 132 may be CMP until the surface of the device isolation film 105 protruding the surface of the semiconductor substrate 100 by a predetermined thickness is exposed.

Next, as shown in FIG. 6, a second polycrystalline silicon film 135 not doped with impurities is deposited on the first polycrystalline silicon film 131 or 132. In the present embodiment, the case of FIG. 4 will be described as an example.

The second polycrystalline silicon film 135 is a layer to be used as a substantially gate electrode of the NMOS and PMOS transistors, and impurity doping is required to match the conductivity type of each MOS transistor. To this end, as shown in FIG. 7, the first photoresist pattern 140 is formed on the second polycrystalline silicon film 135 to expose the NMOS transistor region NMOS. Thereafter, an N-type impurity 145 is doped on the second polycrystalline silicon film 135 in the exposed NMOS transistor region NMOS. Here, reference numeral 135a denotes a second polycrystalline silicon film doped with N-type impurities, and 131a denotes a first polycrystalline silicon film doped with N-type impurities, and an ion implantation method or a plasma doping method is used as the doping method. Can be.

After the first photoresist pattern 140 is removed in a known manner, as shown in FIG. 8, the second photoresist pattern 150 is formed to expose the PMOS transistor region PMOS. The second polycrystalline silicon film 130 of the exposed PMOS transistor region is doped with a P-type impurity 155, for example, BF ₂ . At this time, the concentration of the P-type impurity 155 is lower than that of the conventional P-type impurity that needs to be counter-doped because the impurity is doped into the second polycrystalline silicon film 135 that is not doped. Accordingly, the generation of voids in the second polycrystalline silicon film 135b in the PMOS transistor region PMOS can be reduced. Here, reference numeral 131b is a first polycrystalline silicon film doped with a P-type impurity, and an ion implantation method or a plasma doping method may be used as the doping method, similar to the doping of the N-type impurity. In this case, the doping of the N-type impurities and the doping of the P-type impurities may be reversed. In addition, a polycrystalline silicon film doped with a high concentration of P-type impurities such as an E ¹⁵ / cm 2 concentration boron may be used as the second polycrystalline silicon film 135. In this case, only the process of doping the N-type impurity can be performed, and the process for doping the P-type impurity can be excluded, so that the process can be simplified.

Thereafter, as shown in FIG. 9, the metal layer for reducing the resistance of the gate electrode on the second polycrystalline silicon film 135a and 135b doped with the N-type impurity 145 and the P-type impurity 155 ( 160 and the hard mask film 165 are sequentially deposited. Next, predetermined partial patterning is performed to form the first to third gate electrode structures 170a, 170b, and 170c. Here, the first gate electrode structure 170a includes a gate electrode recessed as a gate electrode of an NMOS transistor in a cell region, and the second gate electrode structure 170b includes a gate of an NMOS transistor in a peripheral region peri. An electrode is formed on the substrate surface. The third gate electrode structure 170c is formed on the substrate surface as the gate electrode of the PMOS transistor in the peripheral region peri. In addition, the first and second gate electrode structures 170a and 170b include a polycrystalline silicon film 130 and / or 135a containing N type impurities, and the third gate electrode structure includes polycrystalline silicon including P type impurities. Film 135b. Thereafter, spacers 175 are formed on both sidewalls of the first to third gate electrode structures 170a, 170b, and 170c in a known manner, and then impurities are injected into the semiconductor substrate 100 on both sides of the spacers 175. Source and drain regions 180a and 180b are formed.

As described in detail above, according to the present invention, the first polycrystalline silicon film containing the high concentration N-type impurity is embedded only in the recessed gate electrode region, that is, the trench portion, and the second polycrystalline silicon film containing no impurities is deposited. Thereafter, the N-type impurities and the P-type impurities are selectively doped at a lower concentration than before.

Accordingly, the ion implantation (doping) of the P-type impurity at a lower concentration than in the prior art can reduce the void caused by the ion implantation of the high concentration P-type impurity. Therefore, not only the electrical characteristics of the gate electrode, in particular, the characteristics of the gate electrode of the PMOS transistor are improved, but also the reliability of the product can be improved.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. Do

Claims (12)

Forming an isolation layer on the semiconductor substrate including the cell region and the peripheral region; Forming a trench in a selected region of a predetermined region of a gate electrode of the semiconductor substrate; Forming a gate insulating film on a surface of the semiconductor substrate; Forming a first polycrystalline silicon film including N-type impurities on the gate insulating layer to fill the trench; Removing the first polycrystalline silicon film by a predetermined thickness; Forming a second polycrystalline silicon film on the first polycrystalline silicon film; And And forming a transistor gate electrode in the NMOS region of the cell region and the NMOS and PMOS regions of the peripheral region by partially patterning the second polycrystalline silicon layer and the first polycrystalline silicon layer of the lower remaining portion. The manufacturing method of the semiconductor element. The method of claim 1, wherein the trench is formed in a cell region of the semiconductor substrate. The method of claim 1, wherein the removing of the first polycrystalline silicon layer is performed by one of chemical mechanical polishing and etching back. The method of claim 1, wherein the removing of the first polycrystalline silicon film comprises removing the first polycrystalline silicon film so as to remain on the gate insulating film by a predetermined thickness. The method of claim 1, wherein removing the first polycrystalline silicon film comprises chemical mechanical polishing or etching back until the surface of the device isolation layer is exposed. The semiconductor device of claim 1, further comprising: implanting an impurity for adjusting the threshold voltage of the peripheral region between the forming of the device isolation layer and the forming of the trench. Method of preparation. . The method of claim 1, further comprising sequentially depositing a metal film and a hard mask film on the second polycrystalline silicon film between the forming of the second polycrystalline silicon film and the patterning of the second polycrystalline silicon film. Including, And the metal film is patterned at the same time when the second polycrystalline silicon film is patterned. 2. The method of claim 1, wherein the second polycrystalline silicon film is a polycrystalline silicon film that is not doped with impurities. 9. The method of claim 8, wherein between the forming of the second polycrystalline silicon film and the patterning of the second polycrystalline silicon film, the second polycrystalline silicon film corresponding to a predetermined region of the NMOS transistor in the cell region and the peripheral region is selectively selected. The method of manufacturing a semiconductor device further comprising the step of doping a high concentration of N-type impurities. 10. The method according to claim 8, wherein a high concentration P is selectively added to the second polycrystalline silicon film corresponding to a predetermined region of the PMOS transistor in the peripheral region between the forming of the second polycrystalline silicon film and the patterning of the second polycrystalline silicon film. A method of manufacturing a semiconductor device, further comprising the step of doping a type impurity. The method of manufacturing a semiconductor device according to claim 1, wherein the second polycrystalline silicon film is a doped polycrystalline silicon film doped with P-type impurities simultaneously with deposition. 12. The second polycrystal of the predetermined region of the NMOS transistor in the cell region and the predetermined region of the NMOS transistor in the peripheral region between the step of forming the second polycrystalline silicon film and patterning the second polycrystalline silicon film. And selectively doping a high concentration of N-type impurities into the silicon film.

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