CN102005388B - N-type metal oxide semiconductor source drain implantation method - Google Patents

Abstract

The invention discloses an N-type metal oxide semiconductor source drain implantation method, which comprises the following steps of: forming a grid structure of an NMOS (N-type metal oxide semiconductor) above an N well of a semiconductor substrate of a silicon chip; performing LDD (lightly doped drain) injection on the semiconductor substrate on two sides of the NMOS grid structure; forming side walls of the NMOS grid structure; and performing photo-etching and ion implantation of an NMOS source drain area on the semiconductor substrate on two sides of the side walls of the NMOS grid structure, wherein the order of the ion implantation is germanium (Ge), phosphorus (P), arsenic (As) and P. The method improves the performance of the NMOS.

Description

Method for implanting is leaked in N type metal oxide semiconductor source

Technical field

The present invention relates to semiconductor components and devices manufacturing technology field, be specifically related to N type metal oxide semiconductor source and leak method for implanting.

Background technology

Fabricate is meant chemistry or the physical operations of on silicon chip, carrying out a series of complicacies.Manufacture craft with complementary metal oxide semiconductors (CMOS) (CMOS) is example, and is as shown in Figure 1, mainly comprises:

Step 101: on the Semiconductor substrate of silicon chip, form N trap, P trap and shallow channel isolation area (STI).

In the existing CMOS manufacture craft, the first step is to adopt twin well process to define the active area of N type metal oxide semiconductor (NMOS) and P-type mos (PMOS), thereby obtains N trap and P trap.Then, through technologies such as photoetching and etchings, on Semiconductor substrate, form STI.

Step 102:, and utilize technologies such as photoetching and etching above the N trap, to form the grid structure of NMOS, the grid structure of formation PMOS above the P trap at silicon chip surface growth gate oxide and deposit polysilicon.

In this step, at first carry out the growth of gate oxide, promptly silicon chip surface oxidation growth one layer thickness be about 20～50 dusts (

) silicon dioxide (SiO ₂); Then, through chemical vapor deposition method, at silicon chip surface deposit one deck polysilicon, thickness is about 500 Afterwards, through technologies such as photoetching and etchings, produce the grid structure of NMOS pipe and PMOS pipe.Grid structure according to the invention comprises grid that is made up of polysilicon and the gate oxide that is positioned at the grid below.

Step 103: on the Semiconductor substrate of NMOS and PMOS grid structure both sides, carry out lightly doped drain (LDD) respectively and inject.

Under the promotion of demands such as semiconductor device miniatureization, densification, high speed and system integration; The width of grid structure constantly reduces, and the channel length of its below also constantly reduces, thereby has increased the possibility of electric charge break-through between the leakage of source; Make leakage current significantly increase; Therefore, need to adopt some means to reduce the possibility that leakage current occurs, inject like LDD.

Before LDD injects, need at first utilize lithographic definition to go out and to carry out the zone that LDD injects; Then, utilize the dopant material of big quality such as arsenic or boron fluoride to carry out LDD and inject, thereby make the upper surface of silicon chip become amorphous state, big quality materials and surface amorphously help to keep shallow junction, shallow junction helps to reduce leakage current.

Step 104: at silicon chip surface deposit silicon dioxide successively and silicon nitride (Si ₃N ₄).

Step 105: utilize the silicon nitride of dry etch process etching silicon chip surface, form the side wall of the grid structure of NMOS and PMOS.

In etching process, need to keep the silicon dioxide of all around gate structure, so that form side wall, side wall can be used for preventing that the follow-up source of carrying out from leaking when injecting and too leak break-through near raceway groove so that generation source, produces leakage current thereby diffusion takes place the impurity that promptly injects.

Step 106: the photoetching and the ion that on the Semiconductor substrate of the side wall both sides of NMOS grid structure, carry out the NMOS source-drain area inject.

At first utilize lithographic definition to go out and to carry out the NMOS source and drain areas that ion injects; Then, carry out n according to the zone that defines ⁺The source is leaked and is injected, and the side wall that forms in the step 105 can be used in the protection raceway groove.n ⁺The source leak to be injected junction depth that the back forms and is carried out LDD than step 103 to inject the junction depth that the back forms bigger.The ion that injects is generally: phosphorus (P), germanium (Ge), arsenic (As).

Step 107: the silicon dioxide of removing silicon chip surface.

Usually, adopt hydrofluoric acid etc. to remove silicon dioxide.

In practical application, step 107 also can be carried out before step 106, promptly also can in the silicon nitride of removing silicon chip surface, remove silicon dioxide.No matter when carry out, its purpose all is that the follow-up for ease ion that carries out injects, and prevents that the existence of silicon dioxide from causing the ion injection inhomogeneous.

Step 108: the photoetching and the ion that on the Semiconductor substrate of the side wall both sides of PMOS grid structure, carry out the PMOS source-drain area inject.

Utilize lithographic definition to go out equally, earlier and will carry out the PMOS source and drain areas that ion injects; Then, carry out p according to the zone that defines ⁺The source is leaked and is injected, and the side wall that forms in the step 105 can be used in the protection raceway groove.p ⁺The source leak to be injected junction depth that the back forms and is carried out LDD than step 103 to inject the junction depth that the back forms bigger.

In order to improve the performance of NMOS, can adopt following method usually: one, reduce the thickness of gate oxide, its shortcoming is to cause the leakage current of gate oxide to increase; Two, the applied stress engineering method is eliminated the stress of silicon dioxide, and the shortcoming of this method is that processing complexity is higher.

Through experiment showed, when NMOS being carried out source leakage injection, adopt the performance of the different resulting NMOS of ion injection order normally different.Usually adopt the ion injection order of P, Ge, As, P at present, so not only avoided above-mentioned two defectives, and obtained NMOS performance preferably.

Summary of the invention

The present invention provides the NMOS source to leak method for implanting, with the performance of further raising NMOS.

Technical scheme of the present invention is achieved in that

Method for implanting is leaked in a kind of NMOS source, and this method comprises:

Above the N trap of the Semiconductor substrate of silicon chip, form the grid structure of NMOS;

On the Semiconductor substrate of NMOS grid structure both sides, carrying out LDD injects;

Form the side wall of the grid structure of NMOS;

The photoetching and the ion that on the Semiconductor substrate of the side wall both sides of NMOS grid structure, carry out the NMOS source-drain area inject, and the order that ion injects is: Ge, P, As, P.

Said Ge and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 1E15 atomicity/centimetre ²

The said P that injects for the first time and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre ²

Said As and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre ²

The said P that injects for the second time and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre ²

Said Ge and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 1E15 atomicity/centimetre ²

The said P that injects for the first time and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre ²

Said As and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre ²

The said P that injects for the second time and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre ²

Compared with prior art, the present invention is when carrying out the leakage injection of NMOS source, and the ion injection of employing is in proper order: Ge, P, As, P experiment showed, that the present invention has improved the performance of NMOS.

Description of drawings

Fig. 1 is the manufacture method flow chart of conventional semiconductor device;

Fig. 2 leaks the method for implanting flow chart for the NMOS source that the embodiment of the invention provides;

When Fig. 3 leaks method for implanting for adopting source existing and that the embodiment of the invention provides, the ON state current of NMOS and off-state current concern sketch map.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment the present invention is remake further detailed explanation.

Fig. 2 leaks the method for implanting flow chart for the NMOS source that the embodiment of the invention provides, and as shown in Figure 2, its concrete steps are following:

Step 201: on the Semiconductor substrate of silicon chip, form N trap, P trap and STI.

Step 202:, and utilize technologies such as photoetching and etching above the N trap, to form the grid structure of NMOS, the grid structure of formation PMOS above the P trap at silicon chip surface growth gate oxide and deposit polysilicon.

Step 203: on the Semiconductor substrate of NMOS and PMOS grid structure both sides, carry out LDD respectively and inject.

Step 204: deposit silicon dioxide and silicon nitride successively on the sidewall of silicon chip surface and NMOS and PMOS grid structure and surface.

Step 205: utilize the sidewall of dry etch process etching silicon chip surface and NMOS and PMOS grid structure and the silicon nitride on surface; Remove the sidewall of silicon chip surface and NMOS and PMOS grid structure and the silicon nitride on surface, form the side wall of the grid structure of NMOS and PMOS.

In etching process, need to keep the silicon dioxide of all around gate structure, so that form side wall, side wall can be used for preventing that the follow-up source of carrying out from leaking when injecting and too leak break-through near raceway groove so that generation source, produces leakage current thereby diffusion takes place the impurity that promptly injects.

Step 206: the photoetching and the ion that on the Semiconductor substrate of the side wall both sides of NMOS grid structure, carry out the NMOS source-drain area inject, and the order that ion injects is: Ge, P, As, P.

Step 207: the silicon dioxide of removing silicon chip surface.

Step 208: the photoetching and the ion that on the Semiconductor substrate of the side wall both sides of PMOS grid structure, carry out the PMOS source-drain area inject.

Embodiment illustrated in fig. 2ly also can not comprise the technical characterictic relevant with PMOS.

Wherein, in the step 206, the optimum range of the various ions of injection and substrate angulation, energy, dosage is following:

Ge：

With the substrate angulation: 0～30 the degree, energy: 10～35 kilo electron volts (ev), dosage: 1E14～1E15 atomicity/centimetre ²

The P that injects for the first time:

With the substrate angulation: 0～30 the degree, energy: 10～35Kev, dosage: 1E14～3E15 atomicity/centimetre ²

As：

With the substrate angulation: 0～30 the degree, energy: 10～40Kev, dosage: 1E14～3E15 atomicity/centimetre ²

The P that injects for the second time:

With the substrate angulation: 0～30 the degree, energy: 10～40Kev, dosage: 1E14～3 draw 5 atomicities/centimetre ²

An important indicator weighing the NMOS performance is: ON state current, and under same off-state current, ON state current is big more, and then the performance of NMOS is good more.

Fig. 3 has provided same NMOS has been adopted existing ion injection order: the ion injection order that P, Ge, As, P and the employing embodiment of the invention provide: when Ge, P, As, P; ON state current (ldsat) and off-state current (loff) concern sketch map; The abscissa of Fig. 3 is the ON state current of NMOS, and ordinate is the off-state current of NMOS, and the unit of electric current is: microampere/micron (uA/um); The ion injection order that the corresponding embodiment of the invention of solid dot among the figure provides; The ion injection order that the corresponding prior art of hollow dots provides, as can beappreciated from fig. 3, for same NMOS; Under same off-state current, prior art is the highest to improve 4% to the ON state current that the method that adopts the embodiment of the invention to provide obtains than adopting.

The above is merely process of the present invention and method embodiment, in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being made, is not equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (1)

1. method for implanting is leaked in a N type metal oxide semiconductor NMOS source, and this method comprises:

Above the N trap of the Semiconductor substrate of silicon chip, form the grid structure of NMOS;

On the Semiconductor substrate of NMOS grid structure both sides, carrying out lightly doped drain LDD injects;

Form the side wall of the grid structure of NMOS;

The photoetching and the ion that on the Semiconductor substrate of the side wall both sides of NMOS grid structure, carry out the NMOS source-drain area inject, and the order that ion injects is: germanium Ge, phosphorus P, arsenic As, P;

Said Ge and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 1E15 atomicity/centimetre ²

The said P that injects for the first time and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre ²

Said As and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre ²

The said P that injects for the second time and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre ²

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