CN102005388A - N-type metal oxide semiconductor source drain implantation method - Google Patents
N-type metal oxide semiconductor source drain implantation method Download PDFInfo
- Publication number
- CN102005388A CN102005388A CN2009101950176A CN200910195017A CN102005388A CN 102005388 A CN102005388 A CN 102005388A CN 2009101950176 A CN2009101950176 A CN 2009101950176A CN 200910195017 A CN200910195017 A CN 200910195017A CN 102005388 A CN102005388 A CN 102005388A
- Authority
- CN
- China
- Prior art keywords
- nmos
- grid structure
- atomicity
- centimetre
- injects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 8
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 8
- 238000002513 implantation Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 15
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000011574 phosphorus Substances 0.000 claims abstract description 3
- 238000002347 injection Methods 0.000 abstract description 12
- 239000007924 injection Substances 0.000 abstract description 12
- 238000005468 ion implantation Methods 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 150000002500 ions Chemical class 0.000 description 20
- 235000012239 silicon dioxide Nutrition 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 11
- 238000005530 etching Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000012407 engineering method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an N-type metal oxide semiconductor source drain implantation method, which comprises the following steps of: forming a grid structure of an NMOS (N-type metal oxide semiconductor) above an N well of a semiconductor substrate of a silicon chip; performing LDD (lightly doped drain) injection on the semiconductor substrate on two sides of the NMOS grid structure; forming side walls of the NMOS grid structure; and performing photo-etching and ion implantation of an NMOS source drain area on the semiconductor substrate on two sides of the side walls of the NMOS grid structure, wherein the order of the ion implantation is germanium (Ge), phosphorus (P), arsenic (As) and P. The method improves the performance of the NMOS.
Description
Technical field
The present invention relates to semiconductor components and devices manufacturing technology field, be specifically related to N type metal oxide semiconductor source and leak method for implanting.
Background technology
Semiconductor device is made and is meant chemistry or the physical operations of carrying out a series of complexity on silicon chip.Manufacture craft with complementary metal oxide semiconductors (CMOS) (CMOS) is an example, as shown in Figure 1, mainly comprises:
Step 101: on the Semiconductor substrate of silicon chip, form N trap, P trap and shallow channel isolation area (STI).
In the existing CMOS manufacture craft, the first step is to adopt twin well process to define the active area of N type metal oxide semiconductor (NMOS) and P-type mos (PMOS), thereby obtains N trap and P trap.Then, by technologies such as photoetching and etchings, on Semiconductor substrate, form STI.
Step 102:, and utilize technologies such as photoetching and etching above the N trap, to form the grid structure of NMOS, the grid structure of formation PMOS above the P trap at silicon chip surface growth gate oxide and deposit polysilicon.
In this step, at first carry out the growth of gate oxide, promptly be about 20～50 dusts at silicon chip surface oxidation growth one layer thickness
Silicon dioxide (SiO
2); Then, by chemical vapor deposition method, at silicon chip surface deposit one deck polysilicon, thickness is about 500
Afterwards, by technologies such as photoetching and etchings, produce the grid structure of NMOS pipe and PMOS pipe.Grid structure of the present invention comprises the grid that is made of polysilicon and is positioned at the gate oxide of grid below.
Step 103: on the Semiconductor substrate of NMOS and PMOS grid structure both sides, carry out lightly doped drain (LDD) respectively and inject.
Under the promotion of demands such as semiconductor device miniatureization, densification, high speed and system integration, the width of grid structure constantly reduces, the channel length of its below also constantly reduces, thereby increased the possibility of electric charge break-through between leak in the source, make leakage current significantly increase, therefore, need to adopt some means to reduce the possibility that leakage current occurs, inject as LDD.
Before LDD injects, need at first utilize lithographic definition to go out and to carry out the zone that LDD injects; Then, utilize the dopant material of big quality such as arsenic or boron fluoride to carry out LDD and inject, thereby make the upper surface of silicon chip become amorphous state, big quality materials and surface amorphously help to keep shallow junction, shallow junction helps to reduce leakage current.
Step 104: at silicon chip surface deposit silicon dioxide successively and silicon nitride (Si
3N
4).
Step 105: utilize the silicon nitride of dry etch process etching silicon chip surface, form the side wall of the grid structure of NMOS and PMOS.
In etching process, need to keep the silicon dioxide of all around gate structure, so that form side wall, side wall can be used for preventing that the follow-up source of carrying out from leaking when injecting and too leak break-through near raceway groove so that generation source, produces leakage current thereby diffusion takes place the impurity that promptly injects.
Step 106: the photoetching and the ion that carry out the NMOS source-drain area on the Semiconductor substrate of the side wall both sides of NMOS grid structure inject.
At first utilize lithographic definition to go out and to carry out the NMOS source and drain areas that ion injects; Then, carry out n according to the zone that defines
+The source is leaked and is injected, and the side wall that forms in the step 105 can be used in the protection raceway groove.n
+The source leak to be injected junction depth that the back forms and is carried out LDD than step 103 to inject the junction depth that the back forms bigger.The ion that injects is generally: phosphorus (P), germanium (Ge), arsenic (As).
Step 107: the silicon dioxide of removing silicon chip surface.
Usually, adopt hydrofluoric acid etc. to remove silicon dioxide.
In actual applications, step 107 also can be carried out before step 106, promptly also can remove silicon dioxide in the silicon nitride of removing silicon chip surface.No matter when carry out, its purpose all is that for convenience follow-up ion that carries out injects, and prevents that the existence of silicon dioxide from causing the ion injection inhomogeneous.
Step 108: the photoetching and the ion that carry out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure inject.
Utilize lithographic definition to go out equally, earlier and will carry out the PMOS source and drain areas that ion injects; Then, carry out p according to the zone that defines
+The source is leaked and is injected, and the side wall that forms in the step 105 can be used in the protection raceway groove.p
+The source leak to be injected junction depth that the back forms and is carried out LDD than step 103 to inject the junction depth that the back forms bigger.
In order to improve the performance of NMOS, can adopt following method usually: one, reduce the thickness of gate oxide, its shortcoming is to cause the leakage current of gate oxide to increase; Two, the applied stress engineering method is eliminated the stress of silicon dioxide, and the shortcoming of this method is that the processing complexity is higher.
Through experiment showed, when NMOS being carried out source leakage injection, adopt the performance of the different resulting NMOS of ion injection order normally different.Usually adopt the ion injection order of P, Ge, As, P at present, so not only avoided above-mentioned two defectives, and obtained NMOS performance preferably.
Summary of the invention
The invention provides the NMOS source and leak method for implanting, with the performance of further raising NMOS.
Technical scheme of the present invention is achieved in that
Method for implanting is leaked in a kind of NMOS source, and this method comprises:
Above the N trap of the Semiconductor substrate of silicon chip, form the grid structure of NMOS;
Carrying out LDD on the Semiconductor substrate of NMOS grid structure both sides injects;
Form the side wall of the grid structure of NMOS;
The photoetching and the ion that carry out the NMOS source-drain area on the Semiconductor substrate of the side wall both sides of NMOS grid structure inject, and the order that ion injects is: Ge, P, As, P.
Described Ge and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 1E15 atomicity/centimetre
2
For the first time the described P that injects and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
Described As and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
For the second time the described P that injects and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
Described Ge and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 1E15 atomicity/centimetre
2
For the first time the described P that injects and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
Described As and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
For the second time the described P that injects and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
Compared with prior art, the present invention is when carrying out the leakage injection of NMOS source, and the ion injection of employing is in proper order: Ge, P, As, P experiment showed, that the present invention has improved the performance of NMOS.
Description of drawings
Fig. 1 is the manufacture method flow chart of conventional semiconductor device;
Fig. 2 leaks the method for implanting flow chart for the NMOS source that the embodiment of the invention provides;
When Fig. 3 leaks method for implanting for adopting source existing and that the embodiment of the invention provides, the ON state current of NMOS and off-state current concern schematic diagram.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Fig. 2 leaks the method for implanting flow chart for the NMOS source that the embodiment of the invention provides, and as shown in Figure 2, its concrete steps are as follows:
Step 201: on the Semiconductor substrate of silicon chip, form N trap, P trap and STI.
Step 202:, and utilize technologies such as photoetching and etching above the N trap, to form the grid structure of NMOS, the grid structure of formation PMOS above the P trap at silicon chip surface growth gate oxide and deposit polysilicon.
Step 203: on the Semiconductor substrate of NMOS and PMOS grid structure both sides, carry out LDD respectively and inject.
Step 204: deposit silicon dioxide and silicon nitride successively on the sidewall of silicon chip surface and NMOS and PMOS grid structure and surface.
Step 205: utilize the sidewall of dry etch process etching silicon chip surface and NMOS and PMOS grid structure and the silicon nitride on surface, remove the sidewall of silicon chip surface and NMOS and PMOS grid structure and the silicon nitride on surface, form the side wall of the grid structure of NMOS and PMOS.
In etching process, need to keep the silicon dioxide of all around gate structure, so that form side wall, side wall can be used for preventing that the follow-up source of carrying out from leaking when injecting and too leak break-through near raceway groove so that generation source, produces leakage current thereby diffusion takes place the impurity that promptly injects.
Step 206: the photoetching and the ion that carry out the NMOS source-drain area on the Semiconductor substrate of the side wall both sides of NMOS grid structure inject, and the order that ion injects is: Ge, P, As, P.
Step 207: the silicon dioxide of removing silicon chip surface.
Step 208: the photoetching and the ion that carry out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure inject.
Embodiment illustrated in fig. 2ly also can not comprise the technical characterictic relevant with PMOS.
Wherein, in the step 206, the optimum range of the various ions of injection and substrate angulation, energy, dosage is as follows:
Ge：
With the substrate angulation: 0～30 the degree, energy: 10～35 kilo electron volts (ev), dosage: 1E14～1E15 atomicity/centimetre
2
The P that inject the first time:
With the substrate angulation: 0～30 the degree, energy: 10～35Kev, dosage: 1E14～3E15 atomicity/centimetre
2
As：
With the substrate angulation: 0～30 the degree, energy: 10～40Kev, dosage: 1E14～3E15 atomicity/centimetre
2
The P that inject the second time:
With the substrate angulation: 0～30 the degree, energy: 10～40Kev, dosage: 1E14～3E15 atomicity/centimetre
2
An important indicator weighing the NMOS performance is: ON state current, and under same off-state current, ON state current is big more, and then the performance of NMOS is good more.
Fig. 3 has provided same NMOS has been adopted existing ion injection order: P, Ge, As, P and the ion injection order that adopts the embodiment of the invention to provide: Ge, P, As, during P, ON state current (ldsat) and off-state current (loff) concern schematic diagram, the abscissa of Fig. 3 is the ON state current of NMOS, ordinate is the off-state current of NMOS, the unit of electric current is: microampere/micron (uA/um), the ion injection order that the corresponding embodiment of the invention of solid dot among the figure provides, the ion injection order that the corresponding prior art of hollow dots provides, as can be seen from Figure 3, for same NMOS, under same off-state current, prior art is the highest to improve 4% to the ON state current that the method that adopts the embodiment of the invention to provide obtains than adopting.
The above only is process of the present invention and method embodiment, in order to restriction the present invention, all any modifications of being made within the spirit and principles in the present invention, is not equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. method for implanting is leaked in a N type metal oxide semiconductor NMOS source, and this method comprises:
Above the N trap of the Semiconductor substrate of silicon chip, form the grid structure of NMOS;
Carrying out lightly doped drain LDD on the Semiconductor substrate of NMOS grid structure both sides injects;
Form the side wall of the grid structure of NMOS;
The photoetching and the ion that carry out the NMOS source-drain area on the Semiconductor substrate of the side wall both sides of NMOS grid structure inject, and the order that ion injects is: germanium Ge, phosphorus P, arsenic As, P.
2. the method for claim 1 is characterized in that,
Described Ge and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 1E15 atomicity/centimetre
2
3. method as claimed in claim 1 or 2 is characterized in that,
For the first time the described P that injects and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
4. method as claimed in claim 1 or 2 is characterized in that,
Described As and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
5. method as claimed in claim 1 or 2 is characterized in that,
For the second time the described P that injects and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
6. the method for claim 1 is characterized in that,
Described Ge and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 1E15 atomicity/centimetre
2
For the first time the described P that injects and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 35 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
Described As and substrate angulation scope be 0 to 30 the degree, energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
For the second time the described P that injects and substrate angulation scope are 0 to 30 to spend, and energy range is 10 to 40 kilo electron volts, dosage range be 1E14 to 3E15 atomicity/centimetre
2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101950176A CN102005388B (en) | 2009-09-02 | 2009-09-02 | N-type metal oxide semiconductor source drain implantation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101950176A CN102005388B (en) | 2009-09-02 | 2009-09-02 | N-type metal oxide semiconductor source drain implantation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102005388A true CN102005388A (en) | 2011-04-06 |
| CN102005388B CN102005388B (en) | 2012-02-08 |
Family
ID=43812637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101950176A Expired - Fee Related CN102005388B (en) | 2009-09-02 | 2009-09-02 | N-type metal oxide semiconductor source drain implantation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102005388B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035530A (en) * | 2012-06-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method of N-channel metal oxide semiconductor (NMOS) switch device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100364122B1 (en) * | 2001-04-24 | 2002-12-11 | Hynix Semiconductor Inc | Method for fabricating semiconductor device |
| KR20090073410A (en) * | 2007-12-31 | 2009-07-03 | 주식회사 동부하이텍 | Transistors and manufacturing methods thereof |
| CN101431057B (en) * | 2008-12-11 | 2010-11-17 | 电子科技大学 | A High Power BCD Process for Etching Monolayer Polysilicon in Two Times |
-
2009
- 2009-09-02 CN CN2009101950176A patent/CN102005388B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035530A (en) * | 2012-06-08 | 2013-04-10 | 上海华虹Nec电子有限公司 | Manufacture method of N-channel metal oxide semiconductor (NMOS) switch device |
| CN103035530B (en) * | 2012-06-08 | 2015-12-02 | 上海华虹宏力半导体制造有限公司 | The manufacture method of nmos switch device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102005388B (en) | 2012-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9455204B1 (en) | 10 nm alternative N/P doped fin for SSRW scheme | |
| CN102800595B (en) | NMOS (N-Channel Metal Oxide Semiconductor) transistor forming method and corresponding COMOS structure forming method | |
| CN102074476B (en) | Forming method of N-channel metal oxide semiconductor (NMOS) transistor | |
| CN106960795A (en) | The forming method of PMOS transistor | |
| CN102800594A (en) | Manufacturing method of PMOS (p-channel metal oxide semiconductor) tube | |
| CN101393893B (en) | CMOS device having different width of lateral wall and manufacturing method thereof | |
| CN102005388B (en) | N-type metal oxide semiconductor source drain implantation method | |
| CN102931233A (en) | N-channel metal oxide semiconductor (NMOS) transistor and forming method thereof | |
| CN103545257A (en) | How to make a CMOS transistor | |
| CN102915968A (en) | Manufacturing method of CMOS (Complementary Metal oxide Semiconductor) transistor | |
| CN101996949B (en) | Method for manufacturing semiconductor device | |
| CN102637600A (en) | Preparation method of MOS (metal oxide semiconductor) device | |
| CN103377940B (en) | A kind of P-type transmission gridistor for SRAM and preparation method thereof | |
| CN103377941A (en) | PMOS transistor and forming method | |
| US20080160710A1 (en) | Method of fabricating mosfet device | |
| CN102709162A (en) | Method of forming silicon germanium channel and PMOS (P-channel metal oxide semiconductor) transistor | |
| CN103426766B (en) | Pmos transistor and forming method thereof | |
| CN102082127A (en) | Method for manufacturing semiconductor device | |
| CN101393892B (en) | Method for manufacturing semiconductor device | |
| KR20030034956A (en) | method for manufacturing of semiconductor device | |
| US9064888B2 (en) | Forming tunneling field-effect transistor with stacking fault and resulting device | |
| CN102054698B (en) | Method for improving threshold voltage of semiconductor device | |
| US20250118560A1 (en) | Method for fabricating semiconductor device | |
| CN101459081A (en) | MOS transistor forming method | |
| CN102044492A (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120208 Termination date: 20190902 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |