CN102427062A - Self-aligned channel doping suppression CMOS short channel effect and preparation method thereof - Google Patents
Self-aligned channel doping suppression CMOS short channel effect and preparation method thereof Download PDFInfo
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- CN102427062A CN102427062A CN201110206463XA CN201110206463A CN102427062A CN 102427062 A CN102427062 A CN 102427062A CN 201110206463X A CN201110206463X A CN 201110206463XA CN 201110206463 A CN201110206463 A CN 201110206463A CN 102427062 A CN102427062 A CN 102427062A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
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Abstract
The self-aligned channel doping inhibits the CMOS short channel effect and the preparation method thereof, and solves the problems that in the prior art, 1, source and drain doping is compensated, so that the source and drain parasitic resistance value is increased; 2. profile of PN junctions of a source lining and a drain lining can be influenced, and reverse bias leakage current of the source lining and the drain lining is increased; 3. the junction depth Xj of the PN junction of the source lining and the drain lining can be increased, so that the SCE can be inhibited in a reaction manner.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, relate in particular to a kind of autoregistration channel doping and suppress CMOS short-channel effect and preparation method thereof.
Background technology
Short-channel effect (Short Channel Effect) is cmos device channel length common phenomena when dwindling; It can cause threshold voltage shift; Break-through, DIBL (Drain induction barrier lower are leaked in the source; Drain-induced barrier reduces) characteristics such as (higher leakage are depressed), can cause the cmos device performance failure when serious.SCE can explain with the charge-sharing model that Yau proposes:
Promptly when raceway groove shortens, the ratio that source lining, leakage lining PN junction are shared raceway groove depletion region electric charge and raceway groove total electrical charge will increase, thereby cause the grid-control ability drop.
According to the threshold voltage shift formula that charge-sharing model is derived, the conventional method that suppresses SCE is following three kinds: improve and reduce tox, channel doping concentration Nb reduces the source lining, leaks the junction depth Xj that serves as a contrast PN junction.
Wherein, Fig. 1 is the sketch map of Xdm in the background technology of the present invention, sees also Fig. 1; To the adjusting of Xdm, i.e. the adjusting of channel doping concentration Nb, conventional method is below raceway groove, to carry out buried regions heavy doping; It generally is to carry out buried regions heavy doping to whole active area, and promptly source-drain area also receives this layer doping, and it is opposite that doping type is leaked in this impurity and source; Possible this can bring following side effect (side effects): 1, can leak doping to the source and compensate, the source of causing is omitted living resistance value and is increased; 2, can influence the side profile (profile) of source lining, leakage lining PN junction, cause their anti-leakage current partially to increase; 3, may serve as a contrast, leak the junction depth Xj of lining PN junction in the increase source, thereby have the opposite effect suppressing SCE.
Summary of the invention
The invention discloses a kind of autoregistration channel doping and suppress CMOS short-channel effect and preparation method thereof, in order to solve in the prior art 1, can leak to mix to the source and compensate, the source of causing be omitted living resistance value and is increased; 2, can influence the profile of source lining, leakage lining PN junction, cause their anti-leakage current partially to increase; 3, may serve as a contrast, leak the junction depth Xj that serves as a contrast PN junction in the increase source, thereby to suppressing the reactive problem of SCE.
Above-mentioned purpose of the present invention realizes through following technical scheme:
A kind of autoregistration channel doping suppresses CMOS short-channel effect and preparation method thereof; In a silicon substrate, be formed with the back grid high-k dual-MOS structure of processing through the back grid technology that comprises a first transistor and a transistor seconds; Wherein, may further comprise the steps:
Step a: the sample grid in the transistor seconds grid groove of the first transistor grid groove of the first transistor device and transistor seconds device are removed, in the process of the sample grid in removing the first transistor grid groove and transistor seconds grid groove thin oxide layer is kept;
Step b: spin coating photoresist on the first transistor and transistor seconds, the first transistor grid groove and transistor seconds grid groove are filled;
Step c: carry out photoetching, remove the photoresist that covers on the first transistor device, and remove the photoresist in the first transistor grid groove;
Steps d: in the first transistor grid groove, inject acceptor impurity, make and form the first buried regions heavy doping under the first transistor raceway groove;
Step e: remove on the transistor seconds and remaining photoresist in the transistor seconds grid groove;
Step f: spin coating photoresist once more on the first transistor and transistor seconds, the first transistor grid groove and transistor seconds grid groove are filled;
Step g: carry out photoetching once more, remove the photoresist that covers on the transistor seconds device, and remove the photoresist in the transistor seconds grid groove;
Step h: in transistor seconds grid groove, inject donor impurity, make and form the second buried regions heavy doping under the transistor seconds raceway groove;
Step I: remove on the first transistor and remaining photoresist in the first transistor grid groove;
Step j: anneal, inject ion to activate;
Step k: carry out conventional back grid high-k device preparation technology.
Aforesaid autoregistration channel doping suppresses CMOS short-channel effect and preparation method thereof, and wherein, silicon substrate is set to P type silicon substrate.
Aforesaid autoregistration channel doping suppresses CMOS short-channel effect and preparation method thereof, and wherein, the first transistor is set to the NMOS pipe, and transistor seconds is set to the PMOS pipe.
Aforesaid autoregistration channel doping suppresses CMOS short-channel effect and preparation method thereof, wherein, in step a, carries out wet etching, and the sample grid in the first transistor grid groove and the transistor seconds grid groove are removed.
Aforesaid autoregistration channel doping suppresses CMOS short-channel effect and preparation method thereof, wherein, in steps d, injects B, BF2, BE, In ion as acceptor impurity.
Aforesaid autoregistration channel doping suppresses CMOS short-channel effect and preparation method thereof, wherein, in step h, injects P, As ion as donor impurity.
Aforesaid autoregistration channel doping suppresses CMOS short-channel effect and preparation method thereof, wherein, carries out rapid thermal annealing, peak value annealing or spike among the step j and injects ion to activate.
In sum, owing to adopted technique scheme, autoregistration channel doping of the present invention suppresses CMOS short-channel effect and preparation method thereof and has solved in the prior art 1, can leak to mix to the source and compensate, and the source of causing is omitted living resistance value and increased; 2, can influence the profile of source lining, leakage lining PN junction, cause their anti-leakage current partially to increase; 3, may serve as a contrast, leak the junction depth Xj that serves as a contrast PN junction in the increase source, thereby to suppressing the reactive problem of SCE.The present invention has realized cmos device channel region autoregistration doping, form raceway groove lower heavy doping buried regions, and source and drain areas is unaffected, thereby effectively suppresses short-channel effect, has promoted the performance of device.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is X in the background technology of the present invention
DmSketch map;
Fig. 2 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps a of CMOS short-channel effect and preparation method thereof;
Fig. 3 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps c of CMOS short-channel effect and preparation method thereof;
Fig. 4 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps g of CMOS short-channel effect and preparation method thereof;
Fig. 5 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps j of CMOS short-channel effect and preparation method thereof;
Fig. 6 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps k of CMOS short-channel effect and preparation method thereof.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
A kind of autoregistration channel doping suppresses CMOS short-channel effect and preparation method thereof, wherein,
Formation one comprises the back grid high-k CMOS structure of a first transistor 110 and a transistor seconds 120 on a silicon substrate; Wherein, substrate is set to P type silicon substrate.
Further, the first transistor 110 is set to the NMOS pipe, transistor seconds 120 is set to the PMOS pipe.
Fig. 2 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps a of CMOS short-channel effect and preparation method thereof; See also Fig. 2, step a: the first transistor grid groove 1130 of the first transistor 110 devices and the transistor seconds grid groove 1230 interior sample grid of transistor seconds 120 devices are removed;
Wherein, through carrying out wet etching, the first transistor grid groove 1130 and the sample grid in the transistor seconds grid groove 1230 are removed.
Further; In the process of the sample grid in step a removes the first transistor grid groove 1130 and transistor seconds grid groove 1230 thin oxide layer is kept; That is to say, the thin oxide layer 1131 of the first transistor grid groove 1130 bottoms and the thin oxide layer 1231 of transistor seconds grid groove 1230 bottoms are kept.
Step b: spin coating photoresist on the first transistor 110 and transistor seconds 120, the first transistor grid groove 1130 and transistor seconds grid groove 1230 are filled;
Fig. 3 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps c of CMOS short-channel effect and preparation method thereof; See also Fig. 3; Step c: carry out photoetching, remove the photoresist that covers on the first transistor 110 devices, and remove the photoresist in the first transistor grid groove 1130;
Steps d: in the first transistor grid groove 1130, inject acceptor impurity; Make and form the first buried regions heavy doping 111 under the first transistor 110 raceway grooves; 111 of the first buried regions heavy doping are formed under the first transistor 110 raceway grooves; Can't exert an influence to source region and drain region, thereby effectively suppress short-channel effect;
Wherein, inject B, BF2, BE, In ion, cause to form the first buried regions heavy doping 111 under the NMOS raceway groove, and source and drain areas is unaffected as acceptor impurity.
Step e: remove photoresist, the remaining photoresist that covers in transistor seconds 120 and the transistor seconds grid groove 1230 is removed;
Step f: spin coating photoresist once more on the first transistor 110 and transistor seconds 120, the first transistor grid groove 1130 and transistor seconds grid groove 1230 are filled;
Fig. 4 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps g of CMOS short-channel effect and preparation method thereof; See also Fig. 4; Step g: carry out photoetching once more; Remove the photoresist that covers on transistor seconds 120 devices, and remove the photoresist in the transistor seconds grid groove 1230;
Step h: in transistor seconds grid groove 1230, inject donor impurity; Make and form the second buried regions heavy doping 121 under transistor seconds 120 raceway grooves; 121 of the second buried regions heavy doping are formed under transistor seconds 120 raceway grooves; Can't exert an influence to source region and drain region, thereby effectively suppress short-channel effect;
In step h, inject P, As ion as donor impurity, cause to form the second buried regions heavy doping 121 under the PMOS raceway groove, and source and drain areas is unaffected
Step I: remove photoresist once more, the remaining photoresist that covers in the first transistor 110 and the first transistor grid groove 1130 is removed;
Fig. 5 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps j of CMOS short-channel effect and preparation method thereof; See also Fig. 5; Step j: anneal, inject the first buried regions heavy doping, 111 ions of the first transistor grid groove 1130 belows and the second buried regions heavy doping 121 of the second crystal grid groove, 1230 belows with activation;
Can inject ion to activate through carrying out rapid thermal annealing, peak value annealing or spike among the step j.
Fig. 6 is the structural representation after autoregistration channel doping of the present invention suppresses the completing steps k of CMOS short-channel effect and preparation method thereof; See also Fig. 6; Step k: carry out conventional back grid high-k device preparation technology, its subsequent technique is identical with prior art, so will not give unnecessary details.
In sum, autoregistration channel doping of the present invention suppresses CMOS short-channel effect and preparation method thereof and has solved in the prior art 1, can leak to mix to the source and compensate, and the source of causing is omitted living resistance value and increased; 2, can influence the profile of source lining, leakage lining PN junction, cause their anti-leakage current partially to increase; 3, may serve as a contrast, leak the junction depth Xj that serves as a contrast PN junction in the increase source; Thereby to suppressing the reactive problem of SCE; The present invention has realized cmos device channel region autoregistration doping, form raceway groove lower heavy doping buried regions, and source and drain areas is unaffected; Thereby effectively suppress short-channel effect, promoted the performance of device.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and the foregoing description can realize said variant, do not repeat them here.Such variant does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (7)
1. an autoregistration channel doping suppresses CMOS short-channel effect and preparation method thereof; In a silicon substrate, be formed with the back grid high-k dual-MOS structure of processing through the back grid technology that comprises a first transistor and a transistor seconds; It is characterized in that, may further comprise the steps:
Step a: the sample grid in the transistor seconds grid groove of the first transistor grid groove of the first transistor device and transistor seconds device are removed, in the process of the sample grid in removing the first transistor grid groove and transistor seconds grid groove thin oxide layer is kept;
Step b: spin coating photoresist on the first transistor and transistor seconds, the first transistor grid groove and transistor seconds grid groove are filled;
Step c: carry out photoetching, remove the photoresist that covers on the first transistor device, and remove the photoresist in the first transistor grid groove;
Steps d: in the first transistor grid groove, inject acceptor impurity, make and form the first buried regions heavy doping under the first transistor raceway groove;
Step e: remove on the transistor seconds and remaining photoresist in the transistor seconds grid groove;
Step f: spin coating photoresist once more on the first transistor and transistor seconds, the first transistor grid groove and transistor seconds grid groove are filled;
Step g: carry out photoetching once more, remove the photoresist that covers on the transistor seconds device, and remove the photoresist in the transistor seconds grid groove;
Step h: in transistor seconds grid groove, inject donor impurity, make and form the second buried regions heavy doping under the transistor seconds raceway groove;
Step I: remove on the first transistor and remaining photoresist in the first transistor grid groove;
Step j: anneal, inject ion to activate;
Step k: carry out conventional back grid high-k device preparation technology.
2. autoregistration channel doping according to claim 1 suppresses CMOS short-channel effect and preparation method thereof, it is characterized in that silicon substrate is set to P type silicon substrate.
3. autoregistration channel doping according to claim 1 suppresses CMOS short-channel effect and preparation method thereof, it is characterized in that, the first transistor is set to the NMOS pipe, and transistor seconds is set to the PMOS pipe.
4. autoregistration channel doping according to claim 1 suppresses CMOS short-channel effect and preparation method thereof, it is characterized in that, in step a, carries out wet etching, and the sample grid in the first transistor grid groove and the transistor seconds grid groove are removed.
5. autoregistration channel doping according to claim 1 suppresses CMOS short-channel effect and preparation method thereof, it is characterized in that, in steps d, injects B, BF2, BE, In ion as acceptor impurity.
6. autoregistration channel doping according to claim 1 suppresses CMOS short-channel effect and preparation method thereof, it is characterized in that, in step h, injects P, As ion as donor impurity.
7. autoregistration channel doping according to claim 1 suppresses CMOS short-channel effect and preparation method thereof, it is characterized in that, in step j, carries out rapid thermal annealing, peak value annealing or spike and injects ion to activate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110206463XA CN102427062A (en) | 2011-07-22 | 2011-07-22 | Self-aligned channel doping suppression CMOS short channel effect and preparation method thereof |
| US13/339,429 US20130020652A1 (en) | 2011-07-22 | 2011-12-29 | Method for suppressing short channel effect of cmos device |
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| CN201110206463XA CN102427062A (en) | 2011-07-22 | 2011-07-22 | Self-aligned channel doping suppression CMOS short channel effect and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867755A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Method for forming NMOS (N-channel metal oxide semiconductor) device with low GIDL (gate induced drain leakage) current |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5994179A (en) * | 1996-06-03 | 1999-11-30 | Nec Corporation | Method of fabricating a MOSFET featuring an effective suppression of reverse short-channel effect |
| US6365450B1 (en) * | 2001-03-15 | 2002-04-02 | Advanced Micro Devices, Inc. | Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate |
| US20100102399A1 (en) * | 2008-10-29 | 2010-04-29 | Sangjin Hyun | Methods of Forming Field Effect Transistors and Devices Formed Thereby |
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- 2011-07-22 CN CN201110206463XA patent/CN102427062A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5994179A (en) * | 1996-06-03 | 1999-11-30 | Nec Corporation | Method of fabricating a MOSFET featuring an effective suppression of reverse short-channel effect |
| US6365450B1 (en) * | 2001-03-15 | 2002-04-02 | Advanced Micro Devices, Inc. | Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate |
| US20100102399A1 (en) * | 2008-10-29 | 2010-04-29 | Sangjin Hyun | Methods of Forming Field Effect Transistors and Devices Formed Thereby |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867755A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Method for forming NMOS (N-channel metal oxide semiconductor) device with low GIDL (gate induced drain leakage) current |
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Application publication date: 20120425 |