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CN102201351A - 半导体器件和形成用于无铅凸块连接的双ubm结构的方法 - Google Patents

半导体器件和形成用于无铅凸块连接的双ubm结构的方法 Download PDF

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Publication number
CN102201351A
CN102201351A CN2011100735907A CN201110073590A CN102201351A CN 102201351 A CN102201351 A CN 102201351A CN 2011100735907 A CN2011100735907 A CN 2011100735907A CN 201110073590 A CN201110073590 A CN 201110073590A CN 102201351 A CN102201351 A CN 102201351A
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China
Prior art keywords
ubm
insulating barrier
conductive layer
contact pad
projection
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CN2011100735907A
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CN102201351B (zh
Inventor
林立人
S·A·墨菲
孙伟
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Stats Chippac Shanghai Co Ltd
Stats Chippac Pte Ltd
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Stats Chippac Shanghai Co Ltd
Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件和形成用于无铅凸块连接的双UBM结构的方法。一种半导体器件具有包括接触焊盘的衬底。第一绝缘层形成在衬底和接触焊盘上。第一凸块下金属化（UBM）形成在第一绝缘层上并且被电连接到接触焊盘。第二绝缘层形成在第一UBM上。第二UBM在第二绝缘层被固化之后形成在第二绝缘层上。第二UBM被电连接到第一UBM。第二绝缘层在第一和第二UBM的多个部分之间并且分隔第一和第二UBM的多个部分。接触焊盘上的具有开口的光致抗蚀剂层被形成在第二UBM上。导电凸块材料被沉积在光致抗蚀剂层中的开口内。光致抗蚀剂层被除去，并且导电凸块材料被回流以形成球形凸块。

Description

半导体器件和形成用于无铅凸块连接的双UBM结构的方法
要求国内优先权
本非临时申请要求2010年3月25日提交的序号为No. 61/317,664的美国临时申请的优先权的权益，并且根据35 U.S.C. § 120要求在先原申请的优先权。
技术领域
本发明总体上涉及半导体器件，更具体地，涉及半导体器件和形成用于无铅凸块连接的双凸块下金属化（UBM）结构的方法。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个管芯并且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占用空间（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的管芯的前端工艺可以实现更小的管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占用空间的半导体器件封装。
互连半导体管芯和印刷电路板或其它器件的一种常用技术涉及使用焊料凸块。图1示出常规UBM上聚酰亚胺（POU）焊料凸块结构10。导电层14形成在半导体晶片12的有源表面上，并且充当接触焊盘。针对初始质量控制（IQC）来检查晶片12。绝缘或钝化层16形成在半导体晶片12和导电层14上。绝缘层16的一部分通过刻蚀工艺被除去以暴露导电层14的一部分。部分形成的POU结构10经历第一次洗涤器清洗。导电层或溅射的UBM 18形成在绝缘层16和导电层14上。镍（Ni）UBM或导电层20形成在导电层18上并且被共形地施加到导电层18以充当用于稍后形成的凸块的凸块焊盘。部分形成的POU结构10经历第二次洗涤器清洗。聚酰亚胺层充当绝缘或钝化层22，其形成在导电层18和Ni UBM 20上。聚酰亚胺在干膜抗蚀剂（DFR）层压之前被涂覆、对准、显影、固化、清除浮渣、酸洗、以及烘烤。绝缘层22中的开口形成在Ni UBM 20上。DFR被层压在绝缘层22上并且然后经历边缘漂洗、对准、聚乙烯对苯二酸酯（polyethylene terepthalate，PET）去除、显影、第一次清除浮渣、硬烘（hard bake）、以及第二次清除浮渣。焊料材料被电镀在Ni UBM 20上以及在DFR层中的开口内。剥去DFR，施加等离子体灰，刻蚀Ni UBM 20，并且部分完成的POU结构10经历第三次洗涤器清洗。焊剂涂层被施加到电镀的焊料材料，并且焊料材料被回流以形成球形球或凸块24，球形球或凸块24形成在Ni UBM 20上并且电连接到Ni UBM 20。该器件经历焊剂清洗、凸块测量、以及最后目视检查（FVI），产生POU结构10。常规POU结构，例如POU结构10，包括这样的风险：锡（Sn）从凸块24沿Ni UBM的侧壁行进与UBM 铜（Cu）起反应而形成金属间化合物（IMC）。
图2示出常规聚酰亚胺和无铅凸块结构28。导电层32形成在半导体晶片30的有源表面上并且充当接触焊盘。针对IQC来检查晶片30。绝缘或钝化层34形成在半导体晶片30上并且接触导电层32的侧壁。部分形成的凸块结构28经历洗涤器清洗并且被烘烤。聚酰亚胺层充当绝缘或钝化层36，并且形成在导电层32和绝缘层34上。聚酰亚胺被涂覆、对准、显影、固化、清除浮渣以及酸洗，使得导电层32的一部分被暴露。导电层38形成在导电层32的一部分和绝缘层36的一部分上并且被共形地施加到那里。在一个实施例中，导电层38被溅射以充当用于稍后形成的凸块的UBM并且包括一层或多层的钛（Ti）、Cu和Ni。然后器件经历洗涤器清洗，并且DFR层被层压在绝缘层36和导电层38上。DFR层经历边缘束漂洗、对准、PET去除、显影、第一次清除浮渣、硬烘、以及第二次清除浮渣。焊料材料被电镀在导电层38上以及在DFR层中的开口内。DFR被剥去，导电层38被刻蚀，并且器件经历第三次洗涤器清洗、第一次氮气（N2）处理、第二次刻蚀、第四次洗涤器清洗、硬烘、以及氧气（O2）等离子体处理。焊剂涂层被施加到电镀的焊料材料，并且焊料材料被回流以形成球形球或凸块40，球形球或凸块40形成在导电层38上并且电连接到导电层38。器件然后经历焊剂清洗、第二次N2处理、凸块测量、第五次洗涤器清洗、以及FVI，产生聚酰亚胺和无铅凸块结构28。
对于利用无铅焊料的倒装芯片结合（例如在图1和2中介绍的那些）来说更加关注焊接接缝的可靠性。无铅焊料包括具有Cu和银（Ag）的锡基合金，其具有比常规共晶SnPb焊料更高的熔点。更高的温度和更高的Sn浓度导致SnPb焊料和UBM之间更剧烈的反应，所述剧烈反应可能导致过多IMC形成，所述过多IMC形成可能会引起UBM上的去湿并且导致不牢固的焊接接缝。
发明内容
存在改善无铅凸块连接的焊接接缝可靠性的需要。因此，在一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供具有接触焊盘的衬底，在衬底和接触焊盘上形成第一绝缘层，在第一绝缘层上形成第一UBM并且电连接到接触焊盘，在第一UBM上形成第二绝缘层，以及在第二绝缘层被固化之后在第二绝缘层上形成第二UBM。第二UBM电连接到第一UBM使得第二绝缘层位于第一和第二UBM的多个部分之间并且分隔第一和第二UBM的多个部分。所述方法进一步包括以下步骤：在第二UBM上形成光致抗蚀剂层并且除去光致抗蚀剂层的一部分以在接触焊盘上的光致抗蚀剂层中形成开口，在光致抗蚀剂层中的开口内沉积导电凸块材料，除去光致抗蚀剂层，除去第二UBM的外围部分使得导电凸块材料悬于第二UBM之上，除去第一UBM的外围部分使得第二绝缘层悬于第一UBM之上，以及回流导电凸块材料以形成球形凸块。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供具有接触焊盘的衬底，在衬底上形成第一UBM并且电连接到接触焊盘，在第一UBM上形成绝缘层，在绝缘层被固化后在绝缘层上形成第二UBM，以及在第二UBM上形成凸块。第二UBM电连接到第一UBM使得第二绝缘层分隔第一和第二UBM的多个部分。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供具有接触焊盘的衬底，在衬底上形成第一UBM并且电连接到接触焊盘，在第一UBM上形成绝缘层，在绝缘层被固化之后在绝缘层上形成第二UBM，以及在第二UBM上形成凸块。
在另一个实施例中，本发明是一种半导体器件，该半导体器件包括具有接触焊盘的衬底。具有比接触焊盘的面积更大的面积的第一UBM形成在衬底上并且被电连接到接触焊盘。绝缘层形成在第一UBM上。第二UBM形成在绝缘层上并且被电连接到第一UBM使得绝缘层在第一和第二UBM的多个部分之间。凸块形成在第二UBM上。
附图说明
图1示出常规POU结构；
图2示出常规聚酰亚胺与无铅焊料结构；
图3示出印刷电路板（PCB），其中不同类型的封装被安装到它的表面；
图4a-4c示出安装到所述PCB的典型半导体封装的更多细节；
图5a-5l示出双UBM结构；以及
图6示出双UBM结构的替换实施例。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electroless plating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的多个部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。在一个实施例中，利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的多个部分。在另一个实施例中，利用溶剂将未经受光的光致抗蚀剂图案部分（负性光致抗蚀剂）除去，暴露将被图案化的下层的多个部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化管芯，沿被叫做划片街区（saw street）或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图3示出具有芯片载体衬底或PCB 52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图3中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数码摄像机（DVC）或其它电子通信设备的一部分。可替换地，电子器件50可以是图形卡、网络接口卡、或能被插入计算机中的其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。对于这些将被市场接受的产品来说，小型化和重量减小是必要的。半导体器件之间的距离必须减小以获得更高的密度。
在图3中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB 52的表面上或多个层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括结合线封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（land grid array，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quad flat non-leaded package，QFN）70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图4a-4c示出示范性半导体封装。图4a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是一层或多层的导电材料，例如铝（AL）、Cu、Sn、Ni、金（Au）、或Ag，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和结合线82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染管芯74或结合线82来进行环境保护。
图4b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。结合线94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和结合线94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积工艺形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图4c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被以机械和电的方式连接到载体106。
BGA 60 利用凸块112使用BGA型第二级封装以机械和电的方式连接到PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
相对于图3和4a-4c，图5a-5l示出形成包括用于无铅凸块连接的双UBM结构的半导体器件的过程。图5a示出具有基底衬底材料122的半导体晶片120，所述基底衬底材料例如是硅、锗、砷化镓、磷化铟或碳化硅，用于结构支撑。多个半导体管芯或部件124形成在晶片120上，如上所述那样被划片街区126分开。
图5b示出半导体晶片120的一部分的截面图。每个半导体管芯124具有后表面128和有源表面130，该有源表面130包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面130内的其它电路元件以实现模拟电路或数字电路（例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路）。半导体管芯124也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。半导体管芯124也可以是倒装芯片类型的半导体管芯。
导电层132形成在有源表面130上并且在有源表面130上延伸，使得导电层132的顶表面产生不平坦的表面，并且相对于有源表面130具有非平面表面形貌。利用PVD、CVD、电解电镀、无电极电镀工艺或其它适当的金属沉积工艺形成导电层132。导电层132可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag或其它适当的导电材料。导电层132用作电连接到有源表面130上的电路的接触焊盘。
图5c示出半导体晶片120的一部分的放大截面图，集中于导电层132和直接包围接触焊盘的区域。针对IQC来检查晶片120。然后，通过跨越有源表面130向上延伸到导电层132的侧壁并且跨越接触焊盘的顶表面延伸，绝缘或钝化层134被共形地施加到晶片120和导电层132并遵循晶片120和导电层132的轮廓。绝缘层134具有顶表面138，所述顶表面138在晶片120上高度发生变化。形成在晶片120上和导电层132的占用空间以外的第一部分顶表面138具有高度H1。形成在晶片120上和导电层132上的第二部分顶表面138具有高度H2，其中H2大于H1。绝缘层134可以是一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、锆石（ZrO2）、氧化铝（Al2O3）、聚酰亚胺、苯并环丁烯（BCB）、聚苯并恶唑（polybenzoxazole，PBO）、或具有合适电绝缘特性的其它材料。利用PVD、CVD、印刷、旋涂、带有固化的烧结（sintering with curing）、或热氧化来图案化或毯式沉积绝缘层134。通过刻蚀工艺除去绝缘层134的一部分以在绝缘层134中形成开口136，所述开口136暴露导电层132的一部分。开口136从绝缘层134的顶表面138延伸到绝缘层134的底表面139。导电层132的另外的部分仍旧被绝缘层134覆盖。部分完成的双UBM结构然后经历第一次洗涤器清洗。
在图5d中，通过使用图案化和金属沉积工艺，例如印刷、PVD、CVD、溅射、电解电镀和无电极电镀，导电层140被形成在绝缘层134和导电层132上并且被共形地施加到绝缘层134和导电层132。在一个实施例中，导电层140是通过溅射形成的Ti、钛钨（TiW）、或铬（Cr）。可替换地，导电层140可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适导电材料。导电层140跨越顶表面138、沿开口136内的绝缘层134的侧壁、和跨越开口136内的导电层132的顶表面遵循绝缘层134的轮廓。导电层140包括在开口136内并且在导电层132上的区域142。区域142基本上是平的，并且比导电层132的面积小。导电层140用作稍后形成的凸块的第一UBM层。部分完成的双UBM结构然后经历第二次洗涤器清洗。
在图5e中，利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，绝缘或钝化层144被沉积或涂覆在导电层140上并且被共形地施加到导电层140。在一个实施例中，绝缘层144包括聚酰亚胺、PBO、或BCB。可替换地，绝缘层144包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。绝缘层144的底表面146遵循导电层140的轮廓。绝缘层144的顶表面148是平坦的并且基本上平行于有源表面130。因此，在底表面146和顶表面148之间测量的绝缘层144的厚度跨越晶片120而变化。绝缘层144用作用于稍后形成的第二UBM层的基底。
图5f示出绝缘层144被对准和显影，并且绝缘层的多个部分被除去以在绝缘层中制造开口152和154。开口152形成在导电层140的区域142上。开口152从绝缘层144的顶表面148穿过绝缘层延伸到绝缘层的底表面146。开口152的占用空间具有的面积比导电层140的区域142小。开口152通过图案化和刻蚀绝缘层144的工艺形成并且暴露导电层140的一部分。导电层140的另外的部分仍旧被绝缘层144覆盖。开口152为稍后形成的第二UBM层的形成提供位置。开口152的侧壁基本上是垂直的或有角度的。
开口154形成在导电层132的占用空间以外的绝缘层144的周边并且在具有高度H1的一部分绝缘层134上。开口154从绝缘层144的顶表面148穿过绝缘层延伸到绝缘层的底表面146。在开口154的周边的绝缘层144的剩余部分包括足够容纳稍后形成的凸块的区域。在一个实施例中，绝缘层144的剩余部分具有比导电层132的面积大的面积。
在绝缘层144被图案化和刻蚀以形成开口152和154后，以高温度剧增（high temperature excursion）来固化绝缘层。因为绝缘层144在第二UBM层的形成之前被固化了，所以在高温剧增期间在导电层140的Ti和稍后形成的第二UBM层的Cu之间形成IMC的风险被减小了。在固化之后绝缘层144经历清除浮渣处理。
在图5g中，通过利用图案化和金属沉积工艺，例如印刷、PVD、CVD、溅射、电解电镀和无电极电镀，导电层160被形成在绝缘层144和导电层140上并且被共形地施加到绝缘层144和导电层140。在一个实施例中，导电层160包括Ti和Cu、TiW和Cu、或Cr和Cu，并且利用溅射或其它合适的金属沉积工艺形成。可替换地，导电层160可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适导电材料。导电层160跨越导电层的顶表面、沿绝缘层144的侧壁、跨越绝缘层144的顶表面148、沿绝缘层144中的开口152内的绝缘层144的侧壁、以及跨越被开口152暴露的该部分区域142遵循导电层140的轮廓。导电层160用作稍后形成的凸块的第二UBM或凸块焊盘。因为导电层160遵循开口152的轮廓并且形成在绝缘层144的顶表面148上，所以绝缘层形成在导电层160和导电层140的一部分之间并且分隔该部分导电层160和导电层140。通过绝缘层144在导电层140和导电层160之间的分隔减小了形成Sn-Cu IMC的风险。在常规POU结构中，例如图1中所示的POU 10，来自凸块24的Sn将沿Ni UMB 20的侧壁行进以与UBM Cu 18反应，从而产生Sn-Cu IMC。包括导电层140、绝缘层144、和导电层160的双UBM结构减小了来自稍后形成的凸块的Sn与UBM Cu反应的风险。在形成导电层160之后，部分完成的双UBM结构经历洗涤器清洗过程。
在图5h中，光致抗蚀剂166被沉积在导电层160上。光致抗蚀剂166的底表面168覆盖并且遵循导电层160的轮廓。光致抗蚀剂166的顶表面170基本上是平的。光致抗蚀剂166包括具有PET支撑膜的DFR材料。DFR被层叠，经历边缘漂洗，在导电层160上被对准，PET支撑膜被除去，然后DFR材料被显影。可以利用可见光激光器照射DFR以形成期望的图案。被照射的DFR材料然后经受显影剂处理，所述显影剂选择性地溶解光致抗蚀剂材料的未被照射的部分并且使光致抗蚀剂材料的被照射的部分保持原样。
因此，图5h进一步示出光致抗蚀剂166被图案化和被刻蚀以形成开口172。开口172从光致抗蚀剂166的顶表面170穿过光致抗蚀剂层延伸到光致抗蚀剂层的底表面168。开口172的占用空间具有的面积大于开口152的面积并且小于绝缘层144的剩余部分。在一个实施例中，开口172包括比导电层132的占用空间小的占用空间。开口172暴露导电层160的一部分。导电层160的另外的部分仍旧被光致抗蚀剂166覆盖。开口172为随后凸块材料的沉积提供位置。在形成开口172之后，DFR经历第一次清除浮渣、硬烘、以及第二次清除浮渣。
在图5i中，利用蒸发、电解电镀、无电极电镀、或丝网印刷工艺将导电凸块材料176沉积在开口172内和导电层160上。当使用丝网印刷工艺时，凸块材料176在被沉积时是膏剂并且需要回流循环以在除去光致抗蚀剂层166之前固化凸块材料。回流凸块材料176固化所述膏剂并且防止凸块材料随着随后光致抗蚀剂层166的除去而被除去或洗掉。当利用蒸发、电解电镀、或无电极电镀沉积凸块材料176时，凸块材料形成固体凸块并且不需要额外的回流循环。
在一个实施例中，凸块材料176是无铅焊料。可替换地，凸块材料176可以是任何金属或其它导电材料，例如Sn、Ni、Au、Ag、Pb、Bi、及其合金，以及可选的焊剂材料。例如，焊料材料可以是共晶Sn/Pb、高铅、或无铅。
在图5j中，光致抗蚀剂层166被除去。在一个实施例中，通过利用等离子体或活性氯气除去DFR层以暴露凸块材料176的侧壁。光致抗蚀剂层166被剥掉，留下凸块材料176在导电层160上。
在图5k中，导电层160被刻蚀以除去被凸块材料176暴露的一部分导电层。导电层160的刻蚀也除去了在凸块材料176下面的外围区域中的一部分导电层。导电层160的外围部分的除去形成了凹进180，所述凹进180部分地但不完全地在凸块材料176之下延伸。因此，在形成凹进180之后，凸块材料176延伸到导电层160的端部以外并且悬于导电层之上。导电层160具有比导电层132的面积小的面积，或可替换地，可以具有比导电层132的面积大的面积。类似地，导电层140被刻蚀以除去被绝缘层144暴露的一部分导电层。导电层140的刻蚀也除去了在绝缘层144下面的外围区域中的一部分导电层。导电层140的外围部分的除去形成了凹进182，所述凹进182部分地但不完全地在绝缘层144之下延伸。因此，在形成凹进182之后，绝缘层144延伸到导电层140的端部以外并且悬于导电层之上。被刻蚀的导电层140可以具有等于或大于导电层132的面积的面积。在刻蚀之后，部分完成的双UBM结构经历洗涤器清洗过程。
在图5l中，通过将凸块材料176加热到它的熔点以上来回流凸块材料176以形成球形球或凸块188。凸块材料176也可以利用可选的焊剂材料来被回流。在一些应用中，凸块188被二次回流以改善到导电层160的电接触。凸块188代表一种可以形成在导电层160上的互连结构。所述互连结构也可以使用3D互连、导电胶、柱形凸块、微凸块、或其它电互连。在形成凸块188之后，双UBM结构经历可选的焊剂清洁，凸块被测量，并且双UBM结构经历FVI。
因此，通过在倒装芯片组装和可靠性测试期间减少裂缝和分层，双UBM结构相对于常规聚酰亚胺和无铅凸块结构提供了改善的低k电介质设计。此外，因为绝缘层144在第二UBM层形成之前并且在第一和第二UBM层的Ti和Cu接触之前被固化，所以在高温度剧增期间在Ti和Cu之间形成IMC的风险被减小了。另外，因为导电层160遵循开口152的轮廓并且形成在绝缘层144的顶表面148上，所以绝缘层形成在一部分导电层140和160之间并且分隔该部分导电层140和160。通过绝缘层144在导电层140和160之间的分隔降低了形成Sn-Cu IMC的风险。在常规POU结构中，例如图1中所示的POU 10，来自凸块24的Sn沿Ni UMB 20的侧壁行进以与UBM Cu 18反应，从而产生Sn-Cu IMC。最后，对于大量制造（HVM）而言，所述方法和器件提供的工艺窗口比另外由常规POU凸块结构提供的工艺窗口更宽。更宽的HVM窗口起因于多种应力缓冲材料和剥离器的增加，所述多种应力缓冲材料和剥离器可以被用来制造双UBM结构而没有化学损伤问题。
类似于图5l，图6示出半导体晶片196的一部分的放大截面图，集中于双UBM结构194。导电层198形成在半导体晶片196的有源表面上并且在半导体晶片196的有源表面上延伸，使得导电层198的顶表面产生不平坦的表面，并且相对于半导体晶片196具有非平面表面形貌。绝缘或钝化层200形成在半导体晶片196上并且直接接触导电层198的侧壁。绝缘层200与图5c中的绝缘层134的不同之处在于没有在相邻导电层198上延伸。在图5c中，绝缘层134在相邻导电层132上延伸。图6进一步示出通过利用图案化和金属沉积工艺（例如印刷、PVD、CVD、溅射、电解电镀、和无电极电镀）被形成在绝缘层200和导电层198上并且被共形地施加到绝缘层200和导电层198的导电层202。在一个实施例中，导电层202是通过溅射形成的Ti，包括具有平面表面形貌的顶部和底部表面，并且用作第一UBM。利用PVD、CVD、丝网印刷、旋涂、喷涂、烧结或热氧化，绝缘或钝化层204被沉积在导电层202上并且被共形地施加到导电层202。在一个实施例中，绝缘层204包括聚酰亚胺、PBO、或BCB。在第二UBM层形成之前，利用高温度剧增固化绝缘层204。因此在高温度剧增期间在导电层202的Ti和稍后形成的第二UBM层的Cu之间的IMC形成的风险被降低了。在一个实施例中，绝缘层204具有比导电层198的面积大的面积。导电层202被刻蚀以形成凹进203，所述凹进203部分地但不是完全地在绝缘层204之下延伸。因此，在形成凹进203之后，绝缘层204延伸到导电层202的端部以外并且悬于导电层之上。通过利用图案化和金属沉积工艺，导电层206形成在绝缘层204和导电层202上并且被共形地施加到绝缘层204和导电层202。在一个实施例中，导电层206是一层或多层的Ti、Cu、Ni、Ti和Cu、TiW和Cu、或Cr和Cu，并且利用溅射或其它合适的金属沉积工艺形成。导电层206用作用于稍后形成的凸块的第二UBM或凸块焊盘。绝缘层204形成在导电层202和206的一部分之间并且分隔该部分导电层202和206。通过绝缘层204在导电层202和206之间的分隔降低了形成Sn-Cu IMC的风险。导电层206具有比导电层198的面积小的面积，或可替换地，可以具有比导电层198的面积大的面积。球形球或凸块208形成在导电层206上并且电连接到导电层206。凸块208包括任何合适的导电材料，并且在一个实施例中是无铅焊料。在一个实施例中，凸块208的占用空间具有的面积大于导电层198的面积并且小于绝缘层204。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (25)

1.一种制造半导体器件的方法，包括：
提供具有接触焊盘的衬底；
在衬底和接触焊盘上形成第一绝缘层；
在第一绝缘层上形成第一凸块下金属化（UBM），所述第一凸块下金属化（UBM）电连接到接触焊盘；
在第一UBM上形成第二绝缘层；
在第二绝缘层被固化之后在第二绝缘层上形成第二UBM，第二UBM电连接到第一UBM使得第二绝缘层在第一和第二UBM的多个部分之间并且分隔第一和第二UBM的多个部分；
在第二UBM上形成光致抗蚀剂层并且除去光致抗蚀剂层的一部分以在接触焊盘上的光致抗蚀剂层中形成开口；
在光致抗蚀剂层中的开口内沉积导电凸块材料；
除去光致抗蚀剂层；
除去第二UBM的外围部分使得导电凸块材料悬于第二UBM之上；
除去第一UBM的外围部分使得第二绝缘层悬于第一UBM之上；以及
回流导电凸块材料以形成球形凸块。
2.根据权利要求1的方法，其中第二绝缘层是利用高温度剧增被固化的聚酰亚胺。
3.根据权利要求1的方法，其中导电凸块材料无铅。
4.根据权利要求1的方法，其中第一UBM是钛、钛钨、或铬。
5.根据权利要求1的方法，其中第二UBM是钛和铜、钛钨和铜、或铬和铜。
6.一种制造半导体器件的方法，包括：
提供具有接触焊盘的衬底；
在衬底上形成第一凸块下金属化（UBM），所述第一凸块下金属化（UBM）电连接到接触焊盘；
在第一UBM上形成绝缘层；
在绝缘层被固化后在绝缘层上形成第二UBM，第二UBM电连接到第一UBM使得第二绝缘层分隔第一和第二UBM的多个部分；以及
在第二UBM上形成凸块。
7.根据权利要求6的方法，其中绝缘层是利用高温度剧增被固化的聚酰亚胺。
8.根据权利要求6的方法，其中凸块无铅。
9.根据权利要求6的方法，其中第一UBM是钛、钛钨、或铬。
10.根据权利要求6的方法，其中第二UBM是钛和铜、钛钨和铜、或铬和铜。
11.根据权利要求6的方法，其中第一UBM具有比接触焊盘的面积大的面积。
12.根据权利要求6的方法，其中第一和第二UBM的外围部分被除去使得凸块悬于第二UBM之上并且绝缘层悬于第一UBM之上。
13.一种制造半导体器件的方法，包括：
提供具有接触焊盘的衬底；
在衬底上形成第一凸块下金属化（UBM），第一凸块下金属化（UBM）电连接到接触焊盘；
在第一UBM上形成绝缘层；
在绝缘层被固化之后在绝缘层上形成第二UBM，以及；
在第二UBM上形成凸块。
14.根据权利要求13的方法，其中绝缘层是利用高温度剧增被固化的聚酰亚胺。
15.根据权利要求13的方法，其中凸块无铅。
16.根据权利要求13的方法，其中第一UBM是钛、钛钨、或铬，并且第二UBM是钛和铜、钛钨和铜、或铬和铜。
17.根据权利要求13的方法，其中第一UBM具有比接触焊盘的面积大的面积。
18.根据权利要求13的方法，其中第一和第二UBM的多个部分被除去使得凸块悬于第二UBM之上并且绝缘层悬于第一UBM之上。
19.根据权利要求13的方法，其中绝缘层在第一和第二UBM的多个部分之间。
20.一种半导体器件，包括：
具有接触焊盘的衬底；
具有比接触焊盘的面积更大的面积的第一凸块下金属化（UBM），所述第一凸块下金属化（UBM）形成在衬底上并且被电连接到接触焊盘；
形成在第一UBM上的绝缘层；
第二UBM，所述第二UBM形成在绝缘层上并且被电连接到第一UBM使得绝缘层在第一和第二UBM的多个部分之间；以及
形成在第二UBM上的凸块。
21.根据权利要求20的半导体器件，其中绝缘层是高温固化的聚酰亚胺。
22.根据权利要求20的半导体器件，其中凸块无铅。
23.根据权利要求20的半导体器件，其中第一UBM是钛、钛钨、或铬。
24.根据权利要求20的半导体器件，其中第二UBM是钛和铜、钛钨和铜、或铬和铜。
25.根据权利要求20的半导体器件，其中凸块悬于第二UBM之上并且绝缘层悬于第一UBM之上。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810601A (zh) * 2016-04-19 2016-07-27 南通富士通微电子股份有限公司 一种半导体芯片封装结构及其制作方法
CN106548997A (zh) * 2015-09-22 2017-03-29 三星电子株式会社 半导体器件和电子器件
CN109065459A (zh) * 2018-07-27 2018-12-21 大连德豪光电科技有限公司 焊盘的制作方法

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8299632B2 (en) * 2009-10-23 2012-10-30 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
US8629053B2 (en) * 2010-06-18 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma treatment for semiconductor devices
JP2012038965A (ja) * 2010-08-09 2012-02-23 Lapis Semiconductor Co Ltd 半導体装置及びその製造方法
US8492892B2 (en) * 2010-12-08 2013-07-23 International Business Machines Corporation Solder bump connections
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
US9258907B2 (en) 2012-08-09 2016-02-09 Lockheed Martin Corporation Conformal 3D non-planar multi-layer circuitry
US8822327B2 (en) 2012-08-16 2014-09-02 Infineon Technologies Ag Contact pads with sidewall spacers and method of making contact pads with sidewall spacers
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
CN103165553A (zh) * 2013-02-04 2013-06-19 日月光半导体制造股份有限公司 半导体晶圆及半导体封装构造
US9257647B2 (en) * 2013-03-14 2016-02-09 Northrop Grumman Systems Corporation Phase change material switch and method of making the same
US8772745B1 (en) 2013-03-14 2014-07-08 Lockheed Martin Corporation X-ray obscuration film and related techniques
US9349700B2 (en) 2013-04-24 2016-05-24 Stats Chippac, Ltd. Semiconductor device and method of forming stress-reduced conductive joint structures
US20150069585A1 (en) * 2013-09-12 2015-03-12 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device with an angled passivation layer
US9806220B2 (en) * 2013-11-12 2017-10-31 Ob Realty, Llc Metal foil metallization for backplane-attached solar cells and modules
US9824989B2 (en) 2014-01-17 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package and methods of forming thereof
TWI620290B (zh) * 2014-05-27 2018-04-01 聯華電子股份有限公司 導電墊結構及其製作方法
US10804153B2 (en) 2014-06-16 2020-10-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method to minimize stress on stack via
US10123410B2 (en) 2014-10-10 2018-11-06 Lockheed Martin Corporation Fine line 3D non-planar conforming circuit
TWI690083B (zh) * 2015-04-15 2020-04-01 杰力科技股份有限公司 功率金氧半導體場效電晶體及其製作方法
TWI621229B (zh) * 2015-04-27 2018-04-11 精材科技股份有限公司 晶片封裝體及其製造方法
JP6524809B2 (ja) * 2015-06-10 2019-06-05 富士電機株式会社 半導体装置
US9520372B1 (en) 2015-07-20 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package (WLP) and method for forming the same
TWI549230B (zh) * 2015-09-07 2016-09-11 矽品精密工業股份有限公司 半導體結構及其製法
KR102410018B1 (ko) * 2015-09-18 2022-06-16 삼성전자주식회사 반도체 패키지
DE102016200063B4 (de) 2016-01-06 2017-08-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung von Metallstrukturen und elektronisches Bauteil mit mindestens einer Metallstruktur
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10700270B2 (en) 2016-06-21 2020-06-30 Northrop Grumman Systems Corporation PCM switch and method of making the same
JP7214966B2 (ja) * 2018-03-16 2023-01-31 富士電機株式会社 半導体装置及び半導体装置の製造方法
KR102127828B1 (ko) 2018-08-10 2020-06-29 삼성전자주식회사 반도체 패키지
US11546010B2 (en) 2021-02-16 2023-01-03 Northrop Grumman Systems Corporation Hybrid high-speed and high-performance switch system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101106114A (zh) * 2006-07-11 2008-01-16 日月光半导体制造股份有限公司 芯片结构及其形成方法
CN101304014A (zh) * 2007-05-07 2008-11-12 索尼株式会社 半导体芯片及其制造方法
CN102034779A (zh) * 2009-10-08 2011-04-27 台湾积体电路制造股份有限公司 具有坚固的拐角凸块的芯片设计

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5268319A (en) * 1988-06-08 1993-12-07 Eliyahou Harari Highly compact EPROM and flash EEPROM devices
GB9200643D0 (en) * 1992-01-13 1992-03-11 Tectron Manufacturing Hk Limit Educational toys
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
US5807453A (en) * 1995-05-04 1998-09-15 Tessera, Inc. Fabrication of leads on semiconductor connection components
US5841166A (en) * 1996-09-10 1998-11-24 Spectrian, Inc. Lateral DMOS transistor for RF/microwave applications
US6020640A (en) * 1996-12-19 2000-02-01 Texas Instruments Incorporated Thick plated interconnect and associated auxillary interconnect
US6731007B1 (en) * 1997-08-29 2004-05-04 Hitachi, Ltd. Semiconductor integrated circuit device with vertically stacked conductor interconnections
JP3068534B2 (ja) * 1997-10-14 2000-07-24 九州日本電気株式会社 半導体装置
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
US6166444A (en) * 1999-06-21 2000-12-26 United Microelectronics Corp. Cascade-type chip module
KR100306842B1 (ko) * 1999-09-30 2001-11-02 윤종용 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
US6136688A (en) * 1999-10-20 2000-10-24 Vanguard International Semiconductor Corporation High stress oxide to eliminate BPSG/SiN cracking
KR100319813B1 (ko) * 2000-01-03 2002-01-09 윤종용 유비엠 언더컷을 개선한 솔더 범프의 형성 방법
US6586323B1 (en) * 2000-09-18 2003-07-01 Taiwan Semiconductor Manufacturing Company Method for dual-layer polyimide processing on bumping technology
JP2002110799A (ja) * 2000-09-27 2002-04-12 Toshiba Corp 半導体装置及びその製造方法
US6534396B1 (en) * 2000-10-10 2003-03-18 Taiwan Semiconductor Manufacturing Co., Ltd. Patterned conductor layer pasivation method with dimensionally stabilized planarization
US6462426B1 (en) * 2000-12-14 2002-10-08 National Semiconductor Corporation Barrier pad for wafer level chip scale packages
US6426281B1 (en) * 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
KR100352236B1 (ko) * 2001-01-30 2002-09-12 삼성전자 주식회사 접지 금속층을 갖는 웨이퍼 레벨 패키지
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
KR100389037B1 (ko) * 2001-04-11 2003-06-25 삼성전자주식회사 플립 칩형 반도체소자 및 그 제조방법
US6596611B2 (en) * 2001-05-01 2003-07-22 Industrial Technology Research Institute Method for forming wafer level package having serpentine-shaped electrode along scribe line and package formed
US6756184B2 (en) * 2001-10-12 2004-06-29 Taiwan Semiconductor Manufacturing Co., Ltd Method of making tall flip chip bumps
US6586322B1 (en) * 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
US7122904B2 (en) * 2002-04-25 2006-10-17 Macronix International Co., Ltd. Semiconductor packaging device and manufacture thereof
US6596619B1 (en) 2002-05-17 2003-07-22 Taiwan Semiconductor Manufacturing Company Method for fabricating an under bump metallization structure
US6590295B1 (en) * 2002-06-11 2003-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic device with a spacer redistribution layer via and method of making the same
US7531898B2 (en) * 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
US20040040855A1 (en) * 2002-08-28 2004-03-04 Victor Batinovich Method for low-cost redistribution and under-bump metallization for flip-chip and wafer-level BGA silicon device packages
WO2004059708A2 (en) * 2002-12-20 2004-07-15 Agere Systems Inc. Structure and method for bonding to copper interconnect structures
US6878633B2 (en) 2002-12-23 2005-04-12 Freescale Semiconductor, Inc. Flip-chip structure and method for high quality inductors and transformers
US7208825B2 (en) * 2003-01-22 2007-04-24 Siliconware Precision Industries Co., Ltd. Stacked semiconductor packages
US6872589B2 (en) * 2003-02-06 2005-03-29 Kulicke & Soffa Investments, Inc. High density chip level package for the packaging of integrated circuits and method to manufacture same
TW584936B (en) * 2003-03-20 2004-04-21 Advanced Semiconductor Eng Wafer bumping process
US6897561B2 (en) * 2003-06-06 2005-05-24 Semiconductor Components Industries, Llc Semiconductor power device having a diamond shaped metal interconnect scheme
TW589727B (en) * 2003-06-30 2004-06-01 Advanced Semiconductor Eng Bumping structure and fabrication process thereof
TWI229436B (en) * 2003-07-10 2005-03-11 Advanced Semiconductor Eng Wafer structure and bumping process
US7244671B2 (en) 2003-07-25 2007-07-17 Unitive International Limited Methods of forming conductive structures including titanium-tungsten base layers and related structures
US6951803B2 (en) * 2004-02-26 2005-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method to prevent passivation layer peeling in a solder bump formation process
EA009510B1 (ru) * 2004-03-19 2008-02-28 Спортс Инновейшн Ас Коврик для игр и занятий спортом
US7189594B2 (en) * 2004-09-10 2007-03-13 Agency For Science, Technology And Research Wafer level packages and methods of fabrication
TWI251284B (en) * 2004-11-12 2006-03-11 Advanced Semiconductor Eng Redistribution layer and circuit structure thereof
JP2006287094A (ja) * 2005-04-04 2006-10-19 Seiko Epson Corp 半導体装置及びその製造方法
US7329951B2 (en) * 2005-04-27 2008-02-12 International Business Machines Corporation Solder bumps in flip-chip technologies
JP4449824B2 (ja) * 2005-06-01 2010-04-14 カシオ計算機株式会社 半導体装置およびその実装構造
DE102005051573B4 (de) * 2005-06-17 2007-10-18 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik MIM/MIS-Struktur mit Praseodymtitanat als Isolatormaterial
US7364998B2 (en) * 2005-07-21 2008-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming high reliability bump structure
US7053490B1 (en) * 2005-07-27 2006-05-30 Semiconductor Manufacturing International (Shanghai) Corporation Planar bond pad design and method of making the same
US7566650B2 (en) * 2005-09-23 2009-07-28 Stats Chippac Ltd. Integrated circuit solder bumping system
US7473999B2 (en) * 2005-09-23 2009-01-06 Megica Corporation Semiconductor chip and process for forming the same
US20070087544A1 (en) * 2005-10-19 2007-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming improved bump structure
TWI298204B (en) * 2005-11-21 2008-06-21 Advanced Semiconductor Eng Structure of bumps forming on an under metallurgy layer and method for making the same
US7659193B2 (en) * 2005-12-23 2010-02-09 Phoenix Precision Technology Corporation Conductive structures for electrically conductive pads of circuit board and fabrication method thereof
TWI293789B (en) * 2006-02-27 2008-02-21 Advanced Semiconductor Eng Redistribution connecting structure of solder balls
JP2007317979A (ja) * 2006-05-29 2007-12-06 Toshiba Corp 半導体装置の製造方法
JP4247690B2 (ja) * 2006-06-15 2009-04-02 ソニー株式会社 電子部品及その製造方法
US7569422B2 (en) * 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
JP5073992B2 (ja) * 2006-08-28 2012-11-14 オンセミコンダクター・トレーディング・リミテッド 半導体装置
US20080054461A1 (en) 2006-08-30 2008-03-06 Dennis Lang Reliable wafer-level chip-scale package solder bump structure in a packaged semiconductor device
US8440272B2 (en) * 2006-12-04 2013-05-14 Megica Corporation Method for forming post passivation Au layer with clean surface
KR100817079B1 (ko) * 2006-12-05 2008-03-26 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지, 그 제조 방법, 및 웨이퍼레벨 칩 스케일 패키지를 포함하는 반도체 칩 모듈
TWI320588B (en) * 2006-12-27 2010-02-11 Siliconware Precision Industries Co Ltd Semiconductor device having conductive bumps and fabrication methodthereof
US7456090B2 (en) * 2006-12-29 2008-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method to reduce UBM undercut
US7838991B1 (en) * 2007-02-05 2010-11-23 National Semiconductor Corporation Metallurgy for copper plated wafers
US8193636B2 (en) * 2007-03-13 2012-06-05 Megica Corporation Chip assembly with interconnection by metal bump
SG193796A1 (en) 2007-07-30 2013-10-30 Stats Chippac Ltd Semiconductor device and method of providing common voltage bus and wire bondable redistribution
KR100885924B1 (ko) * 2007-08-10 2009-02-26 삼성전자주식회사 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
US8241954B2 (en) * 2007-12-03 2012-08-14 Stats Chippac, Ltd. Wafer level die integration and method
JP5007250B2 (ja) * 2008-02-14 2012-08-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE102008044984A1 (de) * 2008-08-29 2010-07-15 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Verspannungsrelaxationsspalte zur Verbesserung der Chipgehäusewechselwirkungsstabilität
JP5203108B2 (ja) * 2008-09-12 2013-06-05 新光電気工業株式会社 配線基板及びその製造方法
TW201015718A (en) * 2008-10-03 2010-04-16 Sanyo Electric Co Semiconductor device and method for manufacturing the same
KR101589690B1 (ko) * 2008-12-18 2016-01-29 삼성전자주식회사 반도체 소자의 본딩 패드 및 그의 제조방법
US7985671B2 (en) * 2008-12-29 2011-07-26 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices
US20100167471A1 (en) * 2008-12-30 2010-07-01 Stmicroelectronics Asia Pacific Pte. Ltd. Reducing warpage for fan-out wafer level packaging
US20100193950A1 (en) * 2009-01-30 2010-08-05 E.I.Du Pont De Nemours And Company Wafer level, chip scale semiconductor device packaging compositions, and methods relating thereto
JP5291485B2 (ja) * 2009-02-13 2013-09-18 ラピスセミコンダクタ株式会社 半導体装置の製造方法
JP5714564B2 (ja) * 2009-03-30 2015-05-07 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ 上部ポストパッシベーション技術および底部構造技術を使用する集積回路チップ
US7977783B1 (en) * 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
US8772087B2 (en) * 2009-10-22 2014-07-08 Infineon Technologies Ag Method and apparatus for semiconductor device fabrication using a reconstituted wafer
JP2011108927A (ja) * 2009-11-19 2011-06-02 Elpida Memory Inc 半導体装置の製造方法
JP2011249564A (ja) * 2010-05-27 2011-12-08 Renesas Electronics Corp 半導体装置の製造方法及び実装構造
US8258055B2 (en) * 2010-07-08 2012-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor die

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101106114A (zh) * 2006-07-11 2008-01-16 日月光半导体制造股份有限公司 芯片结构及其形成方法
CN101304014A (zh) * 2007-05-07 2008-11-12 索尼株式会社 半导体芯片及其制造方法
CN102034779A (zh) * 2009-10-08 2011-04-27 台湾积体电路制造股份有限公司 具有坚固的拐角凸块的芯片设计

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106548997A (zh) * 2015-09-22 2017-03-29 三星电子株式会社 半导体器件和电子器件
CN106548997B (zh) * 2015-09-22 2020-06-09 三星电子株式会社 半导体器件和电子器件
CN105810601A (zh) * 2016-04-19 2016-07-27 南通富士通微电子股份有限公司 一种半导体芯片封装结构及其制作方法
CN109065459A (zh) * 2018-07-27 2018-12-21 大连德豪光电科技有限公司 焊盘的制作方法

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