CN102169837B

CN102169837B - Preparation method of single electron transistor at room temperature

Info

Publication number: CN102169837B
Application number: CN 201110059597
Authority: CN
Inventors: 李加东; 吴东岷; 谢杰
Original assignee: Suzhou Institute of Nano Tech and Nano Bionics of CAS
Current assignee: Suzhou Institute of Nano Tech and Nano Bionics of CAS
Priority date: 2011-03-12
Filing date: 2011-03-12
Publication date: 2013-05-01
Anticipated expiration: 2031-03-12
Also published as: CN102169837A

Abstract

The invention relates to a method for preparing a room-temperature single-electron transistor. The method is as follows: processing and forming the source, drain and gate of the single-electron transistor on the surface of the substrate, and making the electrode region and the non-electrode region on the substrate surface be loaded with different charges by modifying different reagents, so that An electrostatic funnel structure is formed on the substrate; at least the surface of the substrate is placed in a dispersion of nanoparticles, so that the nanoparticles are arranged between the source and the drain of the single-electron transistor under the guidance of the electrostatic funnel; The bottom is dried, and an insulating layer is covered on the surface of the substrate. The invention has at least the advantages of overcoming the problems of oversized quantum dots, disordered arrangement of quantum dots and inability to prepare single electron transistors on a large scale in current single electron transistors, and at the same time reducing the production cost of single electron transistors.

Description

The preparation method of single electron transistor at room temperature

Technical field

The present invention relates to a kind of preparation method of single-electronic transistor, relate in particular to and a kind ofly disperse and pinpoint single electron transistor at room temperature preparation method based on nano particle, belong to nanometer and make the field.

Background technology

Nanoelectronic learns a skill (nanoelectronics) as one of great scientific research content of clearly disposing with an emphasis in the National Program for Medium-to Long-term Scientific and Technological Development, has very important significance.In advanced information society, obtaining, amplify, store, process, transmit, change and showing of information all be unable to do without the development of electronics.The development in electronics technology future will be target with " less, faster, colder "." less " is the integrated level that further improves chip, and " faster " is to realize higher information computing and processing speed, and " colder " then is the power consumption that further reduces chip.Only all obtain synchronous development at this three aspects:, the electronics technology just can obtain new important breakthrough.Realize this goal, the size of electronic device must enter the range scale of nanometer technology, and single-electronic transistor will be the final goal of logical device development.But the advantages such as size is little, speed is fast, large-scale integrated low in energy consumption that single-electronic transistor has, can be used for single-electron memory, logical circuit, current/resistance/temperature standard, the various applied environments such as microwave or Infrared Detectors have very wide application prospect.

Typical single-electronic transistor (single electron transistor) basic structure comprises two electrodes (source electrode and drain electrode), quantum dot by tunneling barrier and two electrode couplings (coulomb island), and with the capacity coupled grid of this quantum dot.It can realize logical operation under nanoscale, be based on the novel nano electronic device of coulomb blockade effect and single tunneling effe.Single-electronic transistor can control Single Electron one by one pass through quantum dot from the source tunnelling to drain terminal, and with metal-oxide semiconductor (MOS) (metal oxidesemiconductor, MOS) device function is similar, can realize logic function at nanoscale.Compare (approximately having comprised 200,000 electronics) with at present general memory stores unit, each storage element of single-electronic transistor only comprises one or a small amount of electronics, therefore it will reduce power consumption greatly, improve the integrated level of integrated circuit, in following nanometer integrated circuit, will play the part of very important role.Studies show that if with quantum dot array as in the single-electronic transistor structure the coulomb island, must make the size of quantum dot less than 10 nanometers, just might realize the single-electronic transistor device of room temperature; When the quantum spot size less than 5nm, just can work at normal temperatures by the bonding electron transistor.

The micro-nano process technology commonly used that can be used at present the single-electronic transistor making mainly contains following several: 1) optical exposure technology; 2) electron beam lithography; 3) focused ion beam process technology; 4) scan-probe process technology; 5) nanometer embossing.Above-mentioned process technology all can be classified as traditional process technology, although experienced the developing history in more than 50 year, basic processing mode there is no too large variation, still is a kind of " from top to bottom " processing mode (top-down).This processing mode finally is subject to the ability of machining tool: the resolution capability of lithography tool or etching apparatus.Along with dwindling of processing yardstick, the cost of tradition nanofabrication technique is more and more higher, arrived the following physical dimension of 10nm, traditional manufacturing process is helpless, and replenish or the alternative concern that is subject to micro-nano processing industry as a kind of based on the nanofabrication technique of molecular self-assembling, this manufacturing process has the processing yardstick much smaller than traditional nanoprocessing achieved physical dimension and the low advantage of cost, thereby is considered to comprise one of developing important nanometer manufacturing means of WeiLai Technology such as nano-electron.

The patent No. is US6,984,845 patent of invention discloses the single-electronic transistor of making based on nano particle, and nano particle adopts the method preparation of physics or chemistry, then be ejected into source electrode and the drain electrode between as quantum dot, like this formation the quantum dot irregular arrangement.The patent No. is US7,067,341 patent of invention discloses based on the electromigratory method for fabricating transistor of single electron of metal nanometer cluster, and the method applies voltage between source electrode and drain electrode, makes nano particle form quantum dot between dropping on source electrode and draining under the effect of electric field force.The method is difficult to effectively control the ordered arrangement of nanostructure, and inapplicable large-scale integrated is made the consistent single-electronic transistor of character height.

Summary of the invention

For many defectives of the prior art, the present invention proposes a kind of preparation method of single electron transistor at room temperature, the ordered arrangement that it can accurately realize nanostructure easily is suitable for preparing on a large scale single-electronic transistor.

For achieving the above object, the present invention has adopted following technical scheme:

A kind of preparation method of single electron transistor at room temperature is characterized in that, the method is:

Be processed to form source electrode, the drain and gate of single-electronic transistor at substrate surface, and make electrode zone and non-electrode zone difference load xenogenesis electric charge on this substrate surface, thereby form the static funnel structure at substrate;

Place the dispersion liquid of nano particle to this substrate surface of major general, make nano particle between the source electrode that is arranged in single-electronic transistor under the guiding of static funnel and drain electrode;

Substrate is carried out drying process, and cover insulating barrier at this substrate surface.

Preferably, the method can comprise the steps:

Adopt micro fabrication to make the source electrode of single-electronic transistor, drain and gate at substrate surface;

Adopt respectively the first reagent and the second reagent to modify electrode zone and non-electrode zone on this substrate surface, make respectively load xenogenesis electric charge of this electrode zone and non-electrode zone, thereby form the pinpoint static funnel structure of bootable nano particle at substrate;

This substrate is immersed in the dispersion liquid of nano particle, make nano particle between the source electrode that drops on single-electronic transistor under the guiding of static funnel and drain electrode;

After substrate dried up, at this substrate surface deposition one insulating barrier.

Described substrate thickness is 280 μ m～2mm, and this substrate preferably adopts any one in monocrystalline substrate, Sapphire Substrate and the glass substrate with silicon dioxide insulating layer.

Described source electrode, drain electrode and gate are 5nm～600nm, and the distance between source electrode and the drain electrode is 5nm～20nm, and its concrete size is according to the size adjustment of quantum dot and be not less than the size of quantum dot.Described source electrode, drain and gate are by any one or being combined to form more than two kinds among Ti, Au, Al, Pt and the Cu.

Further, preferred Ti-Au or the Cr-Au of adopting of described source electrode and drain electrode makes.

Described the first reagent preferably adopts and can form the tail base in gold surface and be the organosulfur compound of-COOH;

Described the second reagent preferably adopts and can form the tail base at silica surface and be-N ₂The biological reagent of H.

Further, described the first reagent preferably adopts any one in 16-sulfydryl hexadecylic acid, sulfydryl undecanoic acid and the TGA;

Described the second reagent preferably adopts APTES.

Described nano particle diameter especially preferably adopts the Au nano particle less than 10nm.

Described thickness of insulating layer is 2nm to 40nm, and this insulating barrier is by any one or being combined to form more than two kinds in silicon dioxide, alchlor and the titanic oxide material.

Compared with prior art, advantage of the present invention is at least: overcome that current single-electronic transistor quantum dot size is excessive, quantum dot is arranged unordered and do not possess the problem of the aspects such as ability of extensive preparation single-electronic transistor, has reduced simultaneously the production cost of single-electronic transistor.

Description of drawings

Fig. 1 is the structural representation of a preferred embodiment of the present invention;

The implication of each Reference numeral is as follows among the figure:

1～alundum (Al2O3) insulating barrier, 2～gold electrode, 3～quantum dot, 4～two throwing dioxygen silicon substrates.

Embodiment

Consider many defectives of existing single-electronic transistor preparation technology, this case inventor is through studying for a long period of time and putting into practice, and the spy proposes the preparation technology of single electron transistor at room temperature of the present invention, and its flow process is:

Adopt electron beam lithography and ultraviolet photolithographic at substrate first, the micro fabrications such as electron beam deposition and stripping technology are made the source electrode of single-electronic transistor, drain and gate; Then adopt two kinds of different reagent respectively modified electrode zone and non-electrode zone, obtain guiding nano particle pinpoint " static funnel ", sample after will modifying afterwards is dipped in the dispersion liquid of nano particle, and nano particle is being dropped under the guiding of " static funnel " between source electrode and the drain electrode; Last sample deposition one layer insulating after drying up.

Further, aforesaid substrate can adopt the substrate of the semiconductor components and devices that industry commonly sees, but preferably with monocrystalline silicon, the sapphire Al of silicon dioxide insulating layer ₂O ₃With the substrate of glass material, and substrate thickness is preferably 280 μ m to 2mm.

Described source electrode, drain electrode and grid can adopt Ti, Au, Al, Pt, Cu or its alloy to make, its thickness is 5nm～600nm, distance between source electrode and the drain electrode is 5nm～20nm, and its concrete size is according to the size adjustment of quantum dot and be not less than the size of quantum dot.

Obvious, among the present invention, those skilled in the art can select different reagent to modify for different substrates and electrode material according to the demand of practical application, thereby reach in the purpose that loads respectively the xenogenesis electric charge on the electrode zone on the substrate and the non-electrode zone.For example, be the single-electronic transistor electrode that the substrate of silicon dioxide material and Au form for the surface, the reagent of modified electrode is can be at the organosulfur compound of gold surface shape tail base for-COOH, particularly preferably 16-sulfydryl hexadecylic acid (C ₁₆H ₃₂O ₂S), sulfydryl undecanoic acid (SH (CH2) ₁₀COOH), TGA (C ₂H ₄O ₂S) etc., the reagent of modifying non-electrode zone is can form the tail base at silica surface to be-N ₂The biological reagent of H, particularly preferably APTES (H ₂NCH ₂CH ₂CH ₂Si (OC ₂H ₅) ₃) etc.

For aforesaid nano particle, its particle diameter is preferably less than 10nm, particularly preferably adopts the Au nano particle of this characteristic dimension.

As for aforesaid insulating barrier, it can form by various ways such as atomic force depositions, and its thickness is preferably 2nm to 40nm.This insulating barrier is preferably silicon dioxide SiO ₂, alchlor Al ₂O ₃And titanium dioxide TiO ₂Etc. material.

Below in conjunction with a preferred embodiment and accompanying drawing technical scheme of the present invention is further described.

As shown in Figure 1, for the method that guides the standby quantum dot of nano particle positioning less than the single-electronic transistor of 10nm based on " static funnel ", its preparation mainly may further comprise the steps

I, on two throwing dioxygen silicon substrates 4 by electron beam lithography and ultraviolet photolithographic, it is the gold electrode 2 of 25nm that electron beam deposition and stripping technology are made thickness, source electrode remains on 10nm with distance between draining;

The method of II, employing molecular self-assembling, elder generation is at non-electrode zone finishing one deck APTES (H of substrate 4 ₂NCH ₂CH ₂CH ₂Si (OC ₂H ₅) ₃) molecular film, make non-electrode zone with positive charge, and then modify one deck 16-sulfydryl hexadecylic acid (C in gold electrode surfaces ₁₆H ₃₂O ₂S) molecular film makes gold electrode 2 surfaces with negative electrical charge;

III, will modify good sample and be dipped in the Au nanoparticle dispersion liquid that diameter is 5nm, and make nano particle drop between source electrode and the drain electrode quantum dot 3 of formation single-electronic transistor under the guiding of " static funnel ";

After IV, employing UV ozone cleaning apparatus cleaned sample, adopting method sample deposition a layer thickness after forming quantum dot of atomic force deposition was the alundum (Al2O3) insulating barrier 1 of 3nm.

It may be noted that and be: for the person of ordinary skill of the art, can make other various corresponding changes and distortion according to technical solution of the present invention and technical conceive, and these changes and distortion all should belong to the protection range of claim of the present invention.

Claims

1. a preparation method of room temperature single electron transistor, is characterized in that, the method comprises the steps:

The source, drain and gate of the single-electron transistor are fabricated on the surface of the substrate by micromachining;

The electrode area and the non-electrode area on the surface of the substrate are respectively modified with the first reagent and the second reagent, so that the electrode area and the non-electrode area are respectively loaded with different charges, thereby forming an electrostatic field on the substrate that can guide the precise positioning of the nanoparticles. funnel structure;

The substrate is immersed in the dispersion liquid of nanoparticles, so that the nanoparticles fall between the source and the drain of the single-electron transistor under the guidance of the electrostatic funnel; the diameter of the nanoparticles is less than 10nm; the source and the drain are The distance between them is 5 nm to 20 nm, and the distance between the source and the drain is not less than the particle diameter of the nanoparticles;

After drying the substrate, depositing an insulating layer on the surface of the substrate;

The first reagent uses an organosulfur compound whose tail group is -COOH on the gold surface;

The second reagent adopts a biological reagent that can form a tail group of -N ₂ H on the surface of silica;

The nanoparticles are Au nanoparticles.

2. The method for preparing a room-temperature single-electron transistor according to claim 1, characterized in that: the thickness of the substrate is 280 μm to 2 mm, and the substrate adopts a single crystal silicon substrate with a silicon dioxide insulating layer, sapphire Either of the substrate and the glass substrate.

3. The preparation method of the room temperature single-electron transistor according to claim 1, characterized in that: the thickness of the source, the drain and the gate is 5nm to 600nm, and the source, the drain and the gate are made of Ti , Au, Al, Pt and Cu in any one or a combination of two or more formed.

4. the preparation method of room temperature single electron transistor according to claim 1, is characterized in that:

The first reagent is any one or a combination of two or more of 16-mercaptohexadecanoic acid, mercaptoundecanoic acid and thioglycolic acid;

The second reagent is 3-aminopropyltriethoxysilane.

5. The preparation method of room temperature single electron transistor according to claim 1, characterized in that: the thickness of the insulating layer is 2nm to 40nm, and the insulating layer is made of any one of silicon dioxide, aluminum oxide and titanium dioxide materials formed by a combination of two or more.