CN102891083B - A method for preparing a room temperature single-electron transistor - Google Patents

Abstract

A kind of method preparing single electron transistor at room temperature, with source electrode, drain gate, barrier layer and coulomb island as basic structure, cover layer, coulomb island, barrier layer, electrode, substrate and substrate stack gradually from top to bottom；Barrier layer on source electrode and drain electrode or on source electrode, drain and gate utilizes atomic layer deposition system to prepare, for forming the potential barrier of electron tunneling between electrode and coulomb island；Coulomb island utilizes the e-beam induced deposition of double-beam system to prepare, and its size, quantity and arrangement have controllability.The present invention accurately controls barrier layer thickness, accurately controls the assembling location on coulomb island, significantly reduces single-electronic transistor and prepare difficulty, improves batch and prepare the concordance of single-electronic transistor performance.

Description

A method for preparing a room temperature single-electron transistor

technical field

The invention relates to the technical field of nanometer electronic devices, in particular to a method for preparing room-temperature single-electron transistors by using atomic layer deposition and electron beam induced deposition techniques.

Background technique

The characteristic size of the integrated circuit with metal oxide semiconductor field effect transistor devices as the mainstream has been developed to the nanometer level, and the application is limited. Further research and development of new nanometer-sized electronic logic devices has become a development demand. Single-electron transistors have the advantages of small size, low power consumption, and large-scale integration. They have broad application prospects and can be used in various applications such as computers, sensors, and detectors. A typical single-electron transistor consists of a source, a drain, a gate, and a Coulomb island, and is a nanoelectronic device based on the Coulomb blocking effect and the single-electron tunneling effect.

In 1987, Fulton et al. of Bell Labs used mask technology to prepare aluminum quantum dots with a size of about 30 nm as Coulomb islands, and observed single-electron phenomena at an ultra-low temperature of 1.7 K. In 1989, Scott-Thomas of MIT used X-ray lithography to make a narrow electron channel with a slit electrode on the silicon inversion layer, with a width of about 30 nm and a length of 1 to 10 µm, at 400 mK It is found that the conductance of the channel exhibits periodic oscillations with the electrode voltage. Using microelectronics processes, many research groups have fabricated single-electron transistors that operate at low temperatures and at room temperature. At the same time, people have also carried out bottom-up research on the preparation of single-electron transistors. In 1995, Chen et al. prepared AuPd nanoparticles with a size of 2 to 3 nm, and the single-electron transistor constructed with this showed a significant Coulomb blocking effect at a temperature of 77 K, and nonlinear voltammetry could be observed even at room temperature. characteristic. In 1996, Klein et al. used Au nanoparticles and CdSe nanoparticles with a size of about 5.8 nm, and observed a clear Coulomb step curve at a temperature of 77 K. Since then, many research groups have used the bottom-up approach to prepare single-electron transistors, and observed single-electron phenomena at room temperature.

However, there are three key technical problems in the preparation of existing single-electron transistors: the controllable preparation of small-sized Coulomb islands; the controllable positioning and assembly of Coulomb islands; and the precise control of the size of the tunneling barrier between Coulomb islands and electrodes. This is related to the operating temperature of the device and the consistency of its performance. Therefore, researchers have long been eager to develop a preparation method that can precisely control the size and location of Coulomb islands, and control the size of the barrier between Coulomb islands and electrodes, so as to greatly promote the preparation and application of single-electron transistors.

Contents of the invention

The technical problem to be solved by the present invention is: to solve the problems existing in the above-mentioned prior art, and propose a method for preparing room temperature single-electron transistors, accurately control the thickness of the barrier layer, precisely control the assembly positioning of Coulomb islands, and significantly reduce the single-electron transistor The difficulty of preparation improves the consistency of the performance of single-electron transistors prepared in batches.

The technical scheme adopted in the present invention is: room temperature single-electron transistor, with source, drain, gate, barrier layer and Coulomb island as the basic structure, cover layer, Coulomb island, barrier layer, electrode, substrate and base are composed of Stacked sequentially from top to bottom; the barrier layer on the source and drain, or on the source, drain and gate, is prepared using an atomic layer deposition system to form a barrier for electron tunneling between the electrode and the Coulomb island. Potential barriers; Coulomb islands are prepared by electron beam-induced deposition of electron/ion dual-beam systems, and their size, quantity and arrangement are controllable.

In the above technical solution, the substrate is prepared from an oxidized Si substrate, and the source, drain, gate, barrier layer and Coulomb island are integrated on the _SiO2 substrate, and the Coulomb island is arranged on the source and drain. Between the electrodes, on the barrier layer, and completely independent of the source, drain and gate; there can be multiple Coulomb islands, arranged in any combination, and the gate is used to regulate the Coulomb island energy level.

In the above technical solution, the preparation process of the room temperature single electron transistor is as follows: first, the source, drain and gate are prepared on the substrate by electron beam direct writing, and then the source, drain and A micron-scale lead electrode connected to the gate electrode, and then use atomic layer deposition to form a barrier layer on the source and drain electrodes, and then use electron beams to induce deposition between the source electrode and the drain electrode and between the barrier layers Prepared on Coulomb Island.

In the above technical solution, the substrate is a SiO ₂ insulating layer with a thickness of 200 to 500 nm formed by thermally oxidizing a Si sheet, and is located on the Si substrate.

In the above technical solution, the source, drain and grid are prepared by electron beam exposure and electron beam evaporation coating technology, using Ti as the metal adhesion layer with a thickness of 2 to 5 nm, and using Au as the deposition material with a thickness of 3 to 25 nm.

In the above technical solution, the distance between the source and the drain is 5 to 15 nm.

In the above technical solution, the distance between the gate, the source and the drain is 1 to 5 times the distance between the source and the drain.

In the above technical solution, the barrier layer is deposited on the source electrode and the drain electrode by atomic layer deposition technology, and its thickness is 2 to 5 nm, and the thickness is precisely controllable.

In the above technical solution, the barrier layer is made of materials such as Al ₂ O ₃ or SiO ₂ .

In the above technical solution, the Coulomb island is deposited between the source electrode and the drain electrode and above the barrier layer by electron beam induced deposition technology, and the diameter of the Coulomb island is 5 to 15 nm.

In the above technical solution, the size, number and arrangement of the Coulomb islands deposited between the source and the drain and on the barrier layer can be precisely controlled.

In the above technical solution, Cu, Au, Al or W and other deposition materials are selected for the Coulomb island.

In the above technical solution, the covering layer is deposited on the source electrode, the drain electrode, the gate electrode and the Coulomb island by atomic layer deposition, thermal evaporation or sputtering.

In the above technical solution, the covering layer is made of materials such as Al ₂ O ₃ or SiO ₂ , with a thickness of 10 to 100 nm.

The electron beam exposure system, ultraviolet lithography system, electron beam evaporation coating system, and atomic layer deposition system used in the present invention are well-known mature technology, and the electron beam induced deposition of the electron/ion dual beam system adopted is also general Well-known mature technology.

For specific usage, please refer to step (2) to step (9) in "Specific Implementation Modes".

The electron beam exposure system of the present invention adopts the JBX5500ZA electron beam exposure machine of Japan Electronics; the ultraviolet lithography system of the present invention adopts the SUSS MA/BA6 lithography machine of SUSS MicroTec Company of Germany; the electron beam evaporation coating system of the present invention adopts Japan ULVAC Company The high vacuum evaporation coating system ei-5z.

The atomic layer deposition system of the present invention adopts the atomic layer deposition (ALD) equipment provided by Beneq of Finland for scientific research and industrial application. In the atomic layer deposition method adopted in the present invention, the semiconductor substrate is placed in the atomic layer deposition chamber, and the first precursor gas flows to the substrate in the chamber, thereby effectively forming the first monomolecular layer on the substrate. In the atomic layer deposition chamber, the Under surface microwave plasma conditions, a second precursor gas having a composition different from that of the first precursor gas flows to the first monomolecular layer in the chamber, reacts with the first monomolecular layer, and forms a second monomolecular layer on the substrate , the composition of the second monomolecular layer is different from that of the first monomolecular layer, the second monomolecular layer includes the composition of the first monomolecular layer and the second precursor gas, and continuously repeats the flow of the first and second precursor gas, Instead, a substantial amount of material having the second monolayer composition is formed on the substrate.

The electron beam induced deposition of the present invention is completed by the Helios NanoLab dual-beam system of FEI in the United States. The dual-beam system integrates a high-resolution electron scanning microscope with a high-performance ion beam. The company supplies electron and ion beam microscopes and nano level application equipment.

The present invention uses electron beam induced deposition to prepare Coulomb islands. In the FEI Helios NanoLab dual-beam system, the laminated barrier layer, electrode, substrate and base are placed, and the electron beam is carried out under predetermined electron beam voltage, current and deposition rate. Induced deposition to prepare Coulomb islands on the barrier layer and between the source and drain.

Compared with the prior art, the beneficial effect of the present invention is that: the present invention can precisely control the size of the barrier between the Coulomb island and the electrode by using the atomic layer deposition, and can precisely control the size, position and arrangement of the Coulomb island deposition by using the electron beam induced deposition. Cloth way. The invention solves the problem of uncontrollable potential barrier size and Coulomb island positioning and assembly in the preparation process of the single electron transistor, significantly reduces the difficulty of preparation of the single electron transistor, and improves the consistency of performance of the single electron transistor prepared in batches.

Description of drawings

Fig. 1 is a three-dimensional schematic diagram of a room temperature single electron transistor in a specific embodiment of the present invention;

Fig. 2 is a schematic cross-sectional structure diagram of a room temperature single-electron transistor shown in Fig. 1;

Fig. 3 is the scanning electron micrograph of the source, drain and gate three electrodes of room temperature single electron transistor shown in Fig. 1;

Fig. 4 is an optical micrograph of the source, drain and gate of the room-temperature single-electron transistor shown in Fig. 1 and the external connection.

Explanation of reference signs:

1—gate, 2—source, 3—base, 4—coulomb island, 5—barrier layer, 6—drain, 7—substrate, 8—covering layer, 9—leading platform connected to source, 10—the lead platform connected to the drain, 11—the lead platform connected to the gate.

detailed description

Referring to the accompanying drawings, the present invention precisely controls the thickness of the barrier layer through the atomic layer deposition technology, and uses the electron beam induced deposition technology to precisely control the positioning of the Coulomb island, and prepares a room-temperature single-electron transistor.

As shown in Figures 1 and 2, the room temperature single-electron transistor is mainly composed of source, drain, gate, barrier layer and Coulomb island, which are integrated on the SiO ₂ substrate, which is made of thermally oxidized Si substrate Prepared. The aforementioned Coulomb island is between the source and drain, above the barrier layer, and is completely independent of the source, drain and gate. At the same time, the aforementioned Coulomb islands can be multiple, and the arrangements can be combined arbitrarily. The gate of the aforementioned single-electron transistor is used to regulate the Coulomb island energy level.

The preparation process of the room temperature single-electron transistor is as follows: first, the source 2, the drain 6 and the gate 1 are prepared on the substrate 7 by electron beam direct writing, and then the source 2 and the drain 6 are prepared by atomic layer deposition. A barrier layer 5 is formed on it, and then Coulomb island 4 is prepared between the source electrode 2 and the drain electrode 6 and on the barrier layer 5 by electron beam induced deposition.

Further speaking, the manufacturing process of the present invention includes the following specific steps:

(1) Clean the Si substrate, and then oxidize it in an oxidation furnace at 1000°C for 2 hours to prepare a SiO ₂ insulating layer as a substrate;

(2) Nano-sized source, drain and gate are prepared by electron beam direct writing, electron beam evaporation, metal lift-off and other technologies (as shown in Figure 3), and the minimum line width of the electrode is 25 nm;

(3) Micron-scale wires and lead tables (as shown in Figure 4) respectively connected to the source, drain and gate are prepared by ultraviolet lithography, electron beam evaporation, metal lift-off and other technologies, which are used to transition the device to For macroscopic circuits, the minimum line width of the electrode is 2 μm;

(4) Coat a layer of AZ5214 photoresist on the sample, and after pre-baking, use a UV lithography machine to perform G-line exposure, and then use the immersion method to develop to form a connecting part centered on the source, drain and gate , a mask pattern with a size of 2×2 μm;

(5) A barrier layer was prepared on the source and drain using an atomic layer deposition system, the substrate temperature was controlled at about 80 °C, and the thickness of the barrier layer deposition was about 2 nm;

(6) Use acetone for wet degumming;

(7) Using a dual-beam system, use a scanning electron microscope to precisely adjust the sample position, and then use electron beam-induced assisted deposition to prepare Coulomb islands or Coulomb island arrays between the source and drain electrodes and above the barrier layer, and the scanning electron microscope is magnified Multiple 25W×, electron beam voltage 30kV, beam current 70pA;

(8) Coat a layer of AZ5214 photoresist on the sample, and after pre-baking, use a UV lithography machine for G-line exposure, and then use the immersion method to develop, and form a Coulomb island in the area other than the Pad used for lead packaging A mask pattern with a center and a size of 2×2 μm;

(9) Prepare a 100 nm thick SiO ₂ capping layer on the source, drain, gate and Coulomb island by electron beam evaporation and other techniques;

(10) Use acetone for wet degumming;

(11) Coat a layer of AZ5214 photoresist on the sample as a protective layer during the scribing process;

(12) Use a grinding wheel dicing machine to cut the wafer with the device structure into small pieces, then clean and remove the glue;

(13) Use a wire machine to perform gold wire ball bonding, and package the device on the tube base to complete the preparation of the room temperature single-electron transistor.

In summary, the present invention solves the problem of precisely controlling the size of the barrier between the Coulomb island and the electrode and the assembly and positioning of the Coulomb island by using technologies such as atomic layer deposition and electron beam induced deposition, thereby providing a high-efficiency, batch-fabricated room temperature single-electron transistor A new method is provided.

Claims (1)

1. A method for preparing room temperature single-electron transistors, characterized in that the specific manufacturing process comprises the following specific steps: (1) Clean the Si substrate, and then oxidize it in an oxidation furnace at 1000°C for 2 hours to prepare a SiO ₂ insulating layer as a substrate; (2) Using electron beam direct writing, electron beam evaporation, and metal lift-off techniques to complete the preparation of nanometer-sized source, drain, and gate electrodes, the minimum line width of the electrodes is 25 nm; (3) Micron-scale wires and lead tables connected to the source, drain, and gate are prepared by ultraviolet lithography, electron beam evaporation, and metal lift-off techniques, which are used to transition the device to a macroscopic circuit. The minimum line width of the electrode is is 2 μm; (4) Coat a layer of AZ5214 photoresist on the sample, and after pre-baking, use a UV lithography machine to perform G-line exposure, and then use the immersion method to develop to form a connecting part centered on the source, drain and gate , a mask pattern with a size of 2×2 μm; (5) A barrier layer was prepared on the source and drain electrodes using an atomic layer deposition system, the substrate temperature was controlled at 80 °C, and the thickness of the barrier layer deposition was 2 nm; (6) Use acetone for wet degumming; (7) Using a dual-beam system, use a scanning electron microscope to precisely adjust the sample position, and then use electron beam-induced assisted deposition to prepare Coulomb islands or Coulomb island arrays between the source and drain electrodes and above the barrier layer, and the scanning electron microscope is magnified Multiple 25W×, electron beam voltage 30kV, beam current 70pA; (8) Coat a layer of AZ5214 photoresist on the sample, and after pre-baking, use a UV lithography machine for G-line exposure, and then use the immersion method to develop, and form a Coulomb island in the area other than the Pad used for lead packaging A mask pattern with a center and a size of 2×2 μm; (9) Prepare a 100 nm-thick SiO ₂ capping layer on the source, drain, gate, and Coulomb islands by electron beam evaporation; (10) Use acetone for wet degumming; (11) Coat a layer of AZ5214 photoresist on the sample as a protective layer during the scribing process; (12) Use a grinding wheel dicing machine to cut the wafer with the device structure into small pieces, then clean and remove the glue; (13) Use a wire machine to perform gold wire ball bonding, and package the device on the tube base to complete the preparation of the room temperature single-electron transistor.