CN102891083A - Method for preparing room temperature single-electron transistor - Google Patents
Method for preparing room temperature single-electron transistor Download PDFInfo
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Abstract
一种制备室温单电子晶体管的方法，以源极、漏极栅极、势垒层和库仑岛为基本结构，覆盖层、库仑岛、势垒层、电极、衬底和基底由上到下依次层叠；源极和漏极之上或者源极、漏极和栅极之上的势垒层利用原子层沉积系统来制备，用于形成电极与库仑岛之间电子隧穿的势垒；库仑岛利用双束系统的电子束诱导沉积来制备，其尺寸、数量和排布具有可控性。本发明精确控制势垒层厚度，精确控制库仑岛的组装定位，显著降低了单电子晶体管制备难度，改善了批量制备单电子晶体管性能的一致性。
A method for preparing a room-temperature single-electron transistor, with source, drain gate, barrier layer and Coulomb island as the basic structure, covering layer, Coulomb island, barrier layer, electrode, substrate and base in sequence from top to bottom Stacking; the barrier layer on the source and drain or on the source, drain and gate is prepared using an atomic layer deposition system to form a barrier for electron tunneling between the electrode and the Coulomb island; Coulomb island Prepared by electron beam-induced deposition of a dual-beam system, its size, quantity and arrangement are controllable. The invention precisely controls the thickness of the potential barrier layer, precisely controls the assembly and positioning of the Coulomb island, significantly reduces the difficulty of preparing the single-electron transistor, and improves the consistency of the performance of the batch-fabricated single-electron transistor.
Description
Technical field
The present invention relates to the nano electron device technical field, particularly a kind of method that adopts ald and e-beam induced deposition technology to prepare single electron transistor at room temperature.
Background technology
The characteristic size of the integrated circuit take MOSFET device as main flow has developed into nanometer scale, and application is restricted, and the electronic logic device of further researching and developing new nano-scale becomes growth requirement.But the advantages such as size is little, large-scale integrated low in energy consumption that single-electronic transistor has are with a wide range of applications, and can be used for the types of applications fields such as computer, transducer, detector.Typical single-electronic transistor is comprised of source electrode, drain electrode, grid and a coulomb island, is based on the nano electron device of coulomb blockade effect and single electron tunneling effect.
1987, the people such as the Fulton of Bell Laboratory adopt mask technique prepared size approximately the aluminium quantum dot of 30 nm under the ultralow temperature of 1.7 K, observed the single electron phenomenon for a coulomb island.1989, the Scott-Thomas of MIT etc. adopt the method for X-ray lithography, done a narrow electron channel with gap electrode on the silicon inversion layer, wide approximately 30 nm, length are 1 to 10 μ m, and the electricity of discovery passage is led with electrode voltage and presented periodic vibration under 400 mK.Adopt microelectronic technique, a lot of research groups have prepared the single-electronic transistor of working under low temperature and the room temperature.Simultaneously, people have also carried out single-electronic transistor preparation research from bottom to top.Nineteen ninety-five, Chen etc. have prepared the AuPd nano particle of size 2 to 3 nm, show significant coulomb blockade effect with this single-electronic transistor that makes up under 77 K temperature, even at room temperature also can observe nonlinear voltage-current characteristic.1996, Klein etc. adopted size approximately Au nano particle and the CdSe nano particle of 5.8 nm, had observed clearly coulomb step curve under temperature 77 K.After this, a lot of research groups utilize approach from bottom to top to prepare single-electronic transistor, have at room temperature observed the single electron phenomenon.
Yet existing single-electronic transistor prepares three key technical problems of ubiquity: the controlled preparation on small size coulomb island; The controlled location assembling on coulomb island; The accurate control of tunneling barrier size between coulomb island and the electrode.This is related to the working temperature of device and the consistency of performance thereof.Therefore, the researcher thirsts for always for a long time that development is a kind of can accurately control coulomb island size and a location, and the preparation method of potential barrier size between control coulomb island and the electrode, with preparation and the application that significantly promotes single-electronic transistor.
Summary of the invention
Technical problem to be solved by this invention is: solve the problem that above-mentioned prior art exists, and a kind of method for preparing single electron transistor at room temperature is proposed, accurately control barrier layer thickness, accurately the assembling on control coulomb island is located, significantly reduce single-electronic transistor and prepare difficulty, improve the consistency for preparing in batches the single-electronic transistor performance.
The technical solution used in the present invention is: single electron transistor at room temperature, and take source electrode, drain electrode, grid, barrier layer and coulomb island as basic structure, cover layer, coulomb island, barrier layer, electrode, substrate and substrate stack gradually from top to bottom; On source electrode and the drain electrode or the barrier layer on the source electrode, drain and gate utilize atomic layer deposition system to prepare, be used to form the potential barrier of electron tunneling between electrode and the coulomb island; Coulomb island utilizes the e-beam induced deposition of electrons/ions double-beam system to prepare, its size, quantity and arrange and have controllability.
In the technique scheme, described substrate is prepared from by oxidation Si substrate, source electrode, drain electrode, grid, barrier layer and coulomb integrated SiO that is arranged in island
2On the substrate, a coulomb island is located between source electrode and the drain electrode, on the barrier layer, and is totally independent of source electrode, drain and gate; The coulomb island can be a plurality of, the arrangement mode combination in any, and grid is used for a regulation and control coulomb island energy level.
In the technique scheme, the preparation process of single electron transistor at room temperature is as follows: at first pass through electron-beam direct writing, prepare source electrode, drain and gate at substrate, then utilize the normal optical lithography to prepare the micron-sized lead-in wire electrode that links to each other with source electrode, drain and gate respectively, then utilize ald, form barrier layer on source electrode and drain electrode, the recycling e-beam induced deposition is preparation coulomb island between source electrode and drain electrode and on the barrier layer.
In the technique scheme, 200 to the 500 nms thick SiO of described substrate for forming by thermal oxidation Si sheet
2Insulating barrier is positioned on the Si substrate.
In the technique scheme, described source electrode, drain and gate adopt electron beam exposure and the preparation of electron beam evaporation deposition technology, and adopting Ti is the metal adhesion layer, and thickness is 2 to 5 nm, and employing Au is deposition materials, and thickness is 3 to 25 nm.
In the technique scheme, has the distance of 5 to 15 nm between described source electrode and the drain electrode.
In the technique scheme, the spacing of described grid and source electrode and drain electrode has 1 to 5 times of distance of leaking spacing to the source.
In the technique scheme, described barrier layer adopts technique for atomic layer deposition, is deposited on source electrode and the drain electrode, and its thickness is 2 to 5 nm, and thickness is accurately controlled.
In the technique scheme, described barrier layer is selected Al
2O
3Or SiO
2Deng material.
In the technique scheme, the e-beam induced deposition technology is adopted on described coulomb of island, is deposited between source electrode and the drain electrode, and on the barrier layer, a coulomb island diameter is 5 to 15 nm.
In the technique scheme, described coulomb island between source electrode and drain electrode, the size, quantity and the arrangement mode that deposit on the barrier layer can accurately control.
In the technique scheme, the deposition materials such as Cu, Au, Al or W are selected on described coulomb of island.
In the technique scheme, described cover layer adopts ald, thermal evaporation or sputtering sedimentation on source electrode, drain electrode, grid and coulomb island.
In the technique scheme, described cover layer is selected Al
2O
3Or SiO
2Deng material, thickness is 10 to 100 nm.
Electron beam exposure system of the present invention, ultraviolet photolithographic system, electron beam evaporation deposition system, atomic layer deposition system are known maturation process technology, and the e-beam induced deposition of the electrons/ions double-beam system that adopts also is general known maturation process technology.
The concrete step (2) asked for an interview in " the embodiment "～step (9) of using.
Electron beam exposure system of the present invention adopts the JBX5500ZA electron beam exposure apparatus of NEC; Ultraviolet photolithographic of the present invention system adopts the SUSS MA/BA6 mask aligner of German SUSS MicroTec company; Electron beam evaporation deposition of the present invention system adopts the high vacuum evaporation coating system ei-5z of Japanese ULVAC company.
Ald (ALD) equipment that is used for scientific research and commercial Application that atomic layer deposition system of the present invention adopts Finland's times Nike (Beneq) to provide.It is indoor that the Atomic layer deposition method that the present invention adopts is arranged on ald with semiconductor base, make the first precursor gas flow to described indoor substrate, thereby effectively form the first monolayer in substrate, indoor at ald, under surperficial microwave plasma condition, make second precursor gas different from the first precursor gas composition flow to the first indoor monolayer, with described the first monolayer reaction, and in described substrate formation the second monolayer, the second monolayer is different from the composition of the first monolayer, the second monolayer comprises the composition of the first monolayer and described the second precursor gas, and repeat continuously first, flowing of the second precursor gas has the material that the second monolayer forms in a large number and effectively form in substrate.
E-beam induced deposition of the present invention adopts the Helios NanoLab double-beam system of U.S. FEI to finish, electronic scanner microscope and high-performance ion beam that this double-beam system is high with resolution combine, the said firm's supplies electrons and ion cluster microscope and nanoscale application apparatus.
The present invention adopts e-beam induced deposition preparation coulomb island, in FEI Helios NanoLab double-beam system, place stacked barrier layer, electrode, substrate and substrate, under predetermined electron-beam voltage, electric current, deposition rate, carry out e-beam induced deposition, on a preparation coulomb island on the barrier layer and between the source electrode, drain electrode.
Compared with prior art, beneficial effect of the present invention is: the present invention adopts ald can accurately control the size of potential barrier between coulomb island and electrode, utilizes e-beam induced deposition can accurately control coulomb size, position and the arrangement mode of island deposition.The invention solves in the single-electronic transistor preparation process, uncontrollable problem is assembled in potential barrier size and a coulomb location, island, has significantly reduced the difficulty of single-electronic transistor preparation, improves the consistency for preparing in batches the single-electronic transistor performance.
Description of drawings
Fig. 1 is the schematic three dimensional views of a kind of single electron transistor at room temperature in the specific embodiment of the invention;
Fig. 2 is the cross-sectional view of single electron transistor at room temperature shown in Figure 1;
Fig. 3 is the three electrode scanning electron microscope (SEM) photograph of source, leakage and grid of single electron transistor at room temperature shown in Figure 1;
Fig. 4 is source, leakage and the grid of single electron transistor at room temperature shown in Figure 1 and the microelectrode light micrograph of external relation.
Description of reference numerals:
1-grid, 2-source electrode, 3-substrate, 4-coulomb island, 5-barrier layer, 6-drain electrode, 7-substrate, 8-cover layer, the 9-lead-in wire platform that links to each other with source electrode, 10-with the lead-in wire platform that drains and link to each other, the 11-lead-in wire platform that links to each other with grid.
Embodiment
Referring to accompanying drawing, the present invention accurately controls barrier layer thickness by technique for atomic layer deposition, and utilizes the e-beam induced deposition technology that location, coulomb island is accurately controlled, and prepares single electron transistor at room temperature.
Shown in Fig. 1～2, this single electron transistor at room temperature mainly forms the integrated SiO that is arranged on by source electrode, drain electrode, grid, barrier layer and a coulomb island
2On the substrate, this substrate is prepared from by thermal oxidation Si substrate.Aforementioned coulomb island and is totally independent of source electrode, drain and gate between source electrode and drain electrode, on the barrier layer.Simultaneously, aforementioned coulomb island can be a plurality of, but the arrangement mode combination in any.The grid of aforementioned single-electronic transistor is used for regulation and control coulomb island energy level.
The preparation process of this single electron transistor at room temperature is as follows: at first pass through electron-beam direct writing, prepare source electrode 2, drain electrode 6 and grid 1 at substrate 7, then utilize ald, on source electrode 2 and drain electrode 6, form barrier layer 5, then utilize e-beam induced deposition at source electrode 2 and drain between 6, on the barrier layer 5, preparation coulomb island 4.
Further say, manufacture craft of the present invention comprises following concrete steps:
(1) cleans the Si substrate, then oxidation 2 hours under 1000 ° of C conditions in oxidation furnace, preparation SiO
2Insulating barrier is as substrate;
(2) adopt the technology such as electron-beam direct writing, electron beam evaporation, metal-stripping to finish the source electrode of nano-scale, the preparation of drain and gate (as shown in Figure 3), the electrode minimum feature is 25 nm;
(3) prepare respectively micron order wire and lead-in wire platform (as shown in Figure 4) with source electrode, drain and gate UNICOM by technology such as ultraviolet photolithographic, electron beam evaporation, metal-strippings, be used for device is transitioned into macroscopical circuit, this electrode minimum feature is 2 μ m;
(4) apply one deck AZ5214 photoresist at sample, after the front baking, use the ultraviolet photolithographic machine to carry out the G line exposing, the recycling immersion method develops, and forms centered by the connecting portion of source electrode, drain and gate, size is the mask pattern of 2 * 2 μ m;
(5) use atomic layer deposition system to prepare barrier layer on source electrode and drain electrode, substrate temperature is controlled at about 80 ° of C, and the thickness of barrier layer deposition is 2 nm approximately;
(6) utilizing acetone to carry out wet method removes photoresist;
(7) use double-beam system, utilize scanning electron microscopy accurate adjustment sample position, then by the electron beam-induced assistant depositing, between source electrode and drain electrode, preparation coulomb island or coulomb island array on the barrier layer, ESEM multiplication factor 25W *, electron-beam voltage 30kV, line 70pA;
(8) apply one deck AZ5214 photoresist at sample, after the front baking, use the ultraviolet photolithographic machine to carry out the G line exposing, the recycling immersion method develops, zone being used for beyond the Pad of lead packages forms centered by the coulomb island, size is the mask pattern of 2 * 2 μ m;
(9) SiO by the technology such as electron beam evaporation preparation 100 nm thickness on source electrode, drain electrode, grid and coulomb island
2Cover layer;
(10) utilizing acetone to carry out wet method removes photoresist;
(11) apply one deck AZ5214 photoresist at sample, as the protective layer in the scribing processes;
(12) use sand-wheel slice cutting machine, the wafer of carrying out device architecture is cut into fritter, then clean, remove photoresist;
(13) use wiring machine to carry out gold ball bonding, device package on base, is finished the preparation of this single electron transistor at room temperature.
In sum, the present invention is by adopting the technology such as ald and e-beam induced deposition, solved the problem of potential barrier size between accurate control coulomb island and electrode and coulomb assembling location, island, thus for efficient, preparing single electron transistor at room temperature provides a kind of new method in batches.
Claims (10)
1. method for preparing single electron transistor at room temperature is characterized in that: take source electrode, drain electrode, grid, barrier layer and coulomb island as basic structure, cover layer, coulomb island, barrier layer, electrode, substrate and substrate stack gradually from top to bottom; On source electrode and the drain electrode or the barrier layer on the source electrode, drain and gate utilize atomic layer deposition system to prepare, be used to form the potential barrier of electron tunneling between electrode and the coulomb island; Coulomb island utilizes the e-beam induced deposition of double-beam system to prepare, its size, quantity and arrange and have controllability.
2. the method for preparing single electron transistor at room temperature according to claim 1, it is characterized in that: described substrate is prepared from by oxidation Si substrate, source electrode, drain electrode, grid, barrier layer and coulomb integrated SiO that is arranged in island
2On the substrate, a coulomb island is located between source electrode and the drain electrode, on the barrier layer, and is totally independent of source electrode, drain and gate; The coulomb island can be a plurality of, the arrangement mode combination in any, and grid is used for a regulation and control coulomb island energy level.
3. the method for preparing single electron transistor at room temperature according to claim 1, it is characterized in that: the preparation process of single electron transistor at room temperature is as follows: at first pass through electron-beam direct writing, prepare source electrode, drain and gate at substrate, then utilize the normal optical lithography to prepare the micron-sized lead-in wire electrode that links to each other with source electrode, drain and gate respectively, then utilize ald, form barrier layer on source electrode and drain electrode, the recycling e-beam induced deposition is preparation coulomb island between source electrode and drain electrode and on the barrier layer.
4. the method for preparing single electron transistor at room temperature according to claim 1 is characterized in that: 200 to the 500 nms thick SiO of described substrate for forming by thermal oxidation Si sheet
2Insulating barrier is positioned on the Si substrate, and described source electrode, drain and gate adopt electron beam exposure and the preparation of electron beam evaporation deposition deposition technique, and adopting Ti is the metal adhesion layer, and thickness is 2 to 5 nm, and employing Au is deposition materials, and thickness is 3 to 25 nm.
5. the method for preparing single electron transistor at room temperature according to claim 1 is characterized in that: have the distance of 5 to 15 nm between described source electrode and the drain electrode, the spacing of described grid and source electrode and drain electrode has 1 to 5 times to the distance of source leakage spacing.
6. the method for preparing single electron transistor at room temperature according to claim 1 is characterized in that: described barrier layer adopts technique for atomic layer deposition, is deposited on source electrode and the drain electrode, and its thickness is 2 to 5 nm, and thickness is accurately controlled.
7. the method for preparing single electron transistor at room temperature according to claim 1, it is characterized in that: described barrier layer is selected Al
2O
3Or SiO
2Deng material.
8. the method for preparing single electron transistor at room temperature according to claim 1 is characterized in that: the e-beam induced deposition technology is adopted on described coulomb of island, is deposited between source electrode and the drain electrode, and on the barrier layer, a coulomb island diameter is 5 to 15 nm.
9. the method for preparing single electron transistor at room temperature according to claim 1 is characterized in that: the deposition materials such as Cu, Au, Al or W are selected on described coulomb of island.
10. the method for preparing single electron transistor at room temperature according to claim 1, it is characterized in that: described cover layer is selected Al
2O
3Or SiO
2Deng material, thickness is 10 to 100 nm.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105502276A (en) * | 2016-01-06 | 2016-04-20 | 中国科学院物理研究所 | Method for preparing test electrodes on microparticles |
| CN106383163A (en) * | 2016-10-19 | 2017-02-08 | 中国人民解放军国防科学技术大学 | Ionizing gas sensor based on single electron transistor and preparation method thereof |
| CN106935501A (en) * | 2016-10-19 | 2017-07-07 | 中国人民解放军国防科学技术大学 | A kind of method that PS microsphere templates assembling gold grain prepares single-electronic transistor |
| CN109894162A (en) * | 2019-03-11 | 2019-06-18 | 太原理工大学 | A kind of micro-fluidic chip and preparation method thereof based on PEDOT:PSS electrochemical transistor |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105502276A (en) * | 2016-01-06 | 2016-04-20 | 中国科学院物理研究所 | Method for preparing test electrodes on microparticles |
| CN106383163A (en) * | 2016-10-19 | 2017-02-08 | 中国人民解放军国防科学技术大学 | Ionizing gas sensor based on single electron transistor and preparation method thereof |
| CN106935501A (en) * | 2016-10-19 | 2017-07-07 | 中国人民解放军国防科学技术大学 | A kind of method that PS microsphere templates assembling gold grain prepares single-electronic transistor |
| CN106935501B (en) * | 2016-10-19 | 2023-08-22 | 中国人民解放军国防科学技术大学 | A method for preparing single-electron transistors by assembling gold particles with polystyrene microsphere template |
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| CN109894162A (en) * | 2019-03-11 | 2019-06-18 | 太原理工大学 | A kind of micro-fluidic chip and preparation method thereof based on PEDOT:PSS electrochemical transistor |
| CN109894162B (en) * | 2019-03-11 | 2021-06-11 | 太原理工大学 | A PEDOT-based: micro-fluidic chip of PSS electrochemical transistor and preparation method thereof |
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