CN101174637A - A silicon-based single-electron memory with side gate structure and its manufacturing method - Google Patents

Abstract

The invention discloses a silicon-based single-electron memory memory with a side gate structure, which comprises preparing a silicon nanocrystal Coulomb island for storing charges on the top layer silicon of an SOI substrate, and a sensor for detecting the stored charges Conductivity of silicon quantum wires. The silicon nanocrystal Coulomb island is adjacent to the conductance of the silicon quantum wire, and the current is controlled by the floating gate covering the surface. The conductance current of the silicon quantum wire can also be controlled independently by the side gate. Charges enter the Coulomb island of silicon nanocrystals through the silicon nanowire channel. On the silicon nanowire channel, two adjacent nano-metal gates for controlling the entry of a single charge and one nano-metal gate for erasing stored charges are fabricated. The invention also discloses a method for manufacturing a silicon-based single-electron memory storage device with a side gate structure. With the invention, the storage process of each electron depends on the quantum coulomb blocking effect, and the storage charge potential field acts on the signal current through capacitive coupling, thereby detecting the storage information of the single charge.

Description

A silicon-based single-electron memory with side gate structure and its manufacturing method

technical field

The invention relates to the technical field of single-electron memory memory in nanoelectronics, in particular to a silicon-based single-electron memory memory with a side gate structure and a manufacturing method thereof.

Background technique

Nanoelectronics is one of the important fields of nanotechnology, and it is the continuous development and extension of microelectronics to the microscopic field. At present, the feature size of VLSI has entered the nanoscale (<100nm) range, and the impact of quantum effects has become more and more prominent in the process of scaling down CMOS devices. The nano-solid structure produced by single atomic layer thin film epitaxial growth technology, tunnel probe technology and advanced photolithography technology shows peculiar quantum effects. On the basis of these effects, people have invented resonant tunneling devices and single-electron devices. , quantum dot devices and other new quantum devices.

Single-electron devices work by controlling the transport of individual electrons through nanometer-sized Coulomb islands. With the development of nanofabrication technology, scientists have been able to control the size and shape of the Coulomb island, as well as the thickness and shape of the tunnel junction barrier in the nanoscale range.

On the Coulomb island, the size of the electron transport space is reduced to the nanometer level, resulting in a significant enhancement of the quantum confinement effect, and the electrons entering the Coulomb island must tunnel through. The charge potential energy in the Coulomb island will repel the entry of external electrons. If the charge energy required by the electron to enter the Coulomb island is greater than the thermal energy of the environment, the electron will be blocked. The electric field of the gate can modulate the potential of the Coulomb island through capacitive coupling. When the energy level in the Coulomb island is located in the energy window formed by the source-drain electron library Fermi level, the electrons will pass through the Coulomb island with a high penetration rate through the resonant tunneling effect. . In this way, electron momentum changes across Coulomb islands are prominently represented as current peaks with discrete energy level characteristics.

A single electron entering the Coulomb island can be regarded as storing a charge, and flowing out of the Coulomb island can be regarded as releasing a charge. In the process of this single electron going in and out of the Coulomb island, the potential will have a fluctuation of e/Ctt (where Ctt is the entire capacitance of the Coulomb island). Then the single-electron memory memory is a device used to detect the Coulomb potential fluctuation of the Coulomb island caused by the single-electron transport.

Traditional memory is to complete the transmission and storage of information by manipulating the charge flow, while single-electron memory uses the single-electron Coulomb blocking effect to precisely control several or even a single electron to complete the same function. It has the following advantages. First, since the device relies on the repulsion between electrons to achieve its operation, it can work in a small size, making large-scale integration and complex wiring possible. Secondly, it can use a few electrons to complete basic functions, so the energy consumption is very small. If it can be integrated at a high density, its power consumption will be only one hundred thousandth of the current microelectronic transistor circuit. Finally, due to the small size of the device, it only needs a few electrons to tunnel to complete the transmission of a bit of information. Compared with the traditional device that requires about 10 ⁵ electrons to participate in tunneling, its response speed is also quite Fast. These advantages of single-electron memory are exactly what the devices that make up the integrated circuit need to have, and they have good development potential in large-scale and ultra-large-scale integration.

The research in the field of single-electron devices began in 1969 when Lambe and Jaklevic observed electron quantization in a structure similar to a single-electron box (for details, please refer to the literature "Lambe and R.C.Jaklevic," Charge-quantization studies using tunnel capacitor," Phys.Rev.Lerr., vol.22, no.25, pp.1371-1375, June 1969."Recorded content).

Silicon-based single-electron devices rely on the oxidizable characteristics of silicon materials and mature process advantages. In less than ten years, crystalline silicon quantum dots with a diameter of less than 10nm have been obtained to work at room temperature, and most silicon-based The preparation method of single-electron devices can be better compatible with the existing silicon CMOS process, making it possible to prepare large-scale quantum digital integrated circuits.

At present, semiconductor single-electron transistors that can work at room temperature in the world are mainly successfully fabricated on SOI substrates with thin silicon films. Compared with the bulk silicon material, the oxide insulating buried layer of SOI isolates the device from the substrate, reduces the influence of the substrate carrier on the device, reduces the parasitic capacitance effect of the silicon device, and is easy to achieve full dielectric isolation, avoiding the device interaction with the substrate. The silicon film of the SOI substrate used to make single-electron devices is thin enough to make tiny tunnel junctions and quantum dots. With the continuous reduction of transistor size, the advantages of SOI technology become more and more prominent. When the transistor on the thin silicon film is turned on, the interface of the buried oxide layer is in a depleted state, and the silicon film is completely depleted. With radiation resistance, high temperature resistance, low electric field, high transconductance, good short channel and narrow channel characteristics, it is especially suitable for high-speed, low-voltage, low-power circuit applications.

By 1993, the first single-electron memory that can observe single-electron storage at room temperature was successfully developed by Yano and Ishii et al. (For details, please refer to the literature "K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F.Murai, and K.Seki, "Room-temperaturesingle-electron memory using fine-grain polycrystalline silicon," in Proc.IEEEInt.Electron Devices Meeting, 1993, pp.541-545."), single electron The application prospect of memory has just emerged. However, just realizing single-electron storage at room temperature does not mean that it can be applied in practice. To realize the application of single-electron storage, there are still many problems to be solved, such as: process compatibility, programming speed, storage time, etc. , in recent years, scientists have done a lot of work on improving the performance of single-electron memories. Several typical single-electron memory designs are listed below:

(1) Single-electron memory with a floating gate structure

As shown in Figure 1, Figure 1 is a schematic structural diagram of a single-electron memory with a floating gate structure in the prior art (for details, please refer to the literature "Shin-ichi O'UCHI, Takeshi TSUBOKURA, Takuro TAJIMA, Shuhei AMAKAWA, Minoru FUJISHIMA1 and KoichiroHOH1, "Charging and Retention Times in Silicon-Floating-Dot-Single-Electron Memory, "Jpn.J.Appl.Phys.Vol.40(2001)pp.2041-2045."Recorded content). It is to put quantum dots or quantum dot arrays capable of storing charges between the channel and the gate of an ordinary MOSFET. The quantum dots and the channel are separated by a thin layer of insulating medium, and electrons enter and exit the quantum dots by tunneling. , due to the large charge Coulomb energy, the number of charges in the quantum dot can be controlled by the gate voltage. The corresponding channel current can be controlled by using different potentials on the quantum dots, so as to affect the magnitude of the channel current. In this way, different states of the device can be known by measuring this current.

(2) Single-electron memories with granular thin films as tunnel junctions

As shown in FIG. 2 , FIG. 2 is a schematic diagram of a single-electron memory structure using a granular thin film as a tunnel junction in the prior art. It is a design proposed by Yano et al. For details, please refer to the literature "K.Yano, T.Ishii, T.Sano, T.Mine, F.Murai, and K.Seki,"Singleelectron-memory integrated circuit for giga-to-tera bit storage, "IEEE Int. Solid-State Circuits Conf., 1996, pp.266-267." This design follows three main principles: it can work at room temperature; it can effectively suppress the influence of background charges; and it can be fabricated using existing processes. Its working principle is similar to that of single-electron memory with a floating gate structure, which uses the storage state of the charge in the storage point to control the current between the source and drain. Under a certain bias voltage, charges are confined in the film, thereby modulating the magnitude of the current flowing through the film. In terms of suppressing the influence of background charges, when there is no background charge, if the applied gate voltage is small, there is no conduction channel in the film due to the Coulomb blocking effect. When the gate voltage increases above the threshold voltage, the channel turns on and charges flow. In the presence of background charge, the Coulomb blockade effect in some regions disappears, while the effect in other regions increases. When there is not enough bias voltage, the overall performance is still no channel conduction. Since the storage point of its charge and the current path modulated by the storage point are all on the same granular film, it is not easy to adjust the working state of the device independently.

(3) Single-electron memory with side gate structure

As shown in Figure 3, Figure 3 is a schematic structural view of a single-electron memory of a quasi-one-dimensional quantum dot array in the prior art (for details, please refer to the literature "A.Dutta, S.P.Lee, S.Hatatani, and S.Oda, "Silicon -based single-electron memory using a multiple-tunnel junction fabricated by electron-beam direct writing "Appl. Phys. Lett.75, 1422 (1999)." Recorded content). This is a device with a two-dimensional planar structure, which is conducive to simplifying the preparation process. The quasi-one-dimensional quantum dot array acts as a multi-tunnel junction, which can provide a high Coulomb blockade energy gap to suppress background charge fluctuations. Under a certain gate voltage, electrons flow into or out of the storage node through the multi-tunnel junction, and the distribution of stored electrons in the multi-tunnel junction will be controlled by the Coulomb blocking effect. The readout process is realized by using a single-electron transistor, and the charging charge potential on the storage node can affect the energy level state of the single-electron transistor quantum dot through capacitive coupling, and then affect the conductance current flowing through the single-electron transistor.

The nanotechnology process of single-electron memories with side-gate structures is the most challenging. If it can work at room temperature, it will be of great significance to the development and application of single-electron logic circuits. In 1994, Nakazato et al. produced the first experimental multi-junction single-electron memory on doped GaAs material (for details, please refer to the literature "K Nakazato, R J Blaikie, H Ahmed et al, "Single-electron memory", J.Appl.Phys.75(10), 1994, p.5123."Recorded content). In 1995, Likharev et al. proposed a multi-junction single-electron memory model independent of random background charge (for details, please refer to the literature "K Likharev A Korotokov, "Analysis of Q0-independent single-electron systems", in Int.Workshop Computational Electronics, 1995, p.42 .” content recorded). In 1998, the Ahmed group produced a multi-junction single electronic RAM memory working at a temperature of 4.2K on SOI materials (for details, please refer to the document "NJ Stone, H Ahmed, "Silicon single electron memory cell", Appl.Phys.Lett.73( 15), 1998, p.2134." recorded content). In 1999, the Oda group prepared a multi-junction single-electron memory working at 20K temperature on the SIMOX material (for details, please refer to the literature "A Dutta, S P Lee, S Hatatani, et al, "Silicon-based single-electron memory using multiple- tunnel junction fabricated by electron-beam direct writing”, Appl.Phys.Lett.75(10), 1999, p.1422.”Recorded content). In 2000, the Ahmed group realized a single-electron multi-tunnel junction gate and CMOS integrated memory device working at a temperature of 65K (for details, please refer to the literature "Z A K Durrani, A C Irvine, H Ahmed," Coulomb blockade memory using integrated single-electron transistor/ metal-oxide-semiconductortransistor gain cells", IEEE Electron devices, 47(12), 2000, p.2334."Recorded content). In 2002, Nakajima et al. studied the conductance mechanism of multi-tunnel junction single-electron transistors (for details, please refer to the literature "A. Nakajima, Yuhei Ito, S Yokoyama, "Conduction mechanism of Si single-electron transistor having a one-dimensional regular array of multiple tunnel junctions" , Appl.Phys.Lett.81(4), 2002, p.733."Recorded content). In 2004, Amakawa reviewed the logic of multi-tunnel junction electronic devices (for details, please refer to the literature "S Amakawa, et al, "Single-electron logic based on multiple-tunnel junctions", Mesoscopic Tunneling Devices, Ed.HiroshiNakashima, 2004: ISBN: 81 -271-0007-2." as recorded).

In recent years, my country has also carried out research work on silicon-based single-electron devices on SOI substrates. The Institute of Physics of the Chinese Academy of Sciences has carried out the design of single-electron transistors with various structures, and developed a silicon-based single-electron transistor at a temperature of 90K (for details, please refer to the literature "T.H.Wang, H.W.Li and J.M.Zhou, Si single-electron transistors with in -plane point-contact metal gates, Appl. Phys. Lett.78, 2160 (2001)."Recorded content). Xi'an University of Technology and Hong Kong University of Science and Technology cooperated with electron beam lithography and reactive ion etching to manufacture silicon single-electron transistors on p-type SIMOX, which can work at low temperatures at 77K (for details, please refer to the literature "G.Lu , Z.M.Chen, J.N.Wang, W.K.Ge.Fabrication and characteristics of aSi-based single electron transistor, Chinese J.Semiconductors, 23(3), 246(2002).”Recorded content). Nanjing University has carried out research on room-temperature silicon-based multi-quantum dot memory based on single-electron effect (for details, please refer to the literature "Huang Xinfan, Room-temperature silicon-based multi-quantum dot memory based on single-electron effect, National Natural Science Foundation of China Project No. 60471021, Nanjing University" recorded content).

The working principle of single-electron devices relies on the Coulomb blocking effect based on the Coulomb repulsion between electrons. Sub-10nm structures are required for single-electron devices operating at room temperature to achieve Coulomb energy to overcome ambient thermal noise. Nanocrystalline silicon particles can replace the floating gate of memory devices. The stored charge distributed on the floating gate shows several attractive characteristics, such as faster write time and lower temperature compared with EEPROM, Compared with flash memory, it has better durability and the like. Of course, there are a number of major challenges that need to be overcome before commercial production of single-electron memories is possible. Various single-electron storage system structures are also under development, such as single-electron transistor flip-flops, single-electron trap memories, single-electron transistor ring memories, random background charge-independent memories, and single/multi-island memories, etc. (For details, please refer to literature "C.Wasshuber, H.Kosina, S.Selberherr, A comparative study of single-electron memories, IEEE TransElectron.Devices, 45(11), 1998, p.2365."Recorded content).

The single-electron counting system mainly utilizes the principle of the single-electron rotating gate. By applying a gate voltage with frequency f changing on the double potential barrier of the single-electron transistor, by increasing the gate voltage to exceed a certain threshold, an electron is randomly drawn from the source electrode. Pulling it into the central Coulomb island, and then lowering the gate voltage, electrons can be pushed out of the central Coulomb island. This kind of turnstile (turnstile) control gate generates a ladder-shaped current ef, as if the voltage turns out an electron every time it rotates. , exhibiting a single-electron transport state. Due to the extremely small capacitance of the Coulomb island, the charging and discharging time of the capacitor is extremely short, and the switching speed of the device is extremely fast. In 2003, six metrology laboratories participating in the European COUNT program and Chalmers University jointly published the initial research results on the measurement of electron flow to achieve quantum standards (for details, please refer to the literature "H.E. Van den Brom, O. Kerkhof et al, Counting electrons one by one-overview of a joint European research project, IEEE trans.Instrum.Meas., 52(2), 2003, p.584."Recorded content). The purpose of the COUNT project is to solve and develop basic instruments and measurement standards for measuring electron currents less than 1nA. Single-electron devices provide the means to manipulate and probe the transport behavior of individual electrons with high precision. COUNT plans to use two complementary single-electron tunneling devices, one of which is used for a single-electron pump to provide a current source. A single electron can be stored on the Coulomb island for a long time, and the transport behavior of the electron can be controlled by the gate voltage; the other A single-electron counter is used as an ammeter, which detects the transmission of every electron.

In conclusion, the transport behavior of single electrons can be effectively manipulated by exploiting the Coulomb blocking effect and resonant tunneling effect of single electron devices. Single-electron memory and its charge counting detection system have great potential in the fields of mass data storage, quantum signal detection, and quantum logic circuits.

Contents of the invention

(1) Technical problems to be solved

In view of this, an object of the present invention is to provide a silicon-based single-electron memory with a side gate structure, so that the storage process of each electron depends on the quantum coulomb blocking effect, and the stored charge potential field acts on the Signal current, thereby detecting the stored information of a single charge.

Another object of the present invention is to provide a method for fabricating a silicon-based single-electron memory with a side-gate structure, so that the storage process of each electron depends on the quantum Coulomb blocking effect, and the potential field of the stored charge acts on the signal through capacitive coupling. current, thereby detecting the stored information of a single charge.

(2) Technical solution

In order to achieve the above-mentioned purpose, the present invention provides a silicon-based single-electron memory with a side gate structure, the silicon-based single-electron memory includes:

Silicon-on-insulator (SOI) substrates;

Silicon nanoconductance thin wire 5 and silicon quantum wire 14 made of top layer silicon on the SOI substrate, the silicon nanoconductance thin wire 5 and silicon quantum wire 14 are parallel to each other, and silicon quantum wire 14 is used to detect silicon nanocrystal The stored charge in the Coulomb island 6, the stored charge enters the silicon nanocrystal Coulomb island 6 through the silicon nanoconductance thin wire 5;

A silicon nanocrystal Coulomb island 6 for storing charges located in the middle of the silicon nanoconductance thin wire 5 and connected to the silicon nanoconductance thin wire 5;

A first ohmic contact conductance step 3 and a second ohmic contact conductance step 4 located at both ends of the silicon nanoconductance thin wire 5 and connected to the silicon nanoconductance thin wire 5;

The first source metal electrode 7 located on the first ohmic contact conductance step 3 and the first drain metal electrode 8 located on the second ohmic contact conductance step 4;

The first fence nano-electrode 9, the second fence nano-electrode 10 and the third fence nano-electrode 11 on the silicon nano-conductance thin wire 5 on both sides of the silicon nanocrystal Coulomb island 6, the first fence nano-electrode 9 Located on the same side of the silicon nanocrystal Coulomb island 6 as the second fence nano-electrode 10, the third fence nano-electrode 11 is located on the other side of the silicon nanocrystal Coulomb island 6;

A third ohmic contact conductance step 15 and a fourth ohmic contact conductance step 16 located on the other side of the silicon quantum wire 14 relative to the silicon nanoconductance thin wire 5 and connected to the silicon quantum wire 14;

The second source metal electrode 19 located on the third ohmic contact conductance step 15 and the second drain metal electrode 20 located on the fourth ohmic contact conductance step 16;

The fifth ohmic contact conductance step located on the same side of the silicon quantum wire 14 relative to the third ohmic contact conductance step 15 and the fourth ohmic contact conductance step 16 and between the third ohmic contact conductance step 15 and the fourth ohmic contact conductance step 16 17;

a metal side gate electrode 18 located on the fifth ohmic contact conductance step 17;

An insulating dielectric layer 12 covering the silicon nanoconductance thin wire 5, the silicon nanocrystal Coulomb island 6, the silicon quantum wire 14, the first fence nano-electrode 9, the second fence nano-electrode 10 and the third fence nano-electrode 11 ;

The surface metal floating gate 13 covering the insulating dielectric layer 12 .

The material used for the silicon nanocrystal Coulomb island 6 is an ultra-thin polysilicon film, which is used to achieve a strong quantum confinement effect on charges at room temperature, and the storage process of each charge depends on the quantum Coulomb blocking effect.

The potential field of the stored charge acts on the signal current passing through the adjacent silicon quantum wire 14 through capacitive coupling, so that the silicon quantum wire 14 obtains the stored information of a single charge.

The signal current is controlled by the metal side gate electrode 18 and/or the surface metal floating gate 13 .

The first ohmic contact conductance step 3, the second ohmic contact conductance step 4, the third ohmic contact conductance step 15, the fourth ohmic contact conductance step 16 and the fifth ohmic contact conductance step 17 are made of the top silicon layer of the SOI substrate made.

The first source metal electrode 7 and the first drain metal electrode 8 are respectively deposited on the first ohmic contact conductance step 3 and the second ohmic contact conductance step 4, and are annealed to realize ohmic contact;

The metal side gate electrode 18 is deposited on the fifth ohmic contact conductance step 17, and is annealed to realize ohmic contact;

The second source metal electrode 19 and the second drain metal electrode 20 are deposited on the third ohmic contact conductance step 15 and the fourth ohmic contact conductance step 16 respectively, and are annealed to realize ohmic contact.

The first surrounding gate nano-electrode 9 and the second surrounding gate nano-electrode 10 are used to control the entry of a single charge into the silicon nanocrystal Coulomb island 6 to realize the controllable storage of a single charge;

The third surrounding gate nano-electrode 11 is used for erasing the charge stored on the silicon nanocrystal Coulomb island 6 .

In order to achieve the above another object, the present invention provides a method for fabricating a silicon-based single-electron memory with a side gate structure, the method comprising:

A. On the silicon oxide insulating layer of the SOI substrate, silicon nanometer conductance thin wires 5, silicon quantum wires 14, first ohmic contact conductance steps 3, second ohmic contact conductance steps 4, third ohmic contact conductance steps 15, The fourth ohmic contact conductance step 16 and the fifth ohmic contact conductance step 17;

B. Use the mask dielectric sleeve to carve out the Coulomb island window connected to the silicon nanoconductance thin line 5, exposing the silicon oxide insulating layer of the SOI substrate;

C, sputtering a thin layer of polycrystalline silicon, chemically etching away the mask medium, and forming a silicon nanocrystal Coulomb island 6 in the Coulomb island window area;

D, deposit and form the first source metal electrode 7, the first drain metal electrode 8, the metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20, and anneal to realize ohmic contact;

E, deposit and form the first fence nano-electrode 9, the second fence nano-electrode 10 and the third fence nano-electrode 11;

F, deposit and form insulation on the silicon nanoconductance fine wire 5, the silicon nanocrystal Coulomb island 6, the silicon quantum wire 14, the first fence nano-electrode 9, the second fence nano-electrode 10 and the third fence nano-electrode 11 Dielectric layer 12;

G. Depositing and forming a surface metal floating gate 13 on the insulating dielectric layer 12;

H. Make electrode lead window.

The step A includes: designing the layout, using photolithography and electron beam exposure technology to make a silicon nanowire conductance structure pattern on the SOI substrate covered with electron beam glue; using inductively coupled plasma (ICP) etching technology on the SOI substrate Silicon nanoconductance thin wire 5, silicon quantum wire 14, first ohmic contact conductance step 3, second ohmic contact conductance step 4, third ohmic contact conductance step 15, fourth ohmic contact conductance step 16 and The fifth ohmic contact conductance step 17 is then thermally oxidized to form a nanowire conduction channel limited by the oxide insulating layer.

The step B includes: using electron beam glue as a mask medium for sputtering silicon nanocrystals, using electron beam exposure technology to engrave the Coulomb Island window area for sputtering silicon nanocrystal Coulomb Island 6 on the electron beam glue, so that It is aligned with the silicon nanoconductive thin wire 5 .

The step C includes: sputtering a thin layer of polysilicon on the surface of the electron beam glue and its window area, and removing the thin layer of polysilicon film on the surface of the electron beam glue by a lift-off process, leaving the window area and the silicon nanoconductor Silicon nanocrystalline Coulomb islands 6 aligned with thin wires 5 .

The step D includes: covering the photoresist, engraving a metal electrode window with a photoresist on the ohmic conductance step, depositing metal Ti/Al by electron beam evaporation, and forming the first metal-semiconductor after removing the photoresist. The source metal electrode 7, the first drain metal electrode 8, the metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20 are then annealed at a high temperature at 450°C to 550°C to form metal electrodes Ohmic contact with silicon conductance steps.

The step E includes: covering the electron beam glue, on the silicon nano-conductance thin wire 5 that transports and stores charges, using an electron beam lithography sleeve to carve out a nano-enclosed grid electrode window, using an electron beam evaporation device to deposit metal Ni, removing electron beam glue to form the first grid-enclosed nano-electrode 9 , the second grid-enclosed nano-electrode 10 and the third grid-enclosed nano-electrode 11 .

Said step F includes: using plasma enhanced chemical vapor deposition (PECVD) equipment on silicon nanoconductance thin wires 5, silicon nanocrystal Coulomb islands 6, silicon quantum wires 14, the first fence nano-electrode 9, the second fence An insulating dielectric SiO2 layer 12 is deposited on the nano-electrode 10 and the third gate-surrounding nano-electrode 11 .

The step G includes: covering the photoresist, engraving the floating gate metal electrode window on the insulating dielectric layer 12 with a photolithography sleeve, depositing metal Al by electron beam evaporation, and forming the surface metal floating gate 13 after removing the photoresist .

The step H includes: covering the photoresist, and engraving the first source metal electrode 7, the first drain metal electrode 8, the first fence nano-electrode 9, the second fence nano-electrode 9, and the second fence Gate nano-electrode 10, the third surrounding grid nano-electrode 11, the metal side gate electrode 18, the second source metal electrode 19 and the lead window of the second drain metal electrode 20, use buffered hydrofluoric acid HF to chemically corrode the SiO2 layer electrode The leads are connected to the window, the photoresist is removed, and the metal leads are connected.

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

1. Utilizing the present invention, realizing massive information storage through single electronic memory storage and its charge counting detection system will have huge market demand and social progress significance. Relying on the advantages of low power, high-density integration, and ultra-fast response speed, single-electron memory and its charge counting detection system will play an important and irreplaceable role in the field of mass storage in the future.

2. Using the present invention, silicon nanocrystal memory is an advanced nano-film storage technology at present. This nanoscale non-volatile memory will greatly reduce the material cost of mass memory, so single-electronic memory memory can become the current non-volatile memory. A future replacement for volatile memory.

3. Using the present invention, the single-electron storage device has more excellent performance in the low-temperature environment of space, and the low temperature can provide a better signal background for the Coulomb charge, which is different from the floating gate that relies on hot electrons for information storage memory. Single-electron storage devices on SOI materials are reinforced against the influence of carriers generated by irradiation by strengthening the gate oxide layer and the field oxide layer. Single-electron memory and its charge counting detection system have extremely broad application prospects in future space vehicles.

Description of drawings

FIG. 1 is a schematic structural view of a single-electron memory with a floating gate structure in the prior art;

2 is a schematic diagram of a single-electron memory structure using a granular thin film as a tunnel junction in the prior art;

Fig. 3 is the structural representation of the single electron memory of quasi-one-dimensional quantum dot array in the prior art;

Fig. 4 is the cross-sectional schematic view of the silicon nanocrystal Coulomb island and its conductive channel for charge storage provided by the present invention;

5 is a schematic plan view of a silicon-based single-electron memory memory with a side gate structure provided by the present invention;

FIG. 6 is a flowchart of a method for fabricating a silicon-based single-electron memory with a side gate structure provided by the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

As shown in Figure 4 and Figure 5, Figure 4 is a schematic cross-sectional view of the silicon nanocrystal Coulomb island and its conductive channel for charge storage provided by the present invention, and Figure 5 is a silicon-based single electron with side gate structure provided by the present invention Schematic diagram of the planar structure of memory storage. The silicon-based single-electron memory memory includes: a silicon-on-insulator (SOI) substrate, which is composed of a top layer of silicon, a silicon oxide insulating layer, and a silicon substrate from top to bottom; on the SOI substrate, the top layer of silicon The silicon nanoconductance thin wire 5 and the silicon quantum wire 14 made, the silicon nanoconductance thin wire 5 and the silicon quantum wire 14 are parallel to each other, and the silicon quantum wire 14 is used to detect the stored charge in the silicon nanocrystal Coulomb island 6, and the stored charge Enter the silicon nanocrystal Coulomb island 6 through the silicon nanoconductance thin wire 5; the silicon nanocrystal Coulomb island 6 for storing charge located in the middle of the silicon nanoconductance thin wire 5 and connected with the silicon nanoconductance thin wire 5; The first ohmic contact conductance step 3 and the second ohmic contact conductance step 4 connected to the two ends of the thin line 5 and connected with the silicon nanoconductance thin line 5; the first source metal electrode 7 located on the first ohmic contact conductance step 3 and the The first drain metal electrode 8 on the second ohmic contact conductance step 4; the first surrounding gate nano-electrode 9, the second surrounding gate nano-electrode 10 and The third fence nano-electrode 11, the first fence nano-electrode 9 and the second fence nano-electrode 10 are located on the same side of the silicon nanocrystal Coulomb island 6, and the third fence nano-electrode 11 is located on the silicon nanocrystal Coulomb island. The other side of the island 6; the third ohmic contact conductance step 15 and the fourth ohmic contact conductance step 16 that are located on the other side of the silicon quantum wire 14 relative to the silicon nanometer conductance fine wire 5 and connected to the silicon quantum wire 14; The second source metal electrode 19 on the ohmic contact conductance step 15 and the second drain metal electrode 20 on the fourth ohmic contact conductance step 16; The fifth ohmic contact conductance step 17 on the same side as the ohmic contact conductance step 16 and between the third ohmic contact conductance step 15 and the fourth ohmic contact conductance step 16; the metal side gate electrode 18 located on the fifth ohmic contact conductance step 17 Covering the insulating dielectric layer on the silicon nanoconductance thin wire 5, the silicon nanocrystal Coulomb island 6, the silicon quantum wire 14, the first fence nano-electrode 9, the second fence nano-electrode 10 and the third fence nano-electrode 11 12 ; the surface metal floating gate 13 covering the insulating dielectric layer 12 .

The material used for the silicon nanocrystal Coulomb island 6 is an ultra-thin polysilicon film, which is used to achieve a strong quantum confinement effect on charges at room temperature, and the storage process of each charge depends on the quantum Coulomb blocking effect. Ultra-thin polysilicon films are expected to have strong quantum confinement effects. The change of polysilicon film thickness, the energy change is as large as 300meV, which is much larger than the thermal energy of 26meV at room temperature, so the electron transport parallel to the polysilicon film is strongly affected by the random potential generated by this quantum confinement effect. If the polysilicon film is made as a nanostructure that stores charges, the two-dimensional tunnel junction array formed by the polysilicon nanostructure will not be affected by the background charge. The background charge comes from impurities located close to the quantum dots, as well as the charge-introducing capacitance of other quantum dots. The increase in the number of quantum dots on the quantum dot array of the granular film helps to reduce the total capacitance in series and increase the Coulomb interaction energy of the charge, thereby overcoming the influence of the background charge disturbed by the environmental thermal noise

The potential field of the stored charge acts on the signal current passing through the adjacent silicon quantum wire 14 through capacitive coupling, so that the silicon quantum wire 14 obtains the stored information of a single charge. The silicon quantum wire 14 is used to detect the stored charge, and the potential field of the stored charge silicon nanocrystal Coulomb island 6 acts on the signal current passing through the adjacent silicon quantum wire 14 through capacitive coupling, so as to obtain the stored information of a single charge. The signal current passing through the silicon quantum wire 14 is controlled by the metal side gate electrode 18 and the surface metal floating gate 13 . The conductance current-voltage curve of the quantum wire is nonlinear quantum modulation, and in order to conduct conductance, a limited gate threshold voltage is required. For single-charge writing and erasing states, the threshold voltage of the metal side gate electrode 18 of the single-electron memory will have electrical hysteresis characteristics, reflecting the performance of charge storage and release of the nanocrystalline Coulomb island 6 . As a result, combined with the charge quantization characteristic, within a certain range of gate voltage, the system can be stabilized in two or more charge states, thus, it is possible for the single-electron memory to realize bistable or multi-stable operation.

The first ohmic contact conductance step 3, the second ohmic contact conductance step 4, the third ohmic contact conductance step 15, the fourth ohmic contact conductance step 16 and the fifth ohmic contact conductance step 17 are made of the top silicon layer of the SOI substrate made.

The first source metal electrode 7 and the first drain metal electrode 8 are respectively deposited on the first ohmic contact conductance step 3 and the second ohmic contact conductance step 4, and are annealed to realize ohmic contact; the metal side gate The electrode 18 is deposited on the fifth ohmic contact conductance step 17, and is annealed to realize ohmic contact; the second source metal electrode 19 and the second drain metal electrode 20 are deposited on the third ohmic contact conductance step 15 and the second drain metal electrode 20 respectively. The fourth ohmic contact is on the conductance step 16 and is annealed to realize ohmic contact.

The first fence nano-electrode 9 and the second fence nano-electrode 10 are used to control the entry of a single charge into the silicon nanocrystal Coulomb island 6 to realize the controllable storage of a single charge; the third fence nano-electrode 11 is used for silicon Erasing of stored charge on nanocrystalline Coulomb islands 6.

The storage and erasing of charges only depend on the charging and discharging bias applied to both ends of the silicon nanocrystal Coulomb island 6 and the voltage of the floating gate 13 . In the quantum dot array structure, the strong Coulomb repulsion makes the transmitted and stored electric charges hinder the transmission of other electrons, and the Coulomb energy becomes comparable to the ambient thermal floating energy. The operation of writing and reading a small amount of electrons is to change the e/Cg (Cg is the total capacitance of the storage node) through the threshold gate voltage to overcome the limitation of Coulomb energy on the capture and outflow of single electrons. The silicon nanocrystal Coulomb islands 6 form a two-dimensional array with nano-tunneling junctions, the capacitance of the tunneling junctions in series is reduced, and the charge Coulomb energy will be increased, thereby increasing the working temperature. For the storage and release of single electrons in multi-tunneling junctions, the change in potential difference across the junction array must be greater than one charge Coulomb gap. When the bias is higher than the Coulomb gap, the energy of the intermediate configuration is lower than that of the initial state of the neighbor, and the sequential tunneling effect occurs. The occurrence of sequential tunneling will suppress the co-tunneling, that is, the inelastic tunneling that occurs in the electron-dependent Coulomb island excited state energy level in the Coulomb blockade region. Therefore, the multi-tunnel junction can effectively suppress the leakage current generated by the common tunneling effect, thereby controlling the storage and release of a small amount of charge. Charge is transported from the current channel to one of the isolated points and trapped, this trap causing a quantum jump in the side gate potential. The signal current passing through the silicon quantum wire 14 is controlled by the bias voltage at both ends of the silicon nanocrystal Coulomb island 6 and/or the metal side gate electrode 18 and/or the surface metal floating gate 13 .

On the silicon nanoconductance thin wire 5 connected with the nanocrystalline Coulomb island 6, two adjacent first fence nano-electrodes 9 and second fence nano-electrodes 10 are made to control the entry of single electrons, Achieving controllable storage of single charges. On the other side of the silicon nano-conductance thin wire 5 connected with the nano-crystal Coulomb island 6, a third surrounding gate nano-electrode 11 is made, which is used for erasing the stored charge on the silicon nano-crystal storage island. The area between the adjacent first fence nano-electrode 9 and the second fence nano-electrode 10 is used as a single electron node storage island, and a frequency is applied on the first fence nano-electrode 9 and the second fence nano-electrode 10. With the changing gate voltage of f, this kind of turnstile (turnstile) control gate produces a step-like current ef, as if one electron is transferred out every time the voltage rotates, showing the transport state of a single electron. Due to the extremely small capacitance of the Coulomb island, the charging and discharging time of the capacitor is extremely short, and the switching speed of the device is extremely fast. The electrons that enter into the silicon nanocrystal side gate nano-channel can be effectively artificially controlled by the first fence nano-electrode 9, the second fence nano-electrode 10 and the third fence nano-electrode 11, and the frequency change on the revolving gate acts as an electron The stored input signal, the current change of the adjacent silicon quantum wire 14 is detected as an output signal. The information storage bit of the single electronic memory changes its value more than a predetermined time, and the resulting delay process will cause an error. Quantum dots discharge spontaneously due to thermal excitation or co-tunneling. Even if the correct value is applied to the cell, a write cycle may produce the wrong value, or a read cycle may fail. The process of refreshing the storage position information of the nanocrystalline Coulomb island 6 can be counted and detected by the revolving gate of the first fenced nano-electrode 9, the second fenced nano-electrode 10 and the third fenced nano-electrode 11, so that the write-in Refreshed BER.

Based on the schematic structural diagrams of the silicon-based single-electron memory with a side gate structure provided in Figure 4 and Figure 5 above, Figure 6 shows a flow chart of a method for fabricating a silicon-based single-electron memory with a side-gate structure provided by the present invention, the method Include the following steps:

Step 601: Fabricate silicon nanometer conductance thin wires 5, silicon quantum wires 14, the first ohmic contact conductance step 3, the second ohmic contact conductance step 4, and the third ohmic contact conductance step 15 on the silicon oxide insulating layer of the SOI substrate , the fourth ohm contact conductance step 16 and the fifth ohm contact conductance step 17;

Step 602: using a mask dielectric sleeve to carve out a Coulomb island window connected to the silicon nanoconductive thin wire 5, exposing the silicon oxide insulating layer of the SOI substrate;

Step 603: sputtering a thin layer of polysilicon, chemically etching away the mask medium, and forming silicon nanocrystal Coulomb islands 6 in the Coulomb island window area;

Step 604: Depositing and forming the first source metal electrode 7, the first drain metal electrode 8, the metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20, and annealing to realize ohmic contact;

Step 605: Depositing and forming the first fenced nano-electrode 9, the second fenced nano-electrode 10 and the third fenced nano-electrode 11;

Step 606: Deposit and form silicon nanoconductance thin wires 5, silicon nanocrystal Coulomb islands 6, silicon quantum wires 14, first fenced nanoelectrodes 9, second fenced nanoelectrodes 10, and third fenced nanoelectrodes 11 insulating dielectric layer 12;

Step 607: Deposit and form a surface metal floating gate 13 on the insulating dielectric layer 12;

Step 608: Make electrode lead window.

Example

Based on the flow chart of the method for fabricating a silicon-based single-electron memory with a side-gate structure shown in FIG. 6 , the method for fabricating a silicon-based single-electron memory with a side-gate structure of the present invention will be further described in detail below in conjunction with specific embodiments.

The process implementation method of a silicon-based single-electron memory memory with a side gate structure provided by the present invention specifically includes the following steps:

(1) Fabricate a nanowire conductance structure on the SOI silicon film;

According to the layout of the structural design described in Figure 4 and Figure 5, use photolithography and electron beam exposure technology to make silicon nanowire conductance structure patterns on the SOI sheet covered with electron beam glue; and then use inductively coupled plasma (ICP) etching technology Fabricate silicon nanoconductance thin wire 5, silicon quantum wire 14, first ohmic contact conductance step 3, second ohmic contact conductance step 4, third ohmic contact conductance step 15, fourth ohmic contact conductance step 16 and fifth ohmic contact Conductance step 17. Then, through thermal oxidation, the conductive channel of nanowires limited by the oxide insulating layer is formed.

(2) Covering the masking medium;

Electron beam gel polymethyl methacrylate (PolyMethyl MethAcrylate, PMMA) with a thickness of 150nm was used as a mask medium for the growth of silicon nanocrystals.

(3) Carve out silicon nanocrystal Coulomb island window;

Electron beam glue is used as a mask medium for sputtering silicon nanocrystals, and the Coulomb island window area for sputtering silicon nanocrystal Coulomb islands 6 is overcutted on the electron beam glue by using electron beam exposure technology, so that it can be compared with silicon nanocrystals. Line 5 is aligned so that silicon nanocrystals are sputtered on the silicon oxide surface in the window region.

(4) sputtering a thin layer of polysilicon on the surface of the electron beam glue and its window area, with a thickness of 50nm, and removing the thin layer of polysilicon film on the surface of the electron beam glue by a lift-off process, leaving the window area and silicon Silicon Nanocrystalline Coulomb Islands 6 Aligned with Nanoconductive Thin Wires 5

(5) Remove the covered mask medium: use acetone to remove the PMMA mask and the silicon nanocrystal thin layer thereon.

(6) The silicon nanocrystal Coulomb island 6 on the surface of silicon oxide is connected to the silicon nanoconductance thin wire 5 , and the high-temperature annealing is to realize better electrical contact between the silicon nanocrystal and the silicon nanowire.

(7) Making ohmic contact metal electrodes:

Cover the photoresist, engrave the metal electrode window with a photoresist sleeve on the ohmic conductivity step, and deposit metal Ti/Al by electron beam evaporation. After removing the photoresist, anneal at a high temperature at 450°C to 550°C to form a metal-semiconductor The first source metal electrode 7 , the first drain metal electrode 8 , the metal side gate electrode 18 , the second source metal electrode 19 and the second drain metal electrode 20 .

(8) Make the control fence metal electrode:

Cover the electron beam glue, on the silicon nanometer conductance thin wire 5 that transports and stores charges, use the electron beam lithography to engrave the nano-enclosed grid electrode window, use the electron beam evaporation equipment to deposit metal Ni, remove the electron beam glue, and form the second A fence nano-electrode 9 , a second fence nano-electrode 10 and a third fence nano-electrode 11 .

(9) Covering the insulating dielectric layer:

Utilize the plasma enhanced chemical vapor deposition (PECVD) equipment on silicon nanoconductance thin wire 5, silicon nanocrystal Coulomb island 6, silicon quantum wire 14, the first fence nano-electrode 9, the second fence nano-electrode 10 and the third An insulating dielectric SiO2 layer 12 is deposited on the surrounding gate nano-electrodes 11 .

(10) Deposit floating gate metal electrodes:

Cover the photoresist, engrave the floating gate metal electrode window on the insulating medium layer 12 with photolithography, use electron beam evaporation to deposit metal Al, and form the surface metal floating gate 13 after removing the photoresist.

(11) Make electrode lead window:

Cover the photoresist, and engrave the first source metal electrode 7, the first drain metal electrode 8, the first fence nano-electrode 9, the second fence nano-electrode 10, the The lead window of the three-enclosed gate nano-electrode 11, the metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20 is chemically corroded with buffered hydrofluoric acid HF to go out the SiO2 layer electrode lead connection window, and remove the light. Resist to connect metal leads.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (16)

1. A silicon-based single-electron memory with a side gate structure, characterized in that the silicon-based single-electronic memory comprises: Silicon-on-insulator SOI substrate; On the SOI substrate, silicon nanometer conductance thin wires (5) and silicon quantum wires (14) made of top-layer silicon, the silicon nanometer conductance thin wires (5) and silicon quantum wires (14) are parallel to each other, and silicon quantum wires (14) are parallel to each other. The line (14) is used to detect the stored charge in the silicon nanocrystal Coulomb island (6), and the stored charge enters the silicon nanocrystal Coulomb island (6) through the silicon nanoconductance thin line (5); A silicon nanocrystal Coulomb island (6) for storing charges located in the middle of the silicon nanoconductance thin wire (5) and connected to the silicon nanoconductance thin wire (5); A first ohmic contact conductance step (3) and a second ohmic contact conductance step (4) located at both ends of the silicon nanoconductance thin wire (5) and connected to the silicon nanoconductance thin wire (5); A first source metal electrode (7) located on the first ohmic contact conductance step (3) and a first drain metal electrode (8) located on the second ohmic contact conductance step (4); The first grid-enclosed nano-electrode (9), the second grid-enclosed nano-electrode (10) and the third grid-enclosed nano-electrode (11) located on the silicon nano-conductance thin wires (5) on both sides of the silicon nanocrystal Coulomb island (6) , the first fence nano-electrode (9) and the second fence nano-electrode (10) are located on the same side of the silicon nanocrystal Coulomb island (6), and the third fence nano-electrode (11) is located at the silicon nanocrystal The other side of Coulomb Island (6); A third ohmic contact conductance step (15) and a fourth ohmic contact conductance step (16) located on the other side of the silicon quantum wire (14) relative to the silicon nanoconductance thin wire (5) and connected to the silicon quantum wire (14); A second source metal electrode (19) located on the third ohmic contact conductance step (15) and a second drain metal electrode (20) located on the fourth ohmic contact conductance step (16); Located on the same side of the silicon quantum wire (14) relative to the third ohmic contact conductance step (15) and the fourth ohmic contact conductance step (16) and between the third ohmic contact conductance step (15) and the fourth ohmic contact conductance step ( 16) fifth ohmic contact conductance step between (17); A metal side gate electrode (18) located on the fifth ohmic contact conductance step (17); Covered with silicon nanoconductance thin wires (5), silicon nanocrystal Coulomb islands (6), silicon quantum wires (14), first fenced nano-electrodes (9), second fenced nano-electrodes (10) and third fenced The insulating dielectric layer (12) on the gate nano-electrode (11); A surface metal floating gate (13) covered on the insulating medium layer (12). 2. the silicon-based single-electron memory memory with side gate structure according to claim 1, is characterized in that, the used material of described silicon nanocrystal Coulomb island (6) is ultra-thin polysilicon film, is used for realizing under room temperature condition Due to the strong quantum confinement effect of charges, the storage process of each charge depends on the quantum Coulomb blockade effect. 3. The silicon-based single-electron memory memory with side gate structure according to claim 1, characterized in that, the potential field of the stored charge acts on the signal current passing through adjacent silicon quantum wires (14) through capacitive coupling, The silicon quantum wire (14) obtains the storage information of a single charge. 4. The silicon-based single-electron memory with a side gate structure according to claim 3, characterized in that, the signal current is controlled by a metal side gate electrode (18) and/or a surface metal floating gate (13). 5. The silicon-based single-electron memory memory with side gate structure according to claim 1, characterized in that, the first ohmic contact conductance step (3), the second ohmic contact conductance step (4), the third ohmic contact The contact conductance step (15), the fourth ohmic contact conductance step (16) and the fifth ohmic contact conductance step (17) are made of the top layer silicon of the SOI substrate. 6. The silicon-based single-electron memory with side gate structure according to claim 1, characterized in that, the first source metal electrode (7) and the first drain metal electrode (8) are respectively deposited on On the first ohmic contact conductance step (3) and the second ohmic contact conductance step (4), the ohmic contact is realized through annealing; The metal side gate electrode (18) is deposited on the fifth ohmic contact conductance step (17), and is annealed to realize ohmic contact; The second source metal electrode (19) and the second drain metal electrode (20) are respectively deposited on the third ohmic contact conductance step (15) and the fourth ohmic contact conductance step (16), and are annealed to realize ohmic contact. 7. The silicon-based single-electron memory memory with side gate structure according to claim 1, characterized in that, The first grid-enclosed nano-electrode (9) and the second grid-enclosed nano-electrode (10) are used to control a single charge to enter the silicon nanocrystal Coulomb island (6), so as to realize the controllable storage of a single charge; The third surrounding gate nano-electrode (11) is used for erasing the charge stored on the silicon nano-crystal Coulomb island (6). 8. A method for fabricating a silicon-based single-electron memory with a side gate structure, characterized in that the method comprises: A. On the silicon oxide insulating layer of the SOI substrate, silicon nanometer conductance thin wires (5), silicon quantum wires (14), first ohmic contact conductance steps (3), second ohmic contact conductance steps (4), The third ohm contact conductance step (15), the fourth ohm contact conductance step (16) and the fifth ohm contact conductance step (17); B. Utilize the mask dielectric sleeve to engrave the Coulomb island window connected with the silicon nanometer conductive thin wire (5), exposing the silicon oxide insulating layer of the SOI substrate; C, sputtering a thin layer of polysilicon, chemically etching away the mask medium, and forming a silicon nanocrystal Coulomb island (6) in the Coulomb island window region; D, deposition forms the first source metal electrode (7), the first drain metal electrode (8), the metal side gate electrode (18), the second source metal electrode (19) and the second drain metal electrode ( 20), and annealed to achieve ohmic contact; E, deposition forms the first fence nano-electrode (9), the second fence nano-electrode (10) and the third fence nano-electrode (11); F, in silicon nanoconductance thin wire (5), silicon nanocrystal Coulomb island (6), silicon quantum wire (14), the first fence nano-electrode (9), the second fence nano-electrode (10) and the third An insulating dielectric layer (12) is formed by depositing on the fence nano-electrode (11); G, deposit and form the surface metal floating gate (13) on the insulating medium layer (12); H. Make electrode lead window. 9. The method for fabricating a silicon-based single-electron memory with a side gate structure according to claim 8, wherein said step A comprises: Design layout, use photolithography and electron beam exposure technology to make silicon nanowire conductance structure pattern on SOI substrate covered with electron beam glue; Using inductively coupled plasma ICP etching technology to fabricate silicon nano-conductance thin wires (5), silicon quantum wires (14), the first ohmic contact conductance step (3), and the second ohmic contact conductance on the top silicon of the SOI substrate. The step (4), the third ohmic contact conductance step (15), the fourth ohmic contact conductance step (16) and the fifth ohmic contact conductance step (17), and then thermally oxidized to form an oxide insulating layer limited nanowire conduction aisle. 10. The method for fabricating a silicon-based single-electron memory with a side gate structure according to claim 8, wherein the step B comprises: Electron beam glue is used as the mask medium for sputtering silicon nanocrystals, and the Coulomb island window area for sputtering silicon nanocrystal Coulomb islands (6) is engraved on the electron beam glue by using electron beam exposure technology, so that it is similar to silicon nanocrystals. Conductance thin wires (5) are aligned. 11. The method for fabricating a silicon-based single-electron memory with a side gate structure according to claim 8, wherein the step C comprises: A thin layer of polysilicon is sputtered on the surface of the electron beam glue and its window area, and the thin layer of polysilicon film on the surface of the electron beam glue is removed by a lift-off process, leaving the window area aligned with the silicon nanometer conductive thin line (5) Silicon Nanocrystalline Coulomb Islands (6). 12. The method for fabricating a silicon-based single-electron memory with a side gate structure according to claim 8, wherein the step D comprises: Cover the photoresist, engrave the metal electrode window with a photoresist sleeve on the ohmic conductance step, and deposit metal Ti/Al by electron beam evaporation. After removing the photoresist, the first source metal electrode of the metal-semiconductor is formed (7 ), the first drain metal electrode (8), the metal side gate electrode (18), the second source metal electrode (19) and the second drain metal electrode (20), and then high temperature annealing at 450C° to 550C° , forming an ohmic contact between the metal electrode and the silicon conductance step. 13. The method for fabricating a silicon-based single-electron memory with a side-gate structure according to claim 8, wherein the step E comprises: Cover the electron beam glue, on the silicon nanometer conductance thin wire (5) that transports and stores the charge, use the electron beam lithography sleeve to carve out the nano-enclosed grid electrode window, use the electron beam evaporation equipment to deposit metal Ni, remove the electron beam glue, Forming the first fence nano-electrode (9), the second fence nano-electrode (10) and the third fence nano-electrode (11). 14. The method for fabricating a silicon-based single-electron memory with a side gate structure according to claim 8, wherein the step F comprises: Using plasma-enhanced chemical vapor deposition PECVD equipment, silicon nanoconductance thin wires (5), silicon nanocrystal Coulomb islands (6), silicon quantum wires (14), first fence nano-electrodes (9), and second fence An insulating dielectric SiO2 layer (12) is deposited on the nano-electrode (10) and the third grid-surrounding nano-electrode (11). 15. The method for fabricating a silicon-based single-electron memory with a side gate structure according to claim 8, characterized in that the step G comprises: The photoresist is covered, and the metal electrode window of the floating gate is engraved on the insulating medium layer (12) with a photoresist cover, the metal Al is deposited by electron beam evaporation, and the surface metal floating gate (13) is formed after removing the photoresist. 16. The method for fabricating a silicon-based single-electron memory with a side gate structure according to claim 8, wherein the step H comprises: Cover the photoresist, engrave the first source metal electrode (7), the first drain metal electrode (8), the first surrounding gate nano-electrode (9), the first The lead window of the second fence nano-electrode (10), the third fence nano-electrode (11), the metal side gate electrode (18), the second source metal electrode (19) and the second drain metal electrode (20), Use buffered hydrofluoric acid HF to chemically etch out the SiO2 layer electrode lead connection window, remove the photoresist, and connect the metal lead.

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