CN101556922B - A kind of nano ring gate MOSFET transistor and its preparation method - Google Patents

Abstract

The invention discloses a nano surrounding-gate MOSFET transistor and a preparation method thereof. The method sequentially comprises the following steps: growing an isolating layer, a back-gate dielectric layer and an isolating layer on a substrate; photoetching the isolating layer arranged on the dielectric layer to obtain a figure of a back-gate electrode; depositing and victimizing a side-walldielectric layer to thicken; photoetching a line with the diameter within 100 nanometers and with a semicircular section on the layer; depositing an amorphous silica dielectric layer which is inducedinto a polysilicon crystallization dielectric layer by metal to obtain a channel region dielectric layer; photoetching the dielectric layer to obtain a channel region; growing the isolating layer, depositing a polysilicon gate dielectric layer and pouring in by taking the gate dielectric layer as mask ions; photoetching the back-gate dielectric layer to obtain a preliminarily etched hole of a back gate; depositing a passivation layer on the polysilicon gate dielectric layer, and photoetching the polysilicon gate dielectric layer to obtain a contact hole from which aluminium is spattered. Themethod is compatible with a silica-based nanowire field-effect device and a traditional scaling down processing method, has simple process and easy control, and obtains the transistor with high driving performance and easy process realization, thereby having a change of being applied to future nano integrated circuits.

Description

A kind of nano ring gate MOSFET transistor and its preparation method

technical field

The invention relates to the field of semiconductor built-up circuit and its manufacturing technology, in particular to a nanometer ring gate MOSFET transistor and a preparation method thereof.

Background technique

CMOS (Complementary Metal Oxide Semiconductor) technology is the mainstream technology of integrated circuits today. As device dimensions continue to shrink, integration increases exponentially, and circuit performance continues to improve. However, as the feature size of MOSFET devices enters the deep submicron and nanometer range, the short channel effect will have an important impact on device performance. At the same time, the traditional device structure and manufacturing process have also encountered new challenges. In order to continue the effectiveness of Moore's law, new device structures such as double-gate devices, FINFET, etc. and their preparation methods have been extensively studied in recent years. Among them, the superior ability of GAA (Gate All Around) MOSFET in suppressing the short channel effect and improving current control makes it one of the most powerful competitors for the future MOSFET device structure. However, due to the relatively complex structure of GAA MOSFET, how to successfully solve the preparation of this device structure is of great significance to the development of integrated circuits.

Contents of the invention

The object of the present invention is to provide a nanometer ring gate MOSFET transistor and a preparation method thereof.

The method for preparing the nanometer ring gate MOSFET transistor provided by the present invention comprises the following steps successively:

1) growing an isolation layer on the semiconductor substrate;

2) On the isolation layer in step 1), grow a back gate dielectric layer and an isolation layer in sequence;

3) The isolation layer obtained in photolithography step 2) to obtain the pattern of the back gate electrode;

4) Deposit a layer of sacrificial sidewall dielectric layer on the isolation layer engraved with the pattern of the back gate electrode, and make it dense;

5) photoetching lines of 0.4-1.0 microns on the sacrificial sidewall dielectric layer;

6) reducing the size of the lithographic lines obtained in step 5) to 200-400 nanometers, and making the cross-section of the lithographic lines rectangular;

7) Etching the photoresist lines obtained in step 6), so that the cross section of the photoresist lines is semicircular, and the size is reduced to within 100 nanometers;

8) Deposit an amorphous silicon dielectric layer on the sacrificial sidewall dielectric layer engraved with photolithographic lines obtained in step 7), and transform the amorphous silicon dielectric layer into a metal-induced polysilicon crystallization dielectric layer to obtain a nanoring A dielectric layer in the channel region of the gate MOSFET transistor;

9) photolithography step 8) the obtained metal-induced polysilicon crystallization medium layer, to obtain the channel region of the nano-ring MOSFET transistor;

10) On the metal-induced polysilicon crystallization dielectric layer containing the channel region obtained in step 9), grow a layer of silicon dioxide as an isolation layer, and deposit a layer of polysilicon gate dielectric layer;

11) using the gate dielectric layer obtained in step 10) as a mask to perform phosphorus ion implantation;

12) The photolithography step 2) obtains the back gate dielectric layer to obtain the pre-engraved hole of the back gate;

13) On the polysilicon gate dielectric layer, sequentially deposit silicon dioxide as a passivation layer, photoetch the silicon dioxide layer to obtain contact holes, and sputter aluminum to obtain a nano-ring MOSFET transistor.

In step 1) of the above-mentioned method for preparing a nano-ring MOSFET transistor, the semiconductor substrate used is selected from Si, Ge, SiGe or GaAs, or binary and ternary compound semiconductors of II-VI, III-V or IV-IV groups Any one of them or a mixture of any combination thereof; the isolation layer on the semiconductor substrate is silicon dioxide;

In step 2), the back gate dielectric layer is polysilicon with a thickness of 4-5nm, and the isolation layer on the back gate dielectric layer is silicon nitride;

In step 4), the sacrificial sidewall dielectric layer is silicon dioxide with a thickness of 250-400nm, the temperature of the densification step is 900°C, and the densification time is 30 minutes;

In step 6), it is preferable to carry out plasma pretreatment (descume) with a photoresist, and reduce the size of the photoresist lines obtained in step 5) to 200-400 nanometers;

In step 7), the etching solution used in the etching step is hydrofluoric acid: an aqueous hydrofluoric acid solution with a volume ratio of water of 1:50;

In step 8), it is preferable to use a metal-induced polysilicon crystallization process to convert the amorphous silicon dielectric layer into a metal-induced polysilicon crystallization dielectric layer;

In step 10), the thickness of the silicon dioxide isolation layer is 40-50 angstroms, and the thickness of the polysilicon gate dielectric layer is 80-100 nanometers;

In step 11), in the ion implantation step, the implantation dose of phosphorus is 4e+15/cm ^-2 , and the implantation energy is 40KeV;

In step 12), the back gate pre-cut hole is a square with a side length of 1 micron.

In step 13), the thickness of the silicon dioxide used as the passivation layer is 4000 angstroms, and the thickness of sputtered aluminum is 8000 angstroms.

In addition, the nanometer ring gate MOSFET transistor obtained by the above preparation method also belongs to the protection scope of the present invention.

The method for preparing nano-ring MOSFET transistors provided by the present invention is compatible with the silicon-based nanowire field effect device and the traditional "scaling down" processing method. From the optimization design of the layout, the self-created ASHING fine silicon-based nano-arc line technology, Comprehensive application of metal-induced polysilicon crystallization (MILC) process combined with practical and feasible process flow design to realize a gate-around structure, which has a strong control effect of the gate electrode on the channel, can achieve high driving capability, and is easy to process. Field Effect Transistor Devices with Core-Shell Structure. The preparation method is simple in process, easy to control, has high practical value, and is expected to be applied in future nanometer integrated circuits.

Description of drawings

FIG. 1 shows the process steps of growing an isolation layer on a semiconductor substrate.

FIG. 2 shows the process steps of growing a back gate dielectric layer.

FIG. 3 is a process step of growing an isolation layer of a back gate dielectric layer.

FIG. 4 shows the process steps of depositing silicon dioxide as a sacrificial sidewall dielectric layer.

FIG. 5 shows the process steps of photoetching 0.4-1.0 micron lines on the sacrificial sidewall dielectric layer.

FIG. 6 shows the process steps of plasma pretreatment with photoresist to reduce the size of nanowires.

FIG. 7 is a process step of etching the cross-section of a photoresist line into a semicircle by repeated rinsing in a 1:50 hydrofluoric acid solution.

Fig. 8 is a process step of depositing an α-Si dielectric layer.

FIG. 9 shows the process steps of metal-induced polysilicon crystallization (MILC).

FIG. 10 is a process step of forming a channel region by photolithography on the MILC dielectric layer.

Figure 11 shows the process steps of growing silicon dioxide as an isolation layer.

FIG. 12 shows the process steps of depositing a polysilicon gate dielectric layer.

Detailed ways

In the method for preparing the nanometer ring gate MOSFET transistor provided by the present invention, the steps such as photolithography, etching, and plasma pretreatment are standard semiconductor preparation process steps, and can refer to "Semiconductor Device Physics and Technology" published by Soochow University Press ".

The method for preparing a nanometer ring gate MOSFET transistor provided by the present invention will be further described below in conjunction with the accompanying drawings, but the present invention is not limited to the following examples.

Embodiment 1, preparation nano-surround gate MOSFET transistor

The method for preparing the nanometer ring gate MOSFET transistor provided by the present invention comprises the following steps successively:

1) As shown in Figure 1, an isolation layer B is grown on a semiconductor substrate A; the semiconductor substrate A used is a silicon substrate, and the isolation layer B is silicon dioxide;

2) On the isolation layer B in step 1), grow a back gate dielectric layer C, which is polysilicon with a thickness of 300nm, as shown in Figure 2; then on the back gate dielectric layer C, growing isolation layer silicon nitride;

3) The isolation layer obtained in the photolithography step 2) is obtained to obtain an isolation layer D engraved with a back gate electrode pattern, as shown in Figure 3;

4) Deposit a layer of sacrificial sidewall dielectric layer _E1 on the isolation layer D engraved with the pattern of the back gate electrode, and make it dense; the sacrificial sidewall dielectric layer is made of silicon dioxide with a thickness of 250nm. Oxygen method is used for densification, the densification temperature is 900°C, and the densification time is 30 minutes;

5) Lithographically etching lines E ₂ of 0.4-1.0 microns on the sacrificial sidewall dielectric layer, as shown in FIG. 5 ;

6) Use the method of carrying out plasma pretreatment (descume) with photoresist, reduce the size _E2 of the photoresist line obtained in step 5) to within 100 nanometers, and make the cross section of the photoresist line rectangular, and the photoresist obtained The engraved line is E ₃ , as shown in Figure 6;

7) Etching the photoresist line _E3 obtained in step 6), so that the cross section of the photoresist line is semicircular, and the size is reduced to within 100 nanometers, and the obtained photoresist line is _E4 , as shown in Figure 7; The etching solution is hydrofluoric acid: an aqueous hydrofluoric acid solution with a volume ratio of 1:50 of water;

8) Deposit an amorphous silicon dielectric layer F on the sacrificial sidewall dielectric layer engraved with photolithographic lines _E4 obtained in step 7), as shown in Figure 8; A layer of silicon dioxide H is deposited on the amorphous silicon dielectric layer F, and then the amorphous silicon dielectric layer F is converted into a metal-induced polysilicon crystallization dielectric layer G to obtain a dielectric layer in the channel region of the nano-ring MOSFET transistor, such as As shown in Figure 9;

9) The metal-induced polysilicon crystallization dielectric layer G obtained in the photolithography step 8) is obtained to obtain the channel region of the nano-gate-all-around MOSFET transistor, as shown in FIG. 10 ;

10) On the metal-induced polysilicon crystallization dielectric layer containing the channel region obtained in step 9), grow a layer of silicon dioxide with a thickness of 50 angstroms as the isolation layer I, as shown in Figure 11, and deposit a layer with a thickness of A polysilicon gate dielectric layer J of 100 nanometers, as shown in FIG. 12 ;

11) Using the gate dielectric layer J obtained in step 10) as a mask, perform ion implantation of phosphorus, the implantation dose of phosphorus is 4e+15/cm ^-2 , and the implantation energy is 40KeV;

12) The back gate dielectric layer C obtained in photolithography step 2) obtains the pre-engraved hole of the back gate, and the pre-engraved hole of the back gate is a square with a side length of 1 micron;

13) On the polysilicon gate dielectric layer J, sequentially deposit silicon dioxide with a thickness of 4000 angstroms as a passivation layer, photoetch the silicon dioxide layer to obtain contact holes, and sputter aluminum, the thickness of the aluminum layer is 8000 angstroms, and obtain The nano ring gate MOSFET transistor provided by the invention.

It has been determined that the threshold voltage of the nanometer ring gate MOSFET transistor is 0.4V.

Claims (10)

1. method for preparing nano surrounding-gate MOSFET transistor in turn includes the following steps:

1) separator of on Semiconductor substrate, growing;

2) on the separator of described step 1), gate dielectric layer and separator are carried on the back in growth successively;

3) the described step 2 of the photoetching) separator that obtains obtains being carved with the separator of back-gate electrode figure;

4) on the described separator that is carved with the back-gate electrode figure, deposit one deck is sacrificed the sidewall dielectric layer, and fine and close;

5) lines of photoetching 0.4-1.0 micron on described sacrifice sidewall dielectric layer;

6) size with described step 5) gained photoetching lines is reduced to the 200-400 nanometer, and to make the cross section of described photoetching lines be rectangle;

7) the photoetching lines that obtain of the described step 6) of etching, the cross section that makes described photoetching lines is for semicircle, and size is reduced in 100 nanometers;

8) be carved with on the sacrifice sidewall dielectric layer of photoetching lines at described step 7) gained, deposit amorphous silicon dielectric layer, and make described amorphous silicon dielectric layer change metal inducement polysilicon crystallization dielectric layer into, obtain the dielectric layer of described nano surrounding-gate MOSFET transistor channel region;

9) the described step 8) gained of photoetching metal inducement polysilicon crystallization dielectric layer obtains the channel region of described nano surrounding-gate MOSFET transistor;

10) contain on the metal inducement polysilicon crystallization dielectric layer of channel region at described step 9) gained, the growth layer of silicon dioxide is as separator, and deposit one deck polysilicon gate dielectric layer;

11) be mask with described step 10) gained polysilicon gate dielectric layer, carry out ion and inject;

12) the described step 2 of photoetching) gained back of the body gate dielectric layer, the hole at pre-quarter that obtains carrying on the back grid;

13) on described polysilicon gate dielectric layer, deposit silicon dioxide is as passivation layer successively, and the described silicon dioxide layer of photoetching obtains contact hole, spatters aluminium, obtains described nano surrounding-gate MOSFET transistor.

2. according to the described preparation method of claim 1, it is characterized in that: in the described step 1), described Semiconductor substrate is selected from Si or Ge, or the mixture of any one or its combination in any in the binary of II-VI, III-V or IV-IV family and the ternary semiconductor; Separator on the described Semiconductor substrate is a silicon dioxide.

3. according to claim 1 or 2 described preparation methods, it is characterized in that: described step 2), back of the body gate dielectric layer is a polysilicon, and thickness is 4-5nm; Separator on the described back of the body gate dielectric layer is a silicon nitride.

4. according to claim 1 or 2 described preparation methods, it is characterized in that: in the described step 4), sacrificing the sidewall dielectric layer is silicon dioxide, and described densification temperature is 900 ℃, and the fine and close time is 30 minutes, and the thickness of described sacrifice sidewall dielectric layer is 300nm; Described deposition process is the low pressure vapor deposition method.

5. according to claim 1 or 2 described preparation methods, it is characterized in that: in the described step 6), adopt the band photoresist to carry out the pretreated method of electricity slurry, the size of described step 5) gained photoetching lines is reduced to the step of 200-400 nanometer; In the described step 7), the used etching liquid of etch step is a hydrofluoric acid: the volume ratio of water is 1: 50 a hydrofluoric acid aqueous solution.

6. according to claim 1 or 2 described preparation methods, it is characterized in that: in the described step 8), adopt metal inducement polysilicon crystallization process, change described amorphous silicon dielectric layer into metal inducement polysilicon crystallization dielectric layer; Described deposition process is the low pressure vapor deposition method.

7. according to claim 1 or 2 described preparation methods, it is characterized in that: in the described step 10), the thickness of silicon dioxide separator is the 40-50 dust, and the thickness of described polysilicon gate dielectric layer is the 80-100 nanometer.

8. according to claim 1 or 2 described preparation methods, it is characterized in that: in the described step 11), the ion of injection is a phosphorus, and the implantation dosage of phosphorus is 4e+15/cm ^-2, the injection energy is 40KeV.

9. according to claim 1 or 2 described preparation methods, it is characterized in that: in the described step 13), the thickness of described silicon dioxide as passivation layer is 4000 dusts, and the described aluminium thickness that spatters is 8000 dusts.

10. the nano surrounding-gate MOSFET transistor that obtains of the arbitrary described preparation method of claim 1-9.

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