CN106684141A - High linearity GaN fin-type high electron mobility transistor and manufacture method thereof - Google Patents

Abstract

The invention relates to a GaN fin-type high electron mobility transistor with high linearity and a manufacturing method thereof. The structure of the transistor of the invention includes a substrate, a buffer layer, a barrier layer, and a passivation layer sequentially from bottom to top; One end above the barrier layer is provided with a source electrode and the other end is provided with a drain electrode; a passivation layer is provided above the barrier layer between the source electrode and the drain electrode, and a groove is provided in the passivation layer , the groove is provided with a T-shaped gate, which is characterized in that periodically arranged GaN-based three-dimensional fins are etched on the barrier layer and the buffer layer limited to the region below the groove, and the GaN-based The length of the three-dimensional fins is equal to the length of the groove, and isolation grooves formed by etching are provided between adjacent GaN-based three-dimensional fins. The device of the invention has high linearity, high output current, strong grid control capability, good heat dissipation performance and high frequency characteristics; the process method of the invention is simple and reliable, and is suitable for high-power and high-linear microwave power devices.

Description

A GaN fin-type high electron mobility transistor with high linearity and its fabrication method

technical field

The invention belongs to the technical field of semiconductor device preparation, in particular to a GaN fin-type high electron mobility transistor with high linearity and a manufacturing method thereof.

technical background

The third-generation semiconductor GaN-based high electron mobility transistor (HEMT) has the characteristics of high output power density, high efficiency, high temperature resistance, and radiation resistance, and has become the mainstream technology for manufacturing high-frequency, high-efficiency, and high-power electronic devices. The performance of weapons and equipment represented by radar has been improved. With the urgent demand for high-linearity transistors in high-data stream satellite communications and modern wireless communication applications (such as 5G communications), high-linearity devices are now the key development direction in the GaN field. High linearity will bring more effective spectrum utilization, and can reduce the demand for linearization modules, further increasing the efficiency and integration of the entire system.

The transconductance of the traditional GaN planar structure exhibits typical peak characteristics, that is, the transconductance is seriously degraded under high current, resulting in rapid compression of device gain under high input power, poor intermodulation characteristics, and low linearity. In order to overcome this defect, the Hong Kong University of Science and Technology proposed an Al _0.05 Ga _0.95 N/GaN composite channel in 2005, which improved the transconductance to a certain extent by reducing the vertical electric field of the channel (see the literature Jie Liu et al., Highly Linear Al _0.3 Ga _0.7 N–Al _0.05 Ga _0.95 N–GaN Composite-Channel HEMTs, IEEE Electron Device Lett., vol.26, no.3, pp.145-147, 2005). Subsequently, North Carolina State University in the United States found that the nonlinear source resistance caused by space charge limitation is the main factor limiting the linearity of GaN devices (see Robert J.Trew et al., Nonlinear Source Resistance in High-Voltage Microwave AlGaN/GaN HFETs, IEEE Trans. Microw. Theory Tech., vol.54, no.5, pp.2061-2067, 2006). Therefore, the composite channel structure is very limited in improving linearity, and will lead to an increase in channel thermal resistance, and a significant degradation of device output power, frequency, and efficiency.

GaN FinFET (or three-dimensional fin structure) has recently received close attention from research institutions at home and abroad. It enhances the ability to control channel electrons by introducing additional side gates on both sides of the channel. Compared with traditional structures, it shows better Sub-threshold characteristics, off-state characteristics, and short-channel effects are also greatly suppressed (see the literature Kota Ohi et al., CurrentStability in Multi-Mesa-Channel AlGaN/GaN HEMTs, IEEE Trans. Electron Devices., vol.60, no .10, pp.2997-3004, 2013). Subsequently, MIT reported GaNFinFET devices with high transconductance and f _T linearity (see literature Kota Ohi Dong Seup Lee et al., Nanowire Channel InAlN/GaNHEMTs With High Linearity of g _m and f _T , IEEE Electron Devices., vol .34, no.8, pp.969-971, 2013), and pointed out that the fundamental reason for the high linearity of the transconductance is that the three-dimensional fins are completely wrapped by the gate metal. However, in order to achieve this goal, the preparation of fins adopts a self-alignment method, the process is complex, and the compatibility with traditional GaN device processes is poor; the most important thing is that the gate electrode of the device prepared by this process is a straight gate structure, and the gate resistance is large. , resulting in a low maximum oscillation frequency, which ultimately limits its application in microwave power circuits.

The Chinese patent application discloses a multi-channel fin structure AlGaN/GaN high electron mobility transistor structure and manufacturing method, which mainly solves the problems of poor gate control capability of existing multi-channel devices and low current of FinFET devices. The structure of the device includes substrate (1), the first layer of AlGaN/GaN heterojunction (2), SiN passivation layer (4) and source-drain-gate electrodes from bottom to top. On the top AlGaN barrier layers on both sides of the passivation layer, among them: a GaN layer and an AlGaN barrier layer are arranged between the first layer of AlGaN/GaN heterojunction and the SiN passivation layer to form the second layer of AlGaN/GaN heterojunction (3); the gate electrode covers the top of the heterojunction in the second layer and the sidewalls of the heterojunction in the first layer and the second layer. The device has strong gate control capability, large saturation current, and good subthreshold characteristics, and can be used for microwave power devices with short gate length, low power consumption and low noise.

The Chinese patent application discloses a T-gate N-plane GaN/AlGaN fin-type high electron mobility transistor, which mainly solves the problems of low maximum oscillation frequency, large ohmic contact resistance and serious short channel effect of existing microwave power devices. The structure of the device includes from bottom to top: substrate (1), GaN buffer layer (2), AlGaN barrier layer (3), GaN channel layer (4), gate dielectric layer (5), passivation layer ( 6) and the source, drain, and gate electrodes, wherein the buffer layer and the channel layer are made of N-face GaN material; the GaN channel layer and the AlGaN barrier layer form a GaN/AlGaN heterojunction; the gate electrode uses a T-shaped gate and is wrapped in On both sides and above the GaN/AlGaN heterojunction, a three-dimensional grid structure is formed. The device has the advantages of good gate control ability, small ohmic contact resistance and high maximum oscillation frequency, and can be used as a small-sized microwave power device.

Although the above two solutions solve the problems of GaN multi-channel and N-surface structures respectively, there are still obvious deficiencies: the main reason is to adopt the traditional GaN-based fin structure and preparation method, that is, to prepare GaN-based three-dimensional fins first and then prepare concaves. The groove, the three-dimensional fin is not only located in the groove, but also in the area outside the groove, as shown in Figure 1 of "N-plane GaN-based fin-type high electron mobility transistor and its manufacturing method". Studies have shown that the key to the high linearity of transconductance of the device is that the three-dimensional fins are completely wrapped by the gate metal, and the above two solutions cannot meet this requirement. Therefore, the existing devices do not have high transconductance and high linearity.

How to overcome the shortcomings of the prior art has become one of the key problems to be solved urgently in the field of semiconductor device preparation technology.

Contents of the invention

The purpose of the present invention is to provide a GaN fin-type high electron mobility transistor with high linearity and its manufacturing method in order to overcome the deficiencies in the prior art. The present invention uses a simplified preparation process to make the device have both high The linearity and the highest oscillation frequency can meet the application needs of GaN high linearity microwave power devices.

According to a GaN fin-type high electron mobility transistor with high linearity proposed by the present invention, the structure of the transistor includes a substrate, a buffer layer, a barrier layer, and a passivation layer in order from bottom to top; the barrier layer One end above is provided with a source electrode and the other end is provided with a drain electrode; a passivation layer is provided above the barrier layer between the source electrode and the drain electrode, and a groove is provided in the passivation layer. There is a T-shaped gate in the groove, which is characterized in that periodically arranged GaN-based three-dimensional fins are etched on the barrier layer and buffer layer only in the area below the groove, and the GaN-based three-dimensional fins The length is equal to the length of the groove, and an isolation groove formed by etching is provided between adjacent GaN-based three-dimensional fins.

A further preferred solution of a GaN fin-type high electron mobility transistor with high linearity proposed by the present invention is:

The GaN-based three-dimensional fins (8) have a height of 10-300 nm and a width of 10-1000 nm.

A part of the T-shaped gate (9) covers both sides above the GaN-based three-dimensional fin (8), and another part of the T-shaped gate (9) covers the adjacent GaN-based three-dimensional fin (8) On the top of the isolation groove between them, another part of the T-shaped gate (9) covers the top of the passivation layer (6).

A GaN fin-type high electron mobility transistor with high linearity proposed by the present invention and a method for preparing a preferred solution include the following specific steps:

1) growing a buffer layer and a barrier layer sequentially on the substrate;

2) Photoetching source and drain patterns on the barrier layer, depositing source and drain metals, and then performing thermal annealing in _N2 atmosphere to make source and drain respectively;

3) depositing a passivation layer on the barrier layer;

4) making an active area mask on the passivation layer, and then performing device isolation by means of etching or ion implantation to form an active area;

5) making a pin mask on the passivation layer, and then etching the passivation layer by means of RIE, ICP, etc. to form grooves;

6) defining a GaN-based three-dimensional fin mask on the barrier layer limited to the region below the groove, and then dry-etching the barrier layer and the buffer layer to form periodically arranged GaN-based three-dimensional fins;

7) Defining a gate cap mask on the passivation layer, depositing gate metal by evaporation or sputtering, and peeling off to form a T-shaped gate;

8) defining an interconnection opening area mask on the passivation layer, and etching to form interconnection openings;

9) Defining an interconnection metal area mask on the passivation layer, and forming interconnection metal through evaporation and stripping processes.

Implementation principle of the present invention: the present invention is based on the existing GaN groove gate device manufacturing process. After the passivation layer is opened with a groove, a fin photolithography mask is made inside the groove, and then a GaN substrate is formed by etching. For three-dimensional fins, the T-shaped gate is finally prepared to completely wrap the GaN-based three-dimensional fins. The preparation process of the present invention can reliably ensure that the GaN-based three-dimensional fins are limited to the bottom of the groove and are completely wrapped by the gate, and there are no three-dimensional fins in other areas. Therefore, according to the principle of high transconductance linearity, the linearity of the device of the present invention is high, because Using the same T-shaped gate as the traditional process, the gate resistance is small, so the maximum oscillation frequency of the device is high.

Compared with the prior art, the present invention has significant advantages in that:

1. The process method of the present invention is simple and reliable, and only needs to add a fin preparation process on the basis of the existing GaN grooved gate process to achieve the purpose of the present invention.

2. The device of the present invention adopts a T-gate structure, which not only has high linearity, but also has a high maximum oscillation frequency, which can meet the requirements of microwave power circuits.

3. Since the degradation of transconductance under high gate voltage is suppressed, the device of the present invention has higher current driving capability and output power capability;

4. Since the GaN-based three-dimensional fins provide auxiliary sidewall heat dissipation, the device of the present invention has low thermal resistance and is suitable for high-power and high-linear microwave power devices.

Description of drawings

FIG. 1 is a schematic diagram of a three-dimensional structure of a GaN fin-type high electron mobility transistor with high linearity according to the present invention.

Fig. 2 includes Fig. 2a, Fig. 2b, Fig. 2c, Fig. 2d, Fig. 2e, Fig. 2f, Fig. 2g, which is a schematic diagram of the manufacturing process of a GaN fin-type high electron mobility transistor with high linearity in the present invention.

Fig. 3 is a schematic diagram of the DC transfer characteristics of a conventional GaN planar device.

FIG. 4 is a schematic diagram of the DC transfer characteristics of a highly linear GaN fin device manufactured according to the present invention.

detailed description

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

Referring to Fig. 1, a GaN fin-type high electron mobility transistor with high linearity proposed by the present invention is based on Group III nitride semiconductors, and its structure includes a substrate 1, a buffer layer 2, and a barrier layer 3 from bottom to top. , passivation layer 6; one end above the barrier layer 3 is provided with a source 4 and the other end is provided with a drain 5; the top of the barrier layer 3 between the source 4 and the drain 5 is provided with passivation layer 6, the passivation layer 6 is provided with a groove 7, and the groove 7 is provided with a T-shaped gate 9, and the barrier layer 3 and the buffer layer 2 in the area only under the groove 7 Several GaN-based three-dimensional fins 8 arranged periodically are etched on the top, and the GaN-based three-dimensional fins 8 only exist below the groove 7, and there are no fins in other regions. The length of the GaN-based three-dimensional fins 8 is the same as The lengths of the grooves 7 are equal, and isolation grooves formed by etching are provided between adjacent GaN-based three-dimensional fins. in:

The GaN-based three-dimensional fin 8 has a height of 10-300nm (including selection of 10nm, 100nm, 150nm, 200nm, 250nm or 300nm, etc.), and a width of 10-1000nm (including selection of 10nm, 100nm, 300nm, 600nm or 1000nm, etc.) , wherein the height of the GaN-based three-dimensional fin 8 is greater than the thickness of the barrier layer 3 .

A part of the T-shaped grid 9 covers both sides above the three-dimensional fins 8, and the other part of the T-shaped grid 9 covers the upper part of the isolation groove between adjacent GaN-based three-dimensional fins 8. Another part of the gate 9 is covered above the passivation layer 6 .

Referring to Fig. 2, a kind of preparation method of GaN fin type high electron mobility transistor with high linearity proposed by the present invention comprises the following specific steps:

1) Growing buffer layer 2 and barrier layer 3 sequentially on substrate 1, as shown in Figure 2a; wherein: the material of substrate 1 is any one of sapphire, SiC, Si, diamond or GaN self-supporting substrate ; The buffer layer 2 is one or a combination of GaN, AlGaN, AlN, and InGaN; the barrier layer 3 is one or a combination of AlGaN, InAlN, InAlGaN, and AlN.

2) Photoetching source and drain patterns on the barrier layer 3, and depositing source and drain metals, and then performing thermal annealing in _N2 atmosphere to make source 4 and drain 5 respectively, as shown in Figure 2b; wherein: The metals of the source 4 and the drain 5 include but are not limited to Ti/Al, Ti/Au, Ti/Al/W, Ti/Al/Mo/Au, Ti/Al/Ni/Au, Si/Ti Any multilayer metal in /Al/Ni/Au, Ti/Al/TiN.

3) Deposit a passivation layer 6 on the barrier layer 3, as shown in Figure 2c; wherein: the material of the passivation layer 6 is one or more combinations of SiN, SiO ₂ , SiON, AlN, with a thickness of 30-300nm (including selection of 30nm, 100nm, 150nm, 200nm, 250nm or 300nm, etc.), the growth method is plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or low pressure chemical vapor deposition ( LPCVD).

4) making an active area mask on the passivation layer 6, and then performing device isolation by means of etching or ion implantation to form an active area;

5) making a pin mask on the passivation layer 6, and then etching and removing the passivation layer 6 by means of RIE, ICP, etc., to form a groove 7, as shown in Figure 2d;

6) Define a GaN-based three-dimensional fin mask on the barrier layer 3 limited to the region below the groove 7, as shown in Figure 2e, and then dry-etch the barrier layer 3 and the buffer layer 2 to form a periodically arranged GaN-based three-dimensional fins 8, as shown in Figure 2f; wherein: the fabrication of GaN-based fin masks adopts optical lithography or electron beam direct writing, and the etching of barrier layer 3 and buffer layer 2 adopts dry methods such as RIE and ICP etching method;

7) Define a gate cap mask on the passivation layer 6, deposit a gate metal by evaporation or sputtering, and peel off to form a T-shaped gate 9, as shown in Figure 2g; wherein: the gate metal includes but is not limited to Ni/Au, Ni Any multilayer metal in /Au/Ni, Pt/Au, Ni/Pt/Au, W/Ti/Au, Ni/Pt/Au/Pt/Ti, TiN/Ti/Al/Ti/TiN, so The thickness of the gate metal is 50-700nm (including selection of 50nm, 100nm, 300nm, 500nm or 700nm, etc.).

8) defining an interconnection opening area mask on the passivation layer 6, and etching to form interconnection openings;

9) Defining an interconnection metal area mask on the passivation layer 6, and forming interconnection metal by evaporation and lift-off processes.

According to the structures and manufacturing methods described above, the present invention provides the following two embodiments, but is not limited to these embodiments.

Example 1: Preparation of SiC substrate, the buffer layer is AlN/GaN, the barrier layer is AlGaN, the passivation layer is SiN, the width of GaN-based three-dimensional fins is 100nm, and the gate metal is Ni/Au/Ni, which has high linearity degree of GaN fin high electron mobility transistors, the process is:

1) On the SiC substrate 1, using metal organic chemical vapor deposition technology MOCVD, first grow 100nm AlN at 1050°C, and then grow a 2μm unintentionally doped GaN layer at 1000°C to form a buffer layer 2, Subsequently, an AlGaN barrier layer 3 with a thickness of 22 nm is grown on the buffer layer 2 with an Al composition of 30%.

2) Make a photolithographic mask on the barrier layer 3, then use electron beam evaporation to deposit a metal stack, and obtain isolated metal blocks at both ends of it through a lift-off process, and finally perform rapid thermal annealing in an _N2 atmosphere to form a source pole 4 and drain 5. The deposited metals are respectively Ti, Al, Ni and Au from bottom to top, and their thicknesses are 20nm, 150nm, 60nm and 50nm respectively. The conditions used for electron beam evaporation are: vacuum degree≦2.0×10 ^-6 Torr, deposition rate less than The process conditions of rapid thermal annealing are: temperature 840°C, time 30s.

3) Using PECVD technology to deposit SiN on the barrier layer 3 to form a passivation layer 6; the deposition process conditions are: the gases are respectively SiH ₄ , NH ₃ , He and N ₂ , and the flow rates are 8 sccm, 2 sccm, 100 sccm and 200 sccm respectively , the pressure is 500mTorr, the temperature is 260°C, the power is 25W, and the thickness of the passivation layer is 100nm.

4) Fabricate an active area mask on the passivation layer 6, and then use ion implantation to isolate devices to form an active area. The implantation conditions are: B ⁺ ions, current 10μA, energy 100KeV, dose 5e14.

5) A mask is made on the upper part of the passivation layer 6, and a groove 7 is opened on the passivation layer 6 between the source 4 and the drain 5 by using the plasma enhanced etching technique RIE. The process conditions for etching the groove are as follows: the gas is SF ₆ , the flow rate is 20 sccm, the pressure is 0.2 Pa, and the time is 200 s.

6) Use ZEP520 glue to make a GaN-based three-dimensional fin mask inside the groove 7, etch AlGaN/GaN by ICP dry method, remove the ZEP520 glue mask, and form a GaN-based three-dimensional fin 8 with a width of 100 nm; where: The etching process conditions are as follows: the gases are BCl ₃ and Cl ₂ , the flow rates are 25 sccm and 5 sccm respectively, the pressure is 30 mTorr, the temperature is 25°C, the upper electrode power is 100 W, the lower electrode is 3 W, the etching time is 5 minutes, and the etching depth is 50 nm.

7) Make a gate mask on the upper part of the passivation layer 6, deposit a metal stack by electron beam evaporation technology, and form a T-shaped gate 9 by using a lift-off process; wherein: the process conditions for depositing a metal stack are: vacuum degree ≦1.5×10 ^-6 Torr, the deposition rate is less than Wherein: the deposited metal stacks are Ni, Au and Ni from bottom to top, and the thicknesses are 20nm, 500nm and 30nm respectively.

8) Defining a photolithography mask for the interconnection opening area on the passivation layer 6, and forming interconnection openings by RIE dry etching. The etching process conditions are as follows: the gas is SF ₆ , the flow rate is 20 sccm, the pressure is 0.2 Pa, and the time is 200 s.

9) Define an interconnection metal region mask on the passivation layer 6, and form interconnection metal through evaporation and lift-off processes. The process conditions for depositing metal stacks are: vacuum degree≦1.5×10 ^-6 Torr, deposition rate less than The deposited metal stacks are Ti and Au from bottom to top, and the thicknesses are 30nm and 500nm respectively.

Example 2: Prepare Si substrate, the buffer layer is AlN/AlGaN/GaN layer, the barrier layer is AlN/InAlN, the passivation layer is SiO ₂ , the GaN-based three-dimensional fin width is 400nm, and the gate metal is TiN/Ti/ Al/Ti/TiN GaN fin-type high electron mobility transistor with high linearity, the process is:

1) On the Si substrate, using metal organic chemical vapor deposition technology MOCVD, first grow 200nm AlN at 1050°C, and then grow a 1μm unintentionally doped AlGaN layer (Al group 15%) and 500nm GaN layer to form a buffer layer 2, and then grow an AlN layer with a thickness of 1nm and 8nm InAlN on the buffer layer 2 at 800°C to form a barrier layer 3 with an Al composition of 83%.

2) Make a photolithographic mask on the barrier layer 3, then use electron beam evaporation to deposit a metal stack, and obtain isolated metal blocks at both ends of it through a lift-off process, and finally perform rapid thermal annealing in an _N2 atmosphere to form a source Electrode 4 and drain 5; the deposited metals are Ti, Al, and TiN from bottom to top, and their thicknesses are 20nm, 200nm, and 100nm respectively; the conditions used for electron beam evaporation are: vacuum degree≦2.0×10 ^-6 Torr , the deposition rate is less than The technological conditions of rapid thermal annealing are: temperature 550° C., time 90 s.

3) Depositing SiO ₂ on the barrier layer 3 to form a passivation layer 6 by using PECVD technology. The deposition process conditions are: the gases are SiH ₄ and N ₂ O respectively, the flow rates are 120 sccm and 200 sccm respectively, the pressure is 500 mTorr, the temperature is 320° C., the power is 35 W, and the thickness of the passivation layer is 150 nm.

4) The 4th step of embodiment 2 is the same as the 4th step of embodiment 1.

5) Make a mask on the top of the passivation layer 6, and use the plasma enhanced etching technology RIE to open a groove 7 on the passivation layer 6 between the source electrode 4 and the drain electrode 5; wherein: the process of etching the groove The conditions are: the gas is SF ₆ , the flow rate is 20 sccm, the pressure is 0.2 Pa, and the time is 600 s.

6) Fabricate a fin mask inside the groove 7 by deep ultraviolet lithography, and dry-etch AlGaN/GaN by ICP, remove the photoresist mask, and form a fin 8 with a width of 400nm. Among them: the etching process conditions are: the gas is BCl ₃ and Cl ₂ respectively, the flow rate is 25sccm and 5sccm respectively, the pressure is 30mTorr, the temperature is 25°C, the upper electrode power is 100W, the lower electrode is 3W, the etching time is 5 minutes, and the etching depth 50nm.

7) Fabricate a gate mask on the upper part of the passivation layer 6, deposit a metal stack by using electron beam evaporation technology, and form a T-shaped gate 9 by using a lift-off process. Among them: the process conditions for depositing metal stacks are: vacuum degree≦1.5×10 ^-6 Torr, deposition rate less than The deposited metal stacks are TiN/Ti/Al/Ti/TiN from bottom to top, and the thicknesses are 20nm, 30nm, 300nm, 30nm and 100nm respectively.

8) On the passivation layer 6, define a photolithography mask for the interconnection opening area, and form interconnection openings by RIE dry etching; wherein: the etching process conditions are: the gas is SF ₆ , the flow rate is 20 sccm, and the pressure is 0.2 Pa. The time is 600s.

9) The 9th step of embodiment 2 is the same as the 9th step of embodiment 1.

The effect of the present invention can be further illustrated by Fig. 3 and Fig. 4 .

Figure 3 shows the DC transfer characteristics of GaN planar devices. It can be seen that the transconductance of the device exhibits typical peak characteristics, the maximum current is 1.2A/mm, and the maximum transconductance G _m is 0.48S/mm. Figure 4 shows the DC transfer characteristics of the highly linear GaN fin device prepared according to the present invention. The transconductance Gm of the device is flatter, the linearity is greatly improved, and the maximum current is 2A/mm, and the maximum transconductance Gm is _{0.74S /} mm . From the above comparison, it can be seen that the maximum current and transconductance of the highly linear GaN fin device of the present invention are much higher than those of the planar device, and the transconductance linearity is greatly improved.

The descriptions not involved in the specific embodiments of the present invention belong to the well-known technologies in the art, and may be implemented with reference to the known technologies.

The invention has been verified through repeated experiments and has achieved satisfactory trial results.

The above specific implementation methods and examples are specific support for the technical idea of a GaN fin-type high electron mobility transistor with high linearity and its manufacturing method proposed by the present invention, and cannot limit the protection scope of the present invention. The technical ideas proposed by the invention and any equivalent changes or equivalent changes made on the basis of the technical solution still belong to the scope of protection of the technical solution of the present invention.

Claims (9)

1. A GaN fin type high electron mobility transistor with high linearity, the structure of the transistor includes a substrate (1), a buffer layer (2), a barrier layer (3), and a passivation layer from bottom to top (6); one end above the barrier layer (3) is provided with a source (4) and the other end is provided with a drain (5); between the source (4) and the drain (5) A passivation layer (6) is provided above the barrier layer (3), a groove (7) is arranged in the passivation layer (6), and a T-shaped gate (9) is arranged in the groove (7). ), characterized in that periodically arranged GaN-based three-dimensional fins (8) are etched only on the barrier layer (3) and the buffer layer (2) in the area below the groove (7), the The length of the GaN-based three-dimensional fins (8) is equal to the length of the groove (7), and isolation grooves formed by etching are provided between adjacent GaN-based three-dimensional fins (8). 2. A GaN fin high electron mobility transistor with high linearity according to claim 1, characterized in that the GaN-based three-dimensional fin (8) has a height of 10-300 nm and a width of 10-300 nm. 1000nm. 3. A kind of GaN fin-type high electron mobility transistor with high linearity according to claim 2, is characterized in that, a part of described T-type gate (9) covers on described GaN base three-dimensional fin ( 8) on both sides of the top, the other part is covered above the isolation groove between adjacent GaN-based three-dimensional fins (8), and another part of the T-shaped gate (9) is covered on the passivation layer (6) above. 4. A method for manufacturing a GaN fin-type high electron mobility transistor with high linearity according to any one of claims 1-3, comprising the following specific steps: 1) growing a buffer layer (2) and a barrier layer (3) sequentially on the substrate (1); 2) Photoetching source and drain patterns on the barrier layer (3), depositing source and drain metals, and then performing thermal annealing in _N2 atmosphere to make source (4) and drain (5) respectively; 3) depositing a passivation layer (6) on the barrier layer (3); 4) making an active area mask on the passivation layer (6), and then performing device isolation by etching or ion implantation to form an active area; 5) making a pin mask on the passivation layer (6), and then etching and removing the passivation layer (6) by RIE or ICP to form a groove (7); 6) defining a GaN-based three-dimensional fin mask on the barrier layer (3) limited to the region below the groove (7), and then dry etching the barrier layer (3) and the buffer layer (2), Forming periodically arranged GaN-based three-dimensional fins (8); 7) defining a gate cap mask on the passivation layer (6), depositing gate metal by evaporation or sputtering, and peeling off to form a T-shaped gate (9); 8) defining an interconnection opening area mask on the passivation layer (6), and etching to form interconnection openings; 9) Defining an interconnection metal region mask on the passivation layer (6), and forming interconnection metal through evaporation and stripping processes. 5. A method for manufacturing a GaN fin-type high electron mobility transistor with high linearity according to claim 4, wherein the material of the substrate (1) in step 1) is sapphire, SiC, Si Any one of , diamond or GaN self-supporting substrates; the buffer layer (2) is one or more combinations of GaN, AlGaN, AlN, InGaN; the barrier layer (3) is AlGaN, InAlN, InAlGaN, AlN one or a combination of several. 6. A method for manufacturing a GaN fin-type high electron mobility transistor with high linearity according to claim 5, characterized in that, step 2) the metal of the source (4) and drain (5) All contain any of Ti/Al, Ti/Au, Ti/Al/W, Ti/Al/Mo/Au, Ti/Al/Ni/Au, Si/Ti/Al/Ni/Au, Ti/Al/TiN A multilayered metal. 7. A kind of manufacturing method of GaN fin type high electron mobility transistor with high linearity according to claim 6, is characterized in that, the material of the passivation layer (6) described in step 3) is SiN, SiO ₂ , SiON, AlN or a combination of several, the thickness of the passivation layer (6) is 30-300nm, the growth method of the passivation layer (6) is plasma enhanced chemical vapor deposition, atomic layer deposition deposition or Low pressure chemical vapor deposition. 8. A method for manufacturing a GaN fin-type high electron mobility transistor with high linearity according to claim 7, characterized in that, step 6) the fabrication of the fin mask adopts optical lithography or electron beam Direct writing method, RIE or ICP method for dry etching. 9. A method for manufacturing a GaN fin-type high electron mobility transistor with high linearity according to claim 8, wherein the gate metal in step 7) includes Ni/Au, Ni/Au/Ni, Any multilayer metal in Pt/Au, Ni/Pt/Au, W/Ti/Au, Ni/Pt/Au/Pt/Ti, TiN/Ti/Al/Ti/TiN, the thickness of the gate metal 50-700nm.