CN102646705A - MIS gate GaN-based enhanced HEMT device and manufacturing method - Google Patents

Abstract

The invention discloses a metal insulated semi-conductor (MIS) grid GaN base enhancing high electro mobility transistor (HEMT) device and a manufacture method, which mainly solve the problems that the existing GaN base enhancing device is low in threshold voltage, poor in controllability and low in reliability. The device comprises a substrate (1), a transition layer (2), a GaN main buffering layer (3) and an N-type AlGaN main barrier layer (4). A source (9) and a drain (10) are arranged on two sides of the top end of the N-type AlGaN main barrier layer (4), a grid (13) is arranged in the middle of the top end of the source (9) and the drain (10), a groove (5) is etched in the middle of the GaN main buffering layer (3), the bottom of the groove is a 0001 polarity plane, a lateral side of the groove is a non-0001 plane, and an inner wall of the groove extends outwards to form a GaN auxiliary buffering layer (6), a AlGaN auxiliary barrier layer (7) and a medium layer (8). The grid (13) is deposited on the medium layer (8). The MIS grid GaN base enhancing HEMT device and the manufacture method have the advantages of being high in threshold voltage, good in regulation performance, high in current density, good in pinching-off performance, simple and mature in manufacture process and good in repeatability and can be used for high temperature high power application situations and digital circuits.

Description

MIS gate GaN-based enhanced HEMT device and manufacturing method

technical field

The invention belongs to the technical field of microelectronics and relates to a semiconductor device, in particular to an MIS gate GaN-based enhanced HEMT device and a manufacturing method, which can be used in high-temperature and high-power applications and form basic units of digital circuits.

Background technique

With the development of modern weaponry and aerospace, nuclear energy, communication technology, automotive electronics, and switching power supplies, higher requirements are placed on the performance of semiconductor devices. As a typical representative of wide bandgap semiconductor materials, GaN-based materials have the characteristics of large bandgap width, high electron saturation drift velocity, high critical breakdown field strength, high thermal conductivity, good stability, corrosion resistance, and radiation resistance. Used in the production of high temperature, high frequency and high power electronic devices. In addition, GaN also has excellent electronic properties, and can form a modulation-doped AlGaN/GaN heterostructure with AlGaN. This structure can obtain an electron mobility higher than 1500 cm ² /Vs at room temperature, and up to 3×10 ⁷ cm /s peak electron velocity and 2×10 ⁷ cm/s saturation electron velocity, and obtains a two-dimensional electron gas density higher than that of the second-generation compound semiconductor heterostructure, and is known as an ideal material for the development of microwave power devices . Therefore, the high electron mobility transistor HEMT based on AlGaN/GaN heterojunction has a very good application prospect in microwave high-power devices.

Due to the unique advantages of AlGaN/GaN heterojunction, the growth of AlGaN/GaN heterojunction materials and the development of AlGaN/GaN HEMT devices have always occupied the main position in the research of GaN electronic devices. However, most of the research work on GaN-based electronic devices in the past decade has focused on depletion-mode AlGaN/GaN HEMT devices. Type devices become very difficult, so the study of high-performance AlGaN/GaN enhancement-mode HEMTs is of great significance.

AlGaN/GaN enhanced HEMT has broad application prospects. First of all, GaN-based materials are known as ideal materials for the development of microwave power devices, and enhanced devices can greatly reduce the complexity and cost of circuits due to the reduction of negative voltage sources in circuits such as microwave power amplifiers and low-noise amplifiers. And the AlGaN/GaN enhanced HEMT device has good circuit compatibility in microwave high-power devices and circuits. At the same time, the development of enhanced devices makes it possible to monolithically integrate digital circuits of depletion-mode/enhanced devices. Moreover, in terms of power switching applications, AlGaN/GaN enhanced HEMTs also have great application prospects. Therefore, research on high-performance AlGaN/GaN enhancement-mode HEMT devices has received great attention.

At present, there are many reports on AlGaN/GaN enhanced HEMTs both domestically and internationally. Due to the immature P-type Mg doping process technology, the Mg activation energy in GaN-based materials is high and the ionization rate is low, resulting in low hole concentration and high mobility in the device. Therefore, the current international research on AlGaN/GaN enhanced HEMT It is not based on the method of P-type Mg doping, but other new technologies are used. Currently, the following technologies are mainly reported:

1. F ion implantation technology, that is, plasma implantation technology based on fluoride CF4. Yong Cai et al. of Hong Kong University of Science and Technology successfully developed an enhanced HEMT device based on F ion implantation technology. The device passes through the AlGaN/GaN HEMT gate F ions are implanted into the AlGaN barrier layer. Due to the strong negative charge of F ions, the F ions in the barrier layer can provide stable negative charges, and thus can effectively deplete the strong two-dimensional electron gas in the channel region. When AlGaN When the number of F ions in the barrier layer reaches a certain amount, the two-dimensional electron gas in the channel under the gate is completely exhausted, thereby realizing an enhanced HEMT device. However, the F-implantation technology will inevitably introduce material damage, and the controllability of the device threshold voltage is not high. The thin layer carrier concentration of the device is as high as 1.3×10 ¹³ cm ^-2 at room temperature, the mobility is 1000cm ² /Vs, the threshold voltage reaches 0.9V, and the maximum drain current reaches 310mA/mm. See Yong Cai, Yugang Zhou, Kevin J. Chen and Kei May Lau, "High-performanceenhancement-mode AlGaN/GaN HEMTs using fluoride-based plasma treatment", IEEE Electron Device Lett, Vol.26, No.7, JULY 2005.

2. Non-polar or semi-polar GaN materials realize enhanced devices. Masayuki Kuroda et al. successfully used a-plane (1120) n-AlGaN/GaN HEMTs on r-plane (1102) sapphire to achieve device enhancement. Due to non-polar Due to the lack of polarization effect of polar or semi-polar materials, the two-dimensional electron gas concentration is small or even non-existent, so AlGaN/GaN HEMT devices based on non-polar or semi-polar materials have enhanced characteristics. The reported threshold voltage is -0.5V, and the threshold voltage of the device can be further increased by reducing the dopant concentration, but the device characteristics are not good, the electron mobility is only 5.14cm ² /Vs, and the sheet resistance at room temperature is very large. And its gate leakage reaches 1.1×10 ^-5 A/mm when Vgs=-10V. See literature Masayuki Kuroda, Hidetoshi Ishida, Tetsuzo Ueda, and Tsuyoshi Tanaka, "Nonpolar (11-20) plane AlGaN/GaN heterojunction field effect transistors on (1-102) plane sapphire", Journal of Aplied Phisics, Vol.102, No. 9, November 2007.

3. Thin barrier layer technology. In 1996, M.Asif Khan and others first realized the AlGaN/GaN enhanced HEMT device with 10nm AlGaN thin barrier layer technology. The thin barrier layer AlGaN/GaN enhanced HEMT device is due to the potential The thickness of the barrier layer is thinned, its polarization effect is weakened, and the concentration of two-dimensional electron gas in the channel caused by the polarization effect is reduced, so that the threshold voltage of the device is shifted to the right. But the results they obtained are not ideal, the peak transconductance is only 23mS/mm. See M.Asif Khan, Q.Chen, C.J.Sun, J.W.Yang, and M.Blasingame, "Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors", Appl.Phys.Lett.Vol.68, No.4, January 1996.

4. Groove gate technology, W.B.Lanford et al. used groove gate technology to make an enhanced device with a threshold voltage of 0.47V through MOCVD. The device structure includes from bottom to top: SiC substrate, nucleation layer, 2um thick GaN, 3nm thick AlGaN, 10nm thick n-AlGaN, 10nm thick AlGaN. After ohmic annealing, instead of directly evaporating the gate metal electrode, a groove is etched in the pre-grown gate area by dry ICP-RIE method, and then rapid thermal annealing is performed in a nitrogen atmosphere at 700 °C, and then the groove is etched. A Ni/Au Schottky contact gate electrode is made on the gate window. The trench gate technology makes the barrier layer under the gate thinner by etching the barrier layer under the gate to a certain depth, thereby reducing the concentration of 2DEG under the gate, while the carrier concentration in the source and drain regions remains unchanged at a relatively large value. It can not only realize the enhanced characteristics of the device, but also ensure a certain current density. The epitaxial growth of enhancement-mode devices realized by trench gate technology is easy to control, but its controllability is poor, and the etching process will cause damage. See W.B.Lanford, T.Tanaka, Y.Otoki and I.Adesida, "Recessed-gate enhancement-mode GaN HEMT with highthreshold voltage", Electronics Letrers, Vol.41, No.7, March 2005.

5. AlGaN/GaN grooved MIS gate HFET structure, Tohru Oka et al. used the grooved MIS gate HFET structure to achieve a threshold voltage up to 5.2V. The epitaxial layer structure is from bottom to top: Si substrate, buffer layer, after 800nm Al _0.05 Ga _0.95 N buffer layer, 40nm thick GaN channel layer, 34nm thick Al _0.25 Ga _0.75 N, 1nm thick AlN barrier layer, 1nm thick GaN cap layer. During the manufacturing process of the device, the barrier layer under the gate window is completely etched by the inductively coupled plasma ICP based on SiCl ₄ /Cl ₂ , and after five minutes of annealing in the N ₂ atmosphere at 500 ° C, the plasma-enhanced chemical vapor phase is used to Deposit PECVD to etch a layer of SiN with a thickness of 20nm as the gate dielectric, which is also a passivation layer, and then deposit W-based metal as the gate metal. In this way, the MIS gate device is formed, because there is no heterojunction structure in the region under the gate, so there is no two-dimensional electron gas, so a high threshold enhancement type can be realized, but this structure also has certain problems, because the heterojunction under the gate is completely covered Etched away, resulting in low device mobility, low current density, and high on-resistance. References Tohru Oka, To mohiro Nozawa, "AlGaN/GaN Recessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications", IEEE Electron Device Lett, VOL.29, NO.7, JULY 2008.

To sum up, at present, AlGaN/GaN enhancement mode HEMT devices in the world are mainly formed based on trench gate technology and fluorine ion implantation technology, which have the following shortcomings:

First, there is a trade-off relationship between threshold voltage and current density, and it is difficult to achieve coexistence of high threshold voltage and high current density, and the regulation of threshold voltage is poor;

Second, whether etching to form trench gates or fluorine ion implantation will cause damage to the material, although a certain amount of damage can be eliminated after annealing, the remaining damage will still affect device performance and reliability. At the same time, the repeatability of this process is still low. not tall;

Third, when forming short-channel devices for microwave applications, it is necessary to use high-end process equipment such as electron beam direct writing to produce short gate lengths, and the process is relatively difficult.

Contents of the invention

The purpose of the present invention is to overcome the defects of the above-mentioned prior art, and propose a metal insulator semiconductor MIS gate GaN-based enhanced high electron mobility transistor HEMT device and its manufacturing method from the perspective of device vertical structure optimization to reduce process difficulty and avoid device The damage caused during the manufacturing process increases the threshold voltage of the device, enhances the controllability of the threshold voltage of the device, and improves the reliability of the device.

In order to achieve the above object, the device of the present invention includes: a substrate, a transition layer, a GaN main buffer layer, an N-type AlGaN main barrier layer, a source and a drain on both sides of the top of the N-type AlGaN main barrier layer, and a gate in the middle. The electrode is characterized by: a groove is etched in the middle of the GaN main buffer layer, the bottom surface of the groove is a 0001 polar surface, the side of the groove is a non-0001 surface, and the inner wall of the groove is epitaxially formed with a GaN sub-buffer layer, AlGaN The sub-barrier layer and the dielectric layer, and the gate electrode is deposited on the dielectric layer.

The main two-dimensional electron gas 2DEG channel is formed at the interface between the GaN main buffer layer and the AlGaN main barrier layer, and the channel is located on both sides of the groove; the GaN sub-buffer layer and the AlGaN sub-barrier layer in the groove The interface forms a sub-two-dimensional electron gas 2DEG channel.

The horizontal position of the secondary 2DEG channel is lower than the horizontal position of the main 2DEG channel.

The main barrier layer is N-type doped with a doping concentration of 6×10 ¹⁹ cm ^-3 .

In order to achieve the above object, the metal insulator semiconductor MIS gate GaN-based enhanced HEMT device and its manufacturing method of the present invention comprise the following steps:

(1) Pretreating the substrate surface in the reaction chamber;

(2) Epitaxial growth of AlGaN/GaN epitaxial layer on the substrate, in which the thickness of GaN is 1um~3um, the thickness of N-type doped Al _x Ga _1-x N barrier layer is 14nm~30nm, and the molar content of Al element x is 20%-35%;

(3) Deposit a mask dielectric layer on the epitaxial layer, then perform photolithography, and etch the dielectric layer on the epitaxial layer by wet etching, and form a 0.5um-long concave on the epitaxial layer groove;

(4) Photoetch the groove area, and use the reactive ion etching RIE method to etch the AlGaN/GaN epitaxial layer in the groove area, and the etching depth is 35nm-140nm;

(5) Keep the mask dielectric layer outside the groove, pass the etched epitaxial layer through the metal organic chemical vapor deposition MOCVD reaction chamber, and grow a 20nm-100nm thick GaN layer and A 14nm-30nm thick AlGaN layer, a 10nm-50nm thick GaN layer and a 7nm-15nm thick AlGaN layer are grown along the side of the groove;

(6) removing the mask dielectric layer;

(7) Depositing a gate dielectric layer with a thickness of 20nm to 60nm by chemical vapor deposition CVD or physical vapor deposition PVD on the surface of the material from which the mask dielectric layer has been removed;

(8) On the gate dielectric layer, the source and drain regions are first photoetched, and then the source and drain windows are etched;

(9) On the surface of the material after photolithography, the metal in ohmic contact is evaporated by electron beam evaporation technology, and the source and drain contact electrodes are formed after stripping and annealing;

(10) Lithographically etch the gate area on the gate dielectric, and use electron beam evaporation technology to evaporate the gate metal, and form a metal insulator semiconductor MIS gate after stripping;

(11) Photolithography has formed the device surface of the source, drain and gate, obtained thickened electrode patterns, and used electron beam evaporation technology to thicken the electrodes to complete the device production.

The present invention has the following advantages:

1) It has good enhancement characteristics and high threshold voltage.

Since the AlGaN/GaN heterojunction interface in the device structure adopted by the present invention is a non-planar structure, the bottom surface of the groove is a 0001 polar surface, and the side surface of the groove is a non-0001 surface, and the non-0001 surface AlGaN epitaxial along the groove side direction /GaN heterojunction reduces or even eliminates the polarization effect, so that the concentration of two-dimensional electron gas formed at the interface of the heterojunction is very low, or even no two-dimensional electron gas, so only a sufficiently high positive voltage is applied to the gate. Sufficient two-dimensional electron gas is induced in the non-0001-plane heterojunction channel epitaxial in the direction of the groove side, and the applied higher gate voltage can form a higher horizontal drift in the sub-GaN buffer layer on the side of the groove The electric field enables electrons to conduct electricity through the main 2DEG channel layer on both sides of the groove, the two-dimensional electron gas channel on the side of the groove, and the secondary 2DEG channel layer on the bottom surface of the groove, realizing the enhanced working mode of the device, and obtain a high threshold voltage.

2) The threshold voltage has good controllability.

The device of the present invention can use different process conditions to epitaxially GaN sub-buffer layers with different thicknesses in the groove side direction during the realization of the process, and the electric field strength in the buffer layer caused by different GaN sub-buffer layer thicknesses The difference of the difference determines the threshold voltage of the device to a large extent, so the threshold voltage of the device can be adjusted by changing the thickness of the GaN sub-buffer layer in the design, such as increasing the thickness of the GaN sub-buffer layer, so that under the same gate voltage, The electric field strength in the GaN subbuffer layer is reduced, thereby increasing the device threshold voltage.

3) It has a high current density.

Since the AlGaN barrier layer on the inner wall of the groove of the device of the present invention and the AlGaN barrier layer outside the groove are not grown at the same time, the AlGaN barrier layer outside the groove is doped with N-type or even N+ type, which can not only greatly reduce the ohmic resistance of the device Contact resistance, and can greatly reduce the series resistance of the source and drain, thus increasing the current density of the device.

4) It has good pinch-off characteristics.

Because the GaN sub-buffer layer on the side of the groove can block the flow of electrons in the channel when the gate voltage is zero, the device of the present invention can realize extremely low off-state current.

5) Since the gate of the present invention adopts the metal insulator semiconductor MIS gate, the breakdown voltage can be increased while the gate leakage current can be reduced, and a higher gate voltage swing can be obtained.

6) The process is simple and mature, the repeatability is good, and the reliability of the device is high.

The process steps in the device manufacturing method of the present invention are relatively mature at home and abroad, and the process flow is relatively simple, low in cost, and fully compatible with the mature depletion-type AlGaN/GaN HEMT device manufacturing process. In addition, the present invention adopts a dry etching method for groove gate etching, and in the subsequent high-temperature secondary growth, the surface damage caused by etching can be repaired to a certain extent, so as to reduce the impact of etching damage on device performance. and reliability effects. Compared with the currently commonly used groove gate etching method at home and abroad, the invention can more effectively avoid material damage caused by etching, and the reliability of the device is higher.

Description of drawings

Fig. 1 is MIS gate GaN-based enhancement mode HEMT device and manufacturing method of the present invention;

Fig. 2 is the preparation and fabrication method of MIS gate GaN-based enhanced HEMT device according to the present invention.

Detailed ways

Referring to Fig. 1, the MIS gate GaN-based enhanced HEMT device of the present invention includes: substrate 1, AlN transition layer 2, GaN main buffer layer 3, N-type _{AlxGa1 -xN} main barrier layer 4, groove 5. GaN sub-buffer layer 6, Al _x Ga _1-x N sub-barrier layer 7, dielectric layer 8, source 9, drain 10 and gate 13; AlN transition layer 2 epitaxially on substrate 1; GaN main The buffer layer 3 is on the AlN transition layer; the N-type Al _x Ga _1-x N main barrier layer 4 is on the GaN main buffer layer 3, and 0≤x≤1, and the doping concentration is 6×10 ¹⁹ cm ^-3 ; On both sides of the top of the N-type AlGaN main barrier layer 4 are the source 9 and the drain 10, and the middle is the gate 13; above the N-type _{AlxGa1 -xN} main barrier layer 4 is a dielectric layer 8, and the thickness of the dielectric layer is 20nm to 60nm; the groove 5 is etched in the middle of the GaN main buffer layer 3, the depth of the groove is 35nm to 140nm, the bottom of the groove after etching is the GaN main buffer layer 3, which is a 0001 polar plane, and the groove The side is a non-0001 plane; the GaN sub-buffer layer 6 is located on the groove 5; the Al _x Ga _1-x N sub-barrier layer 7 is located above the GaN sub-buffer layer 6; the thickness of the GaN sub-buffer layer 6 is above the bottom of the groove 5 20nm-100nm in the direction of the groove 5, 10nm-50nm in the horizontal direction of the side wall of the groove 5; the thickness of the _{AlxGa1 -xN} sub-barrier layer 7 is 14nm-30nm in the upward direction of the bottom of the groove 5 , 7nm-15nm in the horizontal direction of the side wall of the groove 5; the dielectric layer 8 is above the Al _x Ga _1-x N sub-barrier layer 7; the gate electrode 13 is on the dielectric layer 8; the GaN main buffer layer 3 and the Al The main two-dimensional electron gas 2DEG channel 11 is formed at the interface of the _x Ga _1-x N main barrier layer 4, and the channel 11 is located on both sides of the groove 5; the epitaxial GaN sub-buffer layer 6 and the Al _x The interface of the Ga _1-x N sub-barrier layer 7 forms a secondary 2DEG channel 12 , and the horizontal position of the secondary 2DEG channel 12 is lower than the horizontal position of the main 2DEG channel 11 .

Referring to FIG. 2 , the method for fabricating a MIS gate GaN-based enhancement HEMT device according to the present invention provides the following three embodiments.

Example 1

The transition layer is made of AlN, the thickness of the GaN main buffer layer is 1um, the thickness of the Al _0.35 Ga _0.65 N main barrier layer is 14nm, the groove etching depth is 35nm, and the thickness of the GaN secondary buffer layer is 20nm in the upward direction of the bottom of the groove. The thickness in the horizontal direction on the side of the groove is 10nm, the thickness of the Al _0.35 Ga _0.65 N sub-barrier layer is 14nm in the upward direction on the bottom of the groove, the thickness in the horizontal direction on the side of the groove is 7nm, and the thickness of the gate dielectric layer is 20nm MIS gate GaN-based enhancement mode HEMT device, the steps are:

Step 1: Place the C-plane sapphire substrate in the reaction chamber of the MOCVD equipment, evacuate the vacuum of the reaction chamber to below 1×10 ^-2 Torr, and process the sapphire substrate under the protection of the mixed gas of hydrogen and ammonia. For heat treatment and surface nitriding, the heating temperature is 1050° C., the pressure is 20 Torr, the flow rate of hydrogen gas is 1500 sccm, and the flow rate of ammonia gas is 1500 sccm.

In step 2, an AlN transition layer with a thickness of 150 nm is epitaxially grown on the sapphire substrate by MOCVD technology, as shown in FIG. 2( a ).

The process conditions used for the epitaxial AlN transition layer are: temperature 980° C., pressure 20 Torr, hydrogen gas flow 300 sccm, ammonia gas flow 1500 sccm, aluminum source flow 30 sccm.

Step 3, using MOCVD technology to epitaxially grow a GaN main buffer layer with a thickness of 1um on the transition layer, as shown in Figure 2(b).

The process conditions adopted for the epitaxy are: the temperature is 920° C., the pressure is 40 Torr, the hydrogen gas flow rate is 500 sccm, the ammonia gas flow rate is 5000 sccm, and the gallium source flow rate is 220 sccm.

Step 4: epitaxial N-type doped Al _0.35 Ga _0.65 N main barrier layer with a thickness of 14nm on the main buffer layer by MOCVD technology, and achieved a doping concentration of 6×10 ¹⁹ cm by injecting silane SiH ₄ during the growth process ^-3 N-type doping, so that the AlGaN/GaN heterojunction is formed on the AlN transition layer, and the main two-dimensional electron gas 2DEG is formed on the GaN side of the AlGaN/GaN heterojunction interface, forming an epitaxial wafer The structure is shown in Figure 2(c).

The process conditions used for epitaxy are: temperature 920°C, pressure 40 Torr, hydrogen gas flow 500 sccm, ammonia gas flow 5000 sccm, aluminum source flow 10 sccm, gallium source flow 40 sccm.

Step five, after cleaning the above-mentioned epitaxial wafer, deposit a layer of SiN mask dielectric layer on the surface by using plasma enhanced chemical vapor deposition PECVD technology, as shown in Fig. 2(d).

Step 6: On the surface of the epitaxial wafer on which the mask dielectric layer is deposited, firstly carry out positive resist and soft baking; then form the groove window required for etching through exposure and development, and finally use wet etching method to etch away SiN mask dielectric layer under the groove window, and remove residual photoresist on the SiN mask dielectric layer with acetone.

Step 7: Photo-etch the groove window on the epitaxial wafer after deglue, and use reactive ion etching RIE equipment to etch the AlGaN/GaN heterojunction under the groove window to form a 0001 polar surface on the bottom surface and a non-polar surface on the side surface. The groove structure of the 0001 plane is shown in Fig. 2(e).

The etching uses chlorine gas Cl ₂ with a flow rate of 15 sccm, a power of 200 W, a pressure of 10 mT, and an etching depth of 35 nm.

Step eight, remove the etched positive resist with acetone, and clean the surface of the epitaxial wafer.

Step 9: Evacuate the vacuum of the reaction chamber to below 1×10 ^-2 Torr, and heat-treat the cleaned epitaxial wafer under the protection of the mixed gas of hydrogen and ammonia. The heating temperature is 1000°C, the pressure is 20 Torr, and hydrogen The flow rate is 1500 sccm, and the flow rate of ammonia gas is 1500 sccm.

Step 10, repeat step 3, and grow GaN sub-buffer layers of different thicknesses on the inner wall of the groove for the second time, that is, the thickness of the GaN sub-buffer layer grown vertically on the bottom of the groove is 20nm, and the GaN sub-buffer layer grown horizontally on the side of the groove The thickness of the secondary buffer layer is 10nm, as shown in Figure 2(f).

Step 11: Secondary growth of Al _0.35 Ga _0.65 N sub-barrier layers with different thicknesses on the GaN sub-buffer layer using MOCVD technology, that is, the thickness of the Al _0.35 Ga _0.65 N sub-barrier layer grown vertically on the bottom of the groove is The thickness of the Al _0.35 Ga _0.65 N sub-barrier layer grown on the side of the groove in the horizontal direction is 7nm, so that the interface of the sub-AlGaN barrier layer and the sub-GaN buffer layer near the GaN side forms a sub-two-dimensional electron gas 2DEG, and ensure that the horizontal position of the secondary two-dimensional electron gas 2DEG is lower than that of the main two-dimensional electron gas 2DEG, as shown in Figure 2(g).

The growth process conditions are as follows: a temperature of 920° C., a pressure of 40 Torr, a hydrogen gas flow of 500 sccm, an ammonia gas flow of 5000 sccm, an aluminum source flow of 10 sccm, and a gallium source flow of 40 sccm.

Step 12, on the epitaxial wafer after secondary growth of the Al _0.35 Ga _0.65 N sub-barrier layer, deposit a SiN dielectric layer with a thickness of 20 nm by using plasma enhanced chemical vapor deposition PECVD method, the dielectric layer covers the sub-barrier layer and The inner wall of the groove, as shown in Figure 2(h).

The process conditions for depositing the dielectric layer are as follows: the flow rate of ammonia gas is 2.5 sccm, the flow rate of nitrogen gas is 900 sccm, the flow rate of silane gas is 200 sccm, the temperature is 300° C., the pressure is 900 mT, and the power is 25 W.

Step 13, remove the SiN dielectric film in the source and drain regions

First, throw the positive glue on the SiN dielectric layer and soft bake;

Next, source and drain regions are formed by exposure and development;

Finally, the SiN dielectric film in the source and drain regions is removed by wet etching.

In step fourteen, the epitaxial wafer from which the SiN dielectric layer in the source and drain regions has been removed is subjected to correcting and soft baking, and the source and drain windows are obtained through exposure and development.

Step fifteen, using a plasma stripping machine to remove the undeveloped photoresist thin layer in the source and drain windows, which can improve the yield of metal stripping.

Step sixteen, depositing Ti/Al/Ni/Au four-layer ohmic contact metal by electron beam evaporation equipment, wherein the thickness of Ti is 30nm, the thickness of Al is 180nm, the thickness of Ni is 40nm, and the thickness of Au is 60nm.

The process conditions for deposition are: the degree of vacuum is less than 2.0×10 ^-6 Pa, the power is 200W, and the evaporation rate is not greater than 3 angstroms/second.

Step seventeen, soak the evaporated epitaxial wafer in acetone solution for 20 minutes, then perform ultrasonic cleaning, rinse with ultrapure water and blow dry with nitrogen. This step peels off the metal outside the source and drain windows.

Step 18: Perform ohmic contact annealing on the epitaxial wafer after metal stripping in a nitrogen atmosphere at a temperature of 850° C. for 30 seconds to form source and drain contact electrodes, as shown in FIG. 2( i ).

In step nineteen, on the epitaxial wafer on which the source and drain contact electrodes have been formed, the resist is cast, soft baked, and a gate window is obtained through exposure and development.

Step 20: Deposit Ni/Au two-layer metal on the epitaxial wafer with the gate window by photolithography, the thickness of Ni is 30nm, and the thickness of Au is 200nm; Peel off, rinse with ultrapure water for 2 minutes, and blow dry with nitrogen to finally obtain the gate electrode, as shown in Figure 2(j).

Step 21: Photolithography has formed the epitaxial wafer with source, drain, and gate structures to obtain thickened electrode patterns, and electron beam evaporation technology is used to thicken the electrodes to complete the fabrication of the device as shown in Figure 1.

Example 2

The transition layer is made of AlN, the thickness of the GaN main buffer layer is 2um, the thickness of the Al _0.27 Ga _0.73 N main barrier layer is 24nm, the groove etching depth is 80nm, and the thickness of the GaN secondary buffer layer is 50nm in the upward direction of the bottom of the groove. The thickness in the horizontal direction of the side of the groove is 25nm, the thickness of the Al _0.27 Ga _0.73 N sub-barrier layer is 24nm in the upward direction of the bottom of the groove, the thickness in the horizontal direction of the side of the groove is 12nm, and the thickness of the gate dielectric layer is 40nm MIS gate GaN-based enhancement mode HEMT device, the steps are:

Step 1 is the same as Step 1 of Embodiment 1.

Step 2 is the same as Step 2 of Example 1.

In step 3, a GaN main buffer layer with a thickness of 2um is epitaxially grown on the transition layer by MOCVD technology, as shown in Fig. 2(b).

The process conditions adopted for the epitaxy are: the temperature is 920° C., the pressure is 40 Torr, the hydrogen gas flow rate is 500 sccm, the ammonia gas flow rate is 5000 sccm, and the gallium source flow rate is 220 sccm.

Step 4: epitaxial N-type doped Al _0.27 Ga _0.73 N main barrier layer with a thickness of 24nm on the main buffer layer by MOCVD technology, and achieved a doping concentration of 6×10 ¹⁹ cm by injecting silane SiH ₄ during the growth process ^-3 N-type doping, so that the AlGaN/GaN heterojunction is formed on the AlN transition layer, and the main two-dimensional electron gas 2DEG is formed on the GaN side of the AlGaN/GaN heterojunction interface, forming an epitaxial wafer The structure is shown in Figure 2(c).

The process conditions used for epitaxy are: temperature 920°C, pressure 40 Torr, hydrogen gas flow 500 sccm, ammonia gas flow 5000 sccm, aluminum source flow 10 sccm, gallium source flow 40 sccm.

Step 5 is the same as Step 5 of Embodiment 1.

Step 6 is the same as Step 6 of Embodiment 1.

Step 7: Photoetch a groove window on the epitaxial wafer after deglue, and use reactive ion etching RIE equipment to etch the AlGaN/GaN heterojunction under the groove window to form a 0001 polar surface on the bottom surface and a non-polar surface on the side surface. The groove structure of the 0001 plane is shown in Fig. 2(e).

The etching uses chlorine Cl ₂ with a flow rate of 15 sccm, a power of 200 W, a pressure of 10 mT, and an etching depth of 80 nm.

Step 8 is the same as Step 8 of Embodiment 1.

Step 9 is the same as Step 9 in Embodiment 1.

Step 10, repeat step 3, and grow GaN sub-buffer layers with different thicknesses on the inner wall of the groove for the second time, that is, the thickness of the GaN sub-buffer layer grown vertically on the bottom of the groove is 50 nm, and the GaN sub-buffer layer grown horizontally on the side of the groove The thickness of the secondary buffer layer is 25nm, as shown in Figure 2(f).

Step 11, using MOCVD technology to re-grow Al _0.27 Ga _0.73 N sub-barrier layers with different thicknesses on the GaN sub-buffer layer, that is, the thickness of the Al _0.27 Ga _0.73 N sub-barrier layer grown vertically on the bottom of the groove is 24nm , the thickness of the Al _0.27 Ga _0.73 N sub-barrier layer grown in the horizontal direction on the side of the groove is 12nm, so that a sub-two-dimensional electron gas is formed at the interface between the sub-AlGaN barrier layer and the sub-GaN buffer layer near the GaN side 2DEG, and ensure that the horizontal position of the secondary two-dimensional electron gas 2DEG is lower than that of the main two-dimensional electron gas 2DEG, as shown in Figure 2(g).

The growth process conditions are as follows: a temperature of 920° C., a pressure of 40 Torr, a hydrogen gas flow of 500 sccm, an ammonia gas flow of 5000 sccm, an aluminum source flow of 10 sccm, and a gallium source flow of 40 sccm.

Step 12, on the epitaxial wafer after secondary growth of the Al _0.27 Ga _0.73 N sub-barrier layer, deposit a SiN dielectric layer with a thickness of 40 nm by using the plasma enhanced chemical vapor deposition PECVD method, and the dielectric layer covers the sub-barrier layer and the concave The inner wall of the groove, as shown in Figure 2(h).

The process conditions for depositing the dielectric layer are as follows: the flow rate of ammonia gas is 2.5 sccm, the flow rate of nitrogen gas is 900 sccm, the flow rate of silane gas is 200 sccm, the temperature is 300° C., the pressure is 900 mT, and the power is 25 W.

Step 13 is the same as Step 13 in Embodiment 1.

Step 14 is the same as Step 14 in Embodiment 1.

Step 15 is the same as Step 15 of Embodiment 1.

Step 16 is the same as Step 16 in Embodiment 1.

Step 17 is the same as Step 17 in Embodiment 1.

Step 18 is the same as Step 18 in Embodiment 1.

Step 19 is the same as Step 19 in Embodiment 1.

Step 20 is the same as Step 20 of Embodiment 1.

Step 21 is the same as Step 21 of Embodiment 1.

Example 3

The transition layer is made of AlN, the thickness of the GaN main buffer layer is 3um, the thickness of the Al _0.2 Ga _0.8 N main barrier layer is 30nm, the groove etching depth is 140nm, and the thickness of the GaN secondary buffer layer is 100nm in the upward direction of the bottom of the groove. The thickness in the horizontal direction of the side of the groove is 50nm, the thickness of the Al _0.2 Ga _0.8 N sub-barrier layer is 30nm in the upward direction of the bottom of the groove, the thickness in the horizontal direction of the side of the groove is 15nm, and the thickness of the gate dielectric layer is 60nm MIS gate GaN-based enhancement mode HEMT device, the steps are:

Step A is the same as step one of embodiment 1.

Step B is the same as Step 2 of Example 1.

In step C, a GaN main buffer layer with a thickness of 3 μm is epitaxially grown on the transition layer by MOCVD technology, as shown in FIG. 2( b ).

The process conditions adopted for the epitaxy are: the temperature is 920° C., the pressure is 40 Torr, the hydrogen gas flow rate is 500 sccm, the ammonia gas flow rate is 5000 sccm, and the gallium source flow rate is 220 sccm.

Step D, use MOCVD technology to epitaxially N-type doped Al _0.2 Ga _0.8 N main barrier layer with a thickness of 30nm on the main buffer layer, and achieve a doping concentration of 6×10 ¹⁹ cm by injecting silane SiH ₄ during the growth process ^-3 N-type doping, so that the AlGaN/GaN heterojunction is formed on the AlN transition layer, and the main two-dimensional electron gas 2DEG is formed on the GaN side of the AlGaN/GaN heterojunction interface, forming an epitaxial wafer The structure is shown in Figure 2(c).

The process conditions used for epitaxy are: temperature 920°C, pressure 40 Torr, hydrogen gas flow 500 sccm, ammonia gas flow 5000 sccm, aluminum source flow 10 sccm, gallium source flow 40 sccm.

Step E is the same as Step 5 of Example 1.

Step F is the same as Step 6 of Embodiment 1.

Step G, photoetch a groove window on the epitaxial wafer after degelling, and use reactive ion etching RIE equipment to etch the AlGaN/GaN heterojunction under the groove window to form a 0001 polar surface on the bottom surface and a non-polar surface on the side surface. The groove structure of the 0001 plane is shown in Fig. 2(e).

The etching adopts chlorine gas Cl ₂ with a flow rate of 15 sccm, a power of 200 W, a pressure of 10 mT, and an etching depth of 140 nm.

Step H is the same as Step 8 of Embodiment 1.

Step 1 is the same as Step 9 of Embodiment 1.

Step J, repeating Step 3, growing GaN sub-buffer layers with different thicknesses on the inner wall of the groove for the second time, that is, the thickness of the GaN sub-buffer layer grown vertically on the bottom of the groove is 100 nm, and the GaN sub-buffer layer grown horizontally on the side of the groove The thickness of the secondary buffer layer is 50nm, as shown in Figure 2(f).

Step K, secondary growth of Al _0.35 Ga _0.65 N sub-barrier layers with different thicknesses on the GaN sub-buffer layer by MOCVD technology, that is, the thickness of the Al _0.2 Ga _0.8 N sub-barrier layer grown vertically on the bottom of the groove is 30nm , the thickness of the Al _0.2 Ga _0.8 N sub-barrier layer grown on the side of the groove in the horizontal direction is 15nm, so that a sub-two-dimensional electron gas is formed at the interface between the sub-AlGaN barrier layer and the sub-GaN buffer layer near the GaN side 2DEG, and ensure that the horizontal position of the secondary two-dimensional electron gas 2DEG is lower than that of the main two-dimensional electron gas 2DEG, as shown in Figure 2(g).

The growth process conditions are as follows: a temperature of 920° C., a pressure of 40 Torr, a hydrogen gas flow of 500 sccm, an ammonia gas flow of 5000 sccm, an aluminum source flow of 10 sccm, and a gallium source flow of 40 sccm.

Step L, on the epitaxial wafer after secondary growth of the Al _0.2 Ga _0.8 N sub-barrier layer, deposit a SiN dielectric layer with a thickness of 60 nm by using the plasma-enhanced chemical vapor deposition PECVD method, and the dielectric layer covers the sub-barrier layer and the concave The inner wall of the groove, as shown in Figure 2(h).

The process conditions for depositing the dielectric layer are as follows: the flow rate of ammonia gas is 2.5 sccm, the flow rate of nitrogen gas is 900 sccm, the flow rate of silane gas is 200 sccm, the temperature is 300° C., the pressure is 900 mT, and the power is 25 W.

Step M is the same as Step 12 of Embodiment 1.

Step N is the same as Step 13 of Embodiment 1.

Step 0 is the same as Step 14 of Embodiment 1.

Step P is the same as Step 15 of Embodiment 1.

Step Q is the same as Step 16 of Embodiment 1.

Step R is the same as Step 17 of Embodiment 1.

Step S is the same as Step 18 of Embodiment 1.

Step T is the same as Step 19 of Embodiment 1.

Step U is the same as Step 20 of Embodiment 1.

Step v is the same as Step 21 of Embodiment 1.

The above-described embodiments are only several preferred examples of the present invention, and do not constitute any limitation to the present invention. Obviously, for those skilled in the art, after understanding the contents and principles of the present invention, they can Under the circumstances of the invention, various amendments and changes in form and details are made according to the method of the present invention, but these amendments and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims (5)

1. A metal insulator semiconductor MIS gate GaN-based enhanced high electron mobility transistor HEMT device, comprising: substrate (1), transition layer (2), GaN main buffer layer (3), N-type AlGaN main barrier layer (4), the source (9) and the drain (10) are on both sides of the top of the N-type AlGaN main barrier layer (4), and the gate electrode (13) is in the middle, and it is characterized in that the middle of the GaN main buffer layer (3) A groove (5) is etched, the bottom surface of the groove is a 0001 polar surface, and the side surface of the groove is a non-0001 surface, and the inner wall of the groove is successively epitaxially provided with a GaN sub-buffer layer (6), an AlGaN sub-barrier layer ( 7) and a dielectric layer (8); the gate electrode (13) is deposited on the dielectric layer (8). 2. The device according to claim 1, characterized in that a main two-dimensional electron gas 2DEG channel (11) is formed at the interface of the GaN main buffer layer (3) and the AlGaN main barrier layer (4), and the channel (11) located on both sides of the groove (5); the interface of the epitaxial GaN sub-buffer layer (6) and the AlGaN sub-barrier layer (7) in the groove forms a sub-two-dimensional electron gas 2DEG channel (12). 3. The device according to claim 1, characterized in that the horizontal position of the secondary two-dimensional electron gas 2DEG channel (12) is lower than the horizontal position of the main two-dimensional electron gas 2DEG channel (11). 4. The device according to claim 1, characterized in that the main barrier layer (4) is N-type doped with a doping concentration of 6×10 ¹⁹ cm ^-3 . 5. A method for making a metal insulator semiconductor MIS gate GaN-based enhancement mode high electron mobility transistor HEMT device, comprising the following steps: (1) Pretreating the substrate surface in the reaction chamber; (2) Epitaxial growth of AlGaN/GaN epitaxial layer on the substrate, in which the thickness of GaN is 1um~3um, the thickness of N-type doped Al _x Ga _1-x N barrier layer is 14nm~30nm, and the molar content of Al element x is 20%-35%; (3) Deposit a mask dielectric layer on the epitaxial layer, then perform photolithography, and etch the dielectric layer on the epitaxial layer by wet etching, and form a 0.5um-long concave on the epitaxial layer groove; (4) Photoetch the groove area, and use the reactive ion etching RIE method to etch the AlGaN/GaN epitaxial layer in the groove area, and the etching depth is 35nm-140nm; (5) Keep the mask dielectric layer outside the groove, pass the etched epitaxial layer through the metal organic chemical vapor deposition MOCVD reaction chamber, and grow a 20nm-100nm thick GaN layer and A 14nm-30nm thick AlGaN layer, a 10nm-50nm thick GaN layer and a 7nm-15nm thick AlGaN layer are grown along the side of the groove; (6) removing the mask dielectric layer; (7) Depositing a gate dielectric layer with a thickness of 20nm to 60nm by chemical vapor deposition CVD or physical vapor deposition PVD on the surface of the material from which the mask dielectric layer has been removed; (8) On the gate dielectric layer, the source and drain regions are first photoetched, and then the source and drain windows are etched; (9) On the surface of the material after photolithography, the metal in ohmic contact is evaporated by electron beam evaporation technology, and the source and drain contact electrodes are formed after stripping and annealing; (10) Lithographically etch the gate area on the gate dielectric, and use electron beam evaporation technology to evaporate the gate metal, and form a metal insulator semiconductor MIS gate after stripping; (11) Photolithography has formed the device surface of the source, drain and gate, obtained thickened electrode patterns, and used electron beam evaporation technology to thicken the electrodes to complete the device production.

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