CN102683406B - GaN-based MS grid enhancement type high electron mobility transistor and manufacture method thereof - Google Patents

Abstract

The invention discloses a GaN-based MS gate enhanced high electron mobility transistor and a manufacturing method, which mainly solve the problems of low current density and low reliability of the GaN-based enhanced device. The structure of the device is as follows: a transition layer (2) and a GaN main buffer layer (3) are sequentially arranged on the substrate (1), a groove (4) is etched in the middle of the GaN main buffer layer, and the GaN main buffer layer on both sides of the groove The upper layer (3) is an AlGaN main barrier layer (5), and the inner wall of the groove and the surface of the AlGaN main barrier layer (5) on both sides of the groove are successively provided with a GaN sub-buffer layer (6) and an AlGaN sub-barrier layer ( 7); on the AlGaN sub-barrier layer (7) are source level (8), drain level (9), gate (11) and dielectric layer (10), source level (8), drain level (9) are respectively located On both sides above the AlGaN sub-barrier layer (7), the gate (11) is located in the middle above the AlGaN sub-barrier layer (7), and the dielectric layer (10) is distributed in regions other than the source level, the drain level and the gate level . The invention has the advantages of good enhanced characteristics, high current density, high breakdown voltage, simple and mature manufacturing process, and high reliability, and can be used in high-temperature switching devices and digital circuits.

Description

GaN-based MS gate enhanced high electron mobility transistor and manufacturing method

technical field

The invention belongs to the technical field of microelectronics, and relates to semiconductor materials, devices and manufacturing techniques thereof. Specifically, it is a GaN-based MS gate enhanced high electron mobility transistor and its manufacturing method, which can be used in high-temperature and high-power applications and basic units of digital circuits.

Background technique

With the development of modern weaponry and aerospace, nuclear energy, communication technology, automotive electronics, and switching power supplies, higher requirements are placed on the performance of semiconductor devices. As a typical representative of wide bandgap semiconductor materials, GaN-based materials have the characteristics of large bandgap width, high electron saturation drift velocity, high critical breakdown field strength, high thermal conductivity, good stability, corrosion resistance, and radiation resistance. Used in the production of high temperature, high frequency and high power electronic devices. In addition, GaN also has excellent electronic properties, and can form a modulation-doped AlGaN/GaN heterostructure with AlGaN. This structure can obtain an electron mobility higher than 1500 cm ² /Vs at room temperature, and a maximum of 3×10 ⁷ cm /s peak electron velocity and 2×10 ⁷ cm/s saturation electron velocity, and obtained a two-dimensional electron gas density higher than that of the second-generation compound semiconductor heterostructure, known as an ideal material for the development of microwave power devices . Therefore, the high electron mobility transistor HEMT based on AlGaN/GaN heterojunction has a very good application prospect in microwave high-power devices.

The growth of AlGaN/GaN heterojunction materials and the development of AlGaN/GaN HEMT devices have always occupied the main position in the research of GaN electronic devices. However, most of the research work on GaN-based electronic devices in the past decade has focused on depletion-mode AlGaN/GaN HEMT devices. Type devices become very difficult, so the study of high-performance AlGaN/GaN enhancement-mode HEMTs is of great significance. First of all, GaN-based materials are known as ideal materials for the development of microwave power devices, and enhanced devices can greatly reduce the complexity and cost of circuits due to the reduction of negative voltage sources in circuits such as microwave power amplifiers and low-noise amplifiers. And AlGaN/GaN enhanced HEMT devices have good circuit compatibility in microwave high-power devices and circuits; at the same time, the development of enhanced devices makes it possible to monolithically integrate digital circuits of depletion-mode/enhancement-mode devices; and, in In terms of power switching applications, AlGaN/GaN enhanced HEMTs also have great application prospects; therefore, research on high-performance AlGaN/GaN enhanced HEMT devices has received great attention.

At present, there are many reports on AlGaN/GaN enhanced HEMTs both domestically and internationally. Currently reported mainly the following technologies:

1. F ion implantation technology, that is, plasma implantation technology based on fluoride CF4. Yong Cai et al. of Hong Kong University of Science and Technology successfully developed an enhanced HEMT device based on F ion implantation technology. F ions are implanted into the AlGaN barrier layer. Due to the strong negative charge of F ions, the F ions in the barrier layer can provide stable negative charges, and thus can effectively deplete the strong two-dimensional electron gas in the channel region. When the AlGaN potential When the number of F ions in the barrier layer reaches a certain amount, the two-dimensional electron gas in the channel under the gate is completely exhausted, thereby realizing an enhanced HEMT device. However, the F-implantation technology will inevitably introduce material damage, and the controllability of the device threshold voltage is not high. The thin layer carrier concentration of the device is as high as 1.3×10 ¹³ cm ^-2 at room temperature, the mobility is 1000cm ² /Vs, the threshold voltage reaches 0.9V, and the maximum drain current reaches 310mA/mm. See literature Yong Cai, Yugang Zhou, Kevin J. Chen and Kei MayLau, "High-performance enhancement-mode AlGaN/GaN HEMTs using fluoride-based plasmatreatment", IEEE Electron Device Lett, Vol.26, No.7, JULY2005.

2. Non-polar or semi-polar GaN materials realize enhancement devices, and Masayuki Kuroda et al. successfully used r-plane side a on sapphire n-AlGaN/GaN HEMT realizes the enhancement of the device. Due to the lack of polarization effect of non-polar or semi-polar materials, its two-dimensional electron gas concentration is small or even non-existent. Therefore, based on non-polar or semi-polar materials AlGaN/GaN HEMT devices have enhanced characteristics. The reported threshold voltage is -0.5V, and the threshold voltage of the device can be further increased by reducing the dopant concentration, but the device characteristics are not good, the electron mobility is only 5.14cm ² /Vs, and the sheet resistance at room temperature is very large. And its gate leakage reaches 1.1×10 ^-5 A/mm when Vgs=-10V. See literature Masayuki Kuroda, Hidetoshi Ishida, Tetsuzo Ueda, and Tsuyoshi Tanaka, "Nonpolar (11-20) plane AlGaN/GaN heterojunction field effect transistors on (1-102) plane sapphire", Journal of Aplied Phisics, Vol.102, No. 9, November 2007.

3. Thin barrier layer technology. In 1996, M.Asif Khan and others first realized the AlGaN/GaN enhanced HEMT device with 10nm AlGaN thin barrier layer technology. The thin barrier layer AlGaN/GaN enhanced HEMT device is due to the potential The thickness of the barrier layer is thinned, its polarization effect is weakened, and the concentration of two-dimensional electron gas in the channel caused by the polarization effect is reduced, so that the threshold voltage of the device is shifted to the right. But the results they obtained are not ideal, the peak transconductance is only 23mS/mm. See literature M.Asif Khan, Q.Chen, C.J.Sun, J.W.Yang, and M.Blasingame, "Enhancement and depletionmode GaN/AlGaN heterostructure field effect transistors" Appl.Phys.Lett, Vol.68, No.4, January1996.

4. Groove gate technology, W.B.Lanford et al. used groove gate technology to make an enhanced device with a threshold voltage of 0.47V through MOCVD. The device structure includes from bottom to top: SiC substrate, nucleation layer, 2um thick GaN, 3nm thick AlGaN, 10nm thick n-AlGaN, 10nm thick AlGaN. This technology makes the barrier layer under the gate thinner by etching the barrier layer under the gate to a certain depth, so that the concentration of 2DEG under the gate is reduced, while the carrier concentration in the source and drain regions remains at a large value, so that both The enhanced characteristics of the device can be realized, and a certain current density can be guaranteed. The epitaxial growth of enhancement-mode devices realized by trench gate technology is easy to control, but its controllability is poor, and the etching process will cause damage. See literature W.B.Lanford, T.Tanaka, Y.Otoki and I.Adesida, "Recessed-gate enhancement-mode GaN HEMT with high threshold voltage", Electronics Letrers, Vol.41, No.7March2005.

To sum up, at present, AlGaN/GaN HEMT enhancement devices in the world are mainly formed based on trench gate technology and fluorine ion implantation technology, which have the following shortcomings:

(1) The increase of the threshold voltage is often at the cost of reducing the current density, and it is difficult to achieve an enhanced device with high threshold voltage and high current density;

(2) No matter the groove gate technology or the fluorine ion implantation technology will cause damage to the material, although a certain amount of damage can be eliminated after annealing, the residual damage will still affect the performance and reliability of the device. At the same time, the repeatability of this process is still low not tall;

(3) The process of manufacturing short-channel devices with short gate lengths is relatively difficult, resulting in low device reliability.

Contents of the invention

The purpose of the present invention is to overcome the defects of the above-mentioned prior art, and propose a GaN-based MS gate-enhanced high electron mobility transistor and a manufacturing method to increase the current density of the device, reduce the difficulty of the process, and improve the reliability of the device. meet the practical application.

In order to achieve the above object, the structure of the high electron mobility transistor provided by the present invention includes from bottom to top: from bottom to top: substrate, transition layer and GaN main buffer layer, characterized in that:

A groove is etched in the middle of the GaN main buffer layer. The bottom surface of the groove is a 0001 polar plane, and the side of the groove is a non-0001 plane. The GaN main buffer layer on both sides of the groove is above the AlGaN main barrier layer. A main two-dimensional electron gas 2DEG layer is formed on the interface between the buffer layer and the main AlGaN barrier layer;

On the bottom and side surfaces of the groove and on the surface of the main AlGaN barrier layer on both sides of the groove, a GaN sub-buffer layer and an AlGaN sub-barrier layer are arranged in sequence; the GaN sub-buffer layer and the AlGaN sub-barrier layer above the bottom of the groove A sub-two-dimensional electron gas 2DEG layer is formed on the interface of the groove; the GaN sub-buffer layer and the AlGaN sub-barrier layer above the side of the groove are AlGaN/GaN heterojunctions with a non-0001 plane, and an enhanced Two-dimensional electron gas 2DEG layer; an auxiliary two-dimensional electron gas 2DEG layer is formed on the interface between the GaN sub-buffer layer and the AlGaN sub-barrier layer on both sides of the groove;

Above the AlGaN sub-barrier layer are a source level, a drain level, a gate and a dielectric layer, the source level and the drain level are respectively located on both sides above the AlGaN sub-barrier layer, and the gate is located on the top of the AlGaN sub-barrier layer. In the middle, the dielectric layer is distributed in areas other than the source level, drain level, and gate level;

The auxiliary two-dimensional electron gas 2DEG layer, the enhanced two-dimensional electron gas layer and the secondary two-dimensional electron gas 2DEG layer form a first conductive channel through the flow of electrons; the main two-dimensional electron gas 2DEG layer, The enhanced two-dimensional electron gas 2DEG layer and the sub-two-dimensional electron gas 2DEG layer form the second conductive channel through the flow of electrons, so that the regions on both sides of the groove are double-channel structures.

The horizontal position of the secondary 2DEG layer is lower than the horizontal position of the main 2DEG layer.

The AlGaN main barrier layer and the AlGaN sub-barrier layer are N-type AlGaN with a doping concentration of 10×10 ¹⁹ cm ⁻³ .

In order to achieve the above object, the GaN-based MS gate-enhanced high electron mobility transistor and its manufacturing method of the present invention comprise the following steps:

1) Pretreating the substrate surface in a reaction chamber;

2) Epitaxial GaN main buffer layer with a thickness of 1.2um-3.2um on the substrate;

3) Epitaxial N-type doped Al _x Ga _1-x N main barrier layer on the GaN epitaxial layer, forming an AlGaN/GaN heterojunction epitaxial layer on the substrate, the Al _x Ga _1-x N main barrier layer The layer thickness is 15nm-38nm, and 0.18≤x≤0.4;

4) Photoetching the AlGaN/GaN heterojunction epitaxial layer, and using reactive ion etching (RIE) method to etch on the AlGaN/GaN epitaxial layer to form grooves with a length of 0.5um and a depth of 40nm-160nm;

5) Secondary epitaxy of the etched epitaxial layer through a metal-organic chemical vapor deposition MOCVD reaction chamber with a GaN sub-buffer layer having a thickness of 24nm-120nm;

6) Using MOCVD technology to epitaxy an Al _x Ga _1-x N sub-barrier layer with a thickness of 15nm-38nm on the secondary epitaxial GaN layer, and 0.18≤x≤0.4;

7) On the secondary epitaxial _{AlxGa1 -xN} sub-barrier layer, a dielectric layer with a thickness of 1nm-20nm is deposited by plasma enhanced chemical vapor deposition PECVD method;

8) On the dielectric layer, the source, drain, and gate regions are photolithographically etched, and the dielectric layer under the window is etched away to obtain the source, drain, and gate windows;

9) Lithograph the source and drain regions, use electron beam evaporation technology to deposit ohmic contact metal, and carry out metal stripping;

10) annealing the ohmic contact metal to form source and drain contact electrodes;

11) The gate area is photolithographically etched, and the gate metal is deposited by electron beam evaporation technology, and the Schottky gate electrode is formed after stripping;

12) The source, drain and gate epitaxial wafers have been formed by photolithography, and the thickened electrode pattern is obtained, and the electrode is thickened by electron beam evaporation technology to complete the device production.

The process conditions of the epitaxial GaN main buffer layer in step 2) are: temperature 1050°C, pressure 20 Torr, hydrogen gas flow 1500 sccm, ammonia gas flow 6000 sccm, gallium source flow 220 sccm.

The process conditions of the secondary epitaxial GaN sub-buffer layer in step 5) are: temperature 1050°C, pressure 20 Torr, hydrogen gas flow 1500 sccm, ammonia gas flow 3000 sccm, gallium source flow 150 sccm.

The process conditions for depositing the dielectric layer by the plasma enhanced chemical vapor deposition PECVD method in the step 7) are as follows: the flow rate of ammonia gas is 2.5 sccm, the flow rate of nitrogen gas is 900 sccm, the flow rate of silane is 200 sccm, the temperature is 300°C, and the pressure is 900mT. The power is 25W.

The present invention has the following advantages:

1. In the present invention, since a groove is etched in the middle of the GaN main buffer layer, and the bottom surface of the groove is a 0001 polar surface, and the side surface of the groove is a non-0001 surface, the non-0001 surface GaN secondary epitaxy along the groove side direction The AlGaN/GaN heterojunction structure formed by the buffer layer and the AlGaN sub-barrier layer reduces or even eliminates the polarization effect, so that the concentration of the two-dimensional electron gas formed at the interface of the heterojunction is very low, or even no two-dimensional electrons Gas, so that the enhanced two-dimensional electron gas 2DEG layer is formed at the heterojunction interface on the side wall of the groove; at the same time, due to the formation of the main two-dimensional electron gas 2DEG layer, an auxiliary two-dimensional electron gas 2DEG layer is formed on the interface between the GaN sub-buffer layer and the AlGaN sub-barrier layer on both sides of the groove, and a secondary two-dimensional electron gas 2DEG layer is formed on the interface between the GaN sub-buffer layer and the AlGaN sub-barrier layer Two-dimensional electron gas 2DEG layer, thus forming the first conductive channel when electrons flow through the auxiliary two-dimensional electron gas 2DEG layer, the enhanced two-dimensional electron gas 2DEG layer and the secondary two-dimensional electron gas 2DEG layer; The two-dimensional electron gas 2DEG layer, the enhanced two-dimensional electron gas 2DEG layer and the secondary two-dimensional electron gas 2DEG layer form the second conductive channel, so that the present invention has a dual channel conduction mechanism.

2. For the first conductive channel in the present invention, only when a certain degree of positive voltage is applied to the gate, the enhanced two-dimensional electron gas 2DEG layer at the interface of the sub-buffer layer and the sub-barrier layer on the side of the groove can form a two-dimensional The electron gas channel realizes the conduction of the first conduction channel, that is, realizes enhanced characteristics of the device.

For the second conductive channel, since the secondary GaN buffer layer grown on the side of the groove is equivalent to a layer of isolation layer, only when a certain positive voltage is applied to the gate, a strong horizontal drift electric field is formed in the GaN isolation layer, where the drift Under the action of an electric field, the channel electrons can be turned on, thereby forming a current.

Due to the existence of high-concentration two-dimensional electron gas 2DEG in the existing AlGaN/GaN HEMT devices, the devices are all in the conduction state when the gate voltage is zero or even lower, so it is difficult to achieve device enhancement; and the present invention The high electron mobility transistor needs a certain positive gate voltage no matter whether the first conduction channel is turned on or the second conduction channel is turned on, so the present invention can realize good enhancement characteristics.

3. In the present invention, since the regions on both sides of the groove of the device are double-channel structures, and the AlGaN barrier layer above the second conductive channel is doped with N-type or even N+ type, it can not only greatly reduce the ohmic contact of the device resistance, and greatly reduces the series resistance of the source and drain of the device; at the same time, due to the introduction of the conduction mechanism of the second conductive channel, the distance of the enhanced two-dimensional electron gas 2DEG layer that can make electrons flow through the sidewall of the groove is greatly reduced Shortened, avoiding the restriction of the enhanced two-dimensional electron gas 2DEG layer conductivity of the sidewall of the groove to the current, which significantly improves the current density of the device, so that the present invention has high current density characteristics; The electric force line can be terminated in the first conductive channel, the N-type AlGaN main barrier layer, the N-type AlGaN sub-barrier layer and the second conductive channel, so that the electric force line between the gate and the channel is dispersed, and the electric field intensity is weakened, thereby improving the The breakdown voltage of the device makes the present invention have a high breakdown voltage.

4. The process steps in the device manufacturing method of the present invention are relatively mature at home and abroad, and the process flow is relatively simple and low in cost, and can be completely compatible with the mature depletion-mode AlGaN/GaN HEMT device manufacturing process. In addition, the present invention uses a reactive ion etching method for etching, and in the subsequent high-temperature secondary growth, the surface damage formed by etching can be repaired to a certain extent, so as to reduce the impact of etching damage on device performance and reliability. sexual influence. Compared with the currently commonly used groove gate etching method at home and abroad, the invention can more effectively avoid material damage caused by etching, and the reliability of the device is higher.

Description of drawings

Fig. 1 is the structural diagram of the MS gate enhanced high electron mobility transistor of GaN base of the present invention;

Fig. 2 is a flow chart of the process for preparing GaN-based MS gate-enhanced high electron mobility transistors according to the present invention.

Detailed ways

Referring to FIG. 1, the GaN-based MS gate-enhanced high electron mobility transistor of the present invention includes: a substrate 1, a transition layer 2, a GaN main buffer layer 3, a groove 4, an AlGaN main barrier layer 5, and a GaN secondary buffer Layer 6, AlGaN sub-barrier layer 7, source level 8, drain level 9, dielectric layer 10, gate 11; above the substrate 1 is the transition layer 2; above the transition layer 2 is the GaN main buffer layer 3, the GaN main buffer The thickness of layer 3 is 1.2um-3.2um; the groove 4 is etched in the middle of the GaN main buffer layer 3, the groove 4 is 0.5um long, the depth is 40nm-160nm, and the bottom surface of the groove 4 is a 0001 polar surface , the side of the groove 4 is a non-0001 surface; the top of the GaN main buffer layer 3 on both sides of the groove 4 is an N-type doped AlGaN main barrier layer 5, and the thickness of the AlGaN main barrier layer 5 is 15nm-38nm, doped The impurity concentration is 10×10 ¹⁹ cm ^-3 , and 0.18≤x≤0.4; the main two-dimensional electron gas 2DEG layer 12 is formed on the interface between the GaN main buffer layer 3 and the AlGaN main barrier layer 5; Above the surface of the AlGaN main barrier layer 5 and on both sides of the groove is a GaN sub-buffer layer 6, the thickness of the GaN sub-buffer layer 6 is 24nm-120nm; above the GaN sub-buffer layer 6 is an N-type doped AlGaN sub-potential barrier layer 7, the thickness of the AlGaN sub-barrier layer 7 is 15nm-38nm, the doping concentration is 10×10 ¹⁹ cm ^-3 , and 0.18≤x≤0.4; the GaN sub-buffer layer 6 above the bottom surface of the groove 4 and the AlGaN A sub-two-dimensional electron gas 2DEG layer 13 is formed on the interface of the sub-barrier layer 7, and the horizontal position of the sub-two-dimensional electron gas 2DEG layer 13 is lower than the horizontal position of the main two-dimensional electron gas 2DEG layer 12; An auxiliary two-dimensional electron gas 2DEG layer 14 is formed on the interface between the GaN sub-buffer layer 6 and the AlGaN sub-barrier layer 7; the GaN sub-buffer layer 6 and the AlGaN sub-barrier layer 7 in the groove side direction are AlGaN with a non-0001 plane /GaN heterojunction, an enhanced two-dimensional electron gas 2DEG layer is formed at the heterojunction interface; on the AlGaN sub-barrier layer 7 are source level 8, drain level 9, gate 11 and dielectric layer 10, the source The level 8 and the drain level 9 are respectively located on both sides above the AlGaN sub-barrier layer 7, the gate 11 is located in the middle above the AlGaN sub-barrier layer 7, and the dielectric layer 10 is distributed in areas other than the source level, the drain level and the gate level , and its thickness is 1nm-20nm; electrons flow through the auxiliary two-dimensional electron gas 2DEG layer 14 on the left side of the groove, the enhanced two-dimensional electron gas layer on the left side wall of the groove, and the secondary two-dimensional electron gas layer on the bottom surface of the groove The 2DEG layer 13, the enhanced two-dimensional electron gas layer on the right side wall of the groove, and the auxiliary two-dimensional electron gas 2DEG layer 14 on the right side of the groove form a first conductive channel 16; electrons flow through the main two-dimensional electron gas layer on the left side of the groove. Dimensional electron gas 2DEG layer 12, enhanced two-dimensional electron gas 2DEG layer on the left side wall of the groove, and secondary two-dimensional electron gas 2DEG layer 1 on the bottom surface of the groove 3 and the enhanced two-dimensional electron gas layer on the right side wall of the groove, and the main two-dimensional electron gas 2DEG layer 12 on the right side of the groove form the second conductive channel 17, so that the regions on both sides of the groove 4 are double channels structure.

Referring to FIG. 2 , the method for fabricating a GaN-based MS gate enhanced high electron mobility transistor of the present invention provides the following three embodiments.

Example 1

The thickness of GaN main buffer layer is 1.2um, the thickness of Al _0.4 Ga _0.6 N main barrier layer is 15nm, the groove etching depth is 40nm, the thickness of GaN sub-buffer layer is 24nm, and the thickness of Al _0.4 Ga _0.6 N sub-barrier layer GaN-based MS gate-enhanced high electron mobility transistor with a thickness of 15nm and a gate dielectric layer thickness of 1nm, the steps are:

Step 1, heat treatment and surface nitriding of the substrate:

Put the sapphire substrate in the metal organic chemical vapor deposition MOCVD reaction chamber, pump the vacuum degree of the reaction chamber to below 1×10 ^-2 Torr, under the mixed gas of hydrogen gas with a flow rate of 1500 sccm and ammonia gas with a flow rate of 2000 sccm Under protection, the sapphire substrate is subjected to heat treatment and surface nitriding, the heating temperature is 1050° C., and the pressure is 20 Torr.

Step 2, epitaxial AlN transition layer:

Using MOCVD technology, under the process conditions of temperature 1050°C, pressure 20Torr, hydrogen flow rate 1500sccm, ammonia flow rate 2000sccm, aluminum source flow rate 30sccm, the epitaxial thickness on the sapphire substrate after heat treatment and surface nitriding is 150nm AlN transition layer, as shown in Figure 2 (a).

Step 3, epitaxial GaN main buffer layer:

Using MOCVD technology, under the process conditions of temperature 1050℃, pressure 20Torr, hydrogen gas flow rate 1500sccm, ammonia gas flow rate 6000sccm, gallium source flow rate 220sccm, epitaxial GaN main buffer layer with a thickness of 1.2um on the AlN transition layer , as shown in Figure 2(b).

Step 4, epitaxial N-type doped Al _0.4 Ga _0.6 N main barrier layer:

Using MOCVD technology, under the process conditions of temperature 920°C, pressure 40Torr, hydrogen flow rate 6000sccm, ammonia flow rate 5000sccm, aluminum source flow rate 10sccm, gallium source flow rate 40sccm, the epitaxial thickness on the main buffer layer is 15nm The N-type doped Al _0.4 Ga _0.6 N main barrier layer, through the growth process through the silane SiH ₄ to achieve the N-type doping concentration of 10 × 10 ¹⁹ cm ^-3 doping, thus forming on the AlN transition layer The AlGaN/GaN heterojunction is formed, and a two-dimensional electron gas 2DEG is formed at the junction interface, and the epitaxial wafer structure is shown in Figure 2(c).

Step five, deposit SiO ₂ layer mask layer:

After cleaning the epitaxial wafer, use electron beam evaporation equipment to deposit a _SiO2 layer with a thickness of 150nm on the epitaxial wafer, as shown in Figure 2(d). The _SiO2 layer can form a protective effect together with the photoresist on the epitaxial wafer surface. The double-layer mask pattern is more conducive to the protection of the surface of the unetched area.

Step 6, photolithography and etching to form the groove structure:

On the surface of the epitaxial wafer deposited with the SiO ₂ layer, the groove window required for etching was formed by throwing the positive resist, soft baking, exposure and development, and the reactive ion etching RIE method was used, and the flow rate of chlorine Cl ₂ was 15 sccm , the power is 200W, and the process condition of pressure is 10mT to etch the epitaxial wafer, and the etching depth is 40nm to form a groove structure, as shown in Fig. 2(e).

Step 7, remove the glue and remove the SiO ₂ mask layer:

Use acetone solution to remove the residual positive resist on the epitaxial wafer after etching, then etch the SiO ₂ mask deposited in step 5 in HF solution, and finally clean it with ultrapure water and dry it with nitrogen gas.

Step 8, heat treatment and surface nitriding of the epitaxial wafer:

The vacuum degree of the reaction chamber was evacuated to below 1×10 ^-2 Torr, and the cleaned epitaxial wafer was heat-treated under the protection of a mixture of hydrogen gas with a flow rate of 1500 sccm and ammonia gas with a flow rate of 2000 sccm at a heating temperature of 1000 °C. The pressure is 20 Torr.

Step 9, secondary epitaxial GaN sub-buffer layer:

Using MOCVD technology, under the process conditions of temperature 1050°C, pressure 20 Torr, hydrogen gas flow rate 1500 sccm, ammonia gas flow rate 3000 sccm, and gallium source flow rate 150 sccm, a GaN sub-buffer layer with a thickness of 24 nm was epitaxially grown on the epitaxial wafer, as shown in the figure 2(f).

Step ten, secondary epitaxial Al _0.4 Ga _0.6 N sub-barrier layer:

Using MOCVD technology, the temperature is 920°C, the pressure is 40Torr, the flow rate of hydrogen gas is 6000sccm, the flow rate of ammonia gas is 5000sccm, the flow rate of aluminum source is 10sccm, the flow rate of gallium source is 40sccm, and silane SiH ₄ is introduced during the growth process Realize N-type doping with a doping concentration of 10×10 ¹⁹ cm ^-3 , and epitaxially form an N-type doped Al _0.4 Ga _0.6 N sub-barrier layer with a thickness of 15 nm on the GaN sub-buffer layer, so that on the bottom of the groove The AlGaN/GaN heterojunction is formed with the Al _0.4 Ga _0.6 N sub-barrier layer and the GaN sub-buffer layer on both sides of the groove. A two-dimensional electron gas 2DEG is formed at the interface of the heterojunction. The epitaxial wafer structure formed after epitaxy Figure 2(g).

Step eleven, depositing a SiN dielectric layer:

Using the plasma-enhanced chemical vapor deposition PECVD method, under the process conditions of ammonia gas flow rate of 2.5 sccm, nitrogen gas flow rate of 900 sccm, silane flow rate of 200 sccm, temperature of 300°C, pressure of 900mT, and power of 25W, the deposition thickness is 1nm SiN dielectric layer, the dielectric layer covers the entire groove, as shown in Figure 2 (h).

Step 12, lithography source and drain windows:

12a) Form the photolithographic windows of the source, drain and gate by throwing the positive resist, soft baking, exposure and development, and remove the SiN dielectric film under the source, drain and gate regions by wet etching.

12a) The epitaxial wafer from which the SiN dielectric film under the source, drain, and gate regions has been removed is subjected to correcting, soft-baking, exposure, and development to obtain windows in the source and drain regions, and a plasma remover is used to remove the undeveloped areas of the window areas Thin layer of photoresist to improve metal lift-off yield.

Step Thirteen, Evaporate Ohmic Contact Metals:

Electron beam evaporation equipment is used to evaporate Ti, Al, Ni, Au four-layer ohmic contact metal under the process conditions of vacuum degree less than 2.0×10 ^-6 Pa, power range of 600W, evaporation rate not greater than 3 angstroms/second, Ti, Al, Ni, Au The thicknesses of Al, Ni, and Au are 30nm, 180nm, 40nm, and 60nm, respectively.

Step 14, metal stripping and ohmic contact annealing:

First, soak the epitaxial wafer with evaporated ohmic contact metal in acetone solution for 20 minutes, then perform ultrasonic cleaning, then rinse with ultrapure water and blow dry with nitrogen to achieve metal stripping, and finally carry out in a nitrogen atmosphere at a temperature of 850°C 30s ohmic contact annealing to form source and drain contact electrodes, as shown in Figure 2(i).

Step fifteen, photolithography out of the gate window:

On the epitaxial wafer after annealing, positive resist, soft baking, exposure and development are carried out to obtain gate windows.

Step sixteen, evaporation grid metal:

Electron beam evaporation equipment is used to deposit Ni and Au two layers of metal. The thickness of Ni and Au are 30nm and 200nm respectively. Then the device is soaked in the stripping solution for metal stripping, then rinsed with ultrapure water for 2min, and finally blown dry with nitrogen. , and finally obtain the gate electrode, as shown in Figure 2(j).

Step seventeen, complete the device production:

The source, drain, and gate epitaxial wafers have been formed by photolithography, and the thickened electrode pattern is obtained, and the electrode is thickened by electron beam evaporation technology, and the device production shown in Figure 1 is completed.

Example 2

The thickness of GaN main buffer layer is 2.5um, the thickness of Al _0.3 Ga _0.7 N main barrier layer is 28nm, the groove etching depth is 100nm, the thickness of GaN sub-buffer layer is 70nm, and the thickness of Al _0.3 Ga _0.7 N sub-barrier layer GaN-based MS gate-enhanced high electron mobility transistor with a thickness of 28nm and a gate dielectric layer thickness of 10nm, the steps are:

Step 1 is the same as Step 1 of Embodiment 1.

Step 2 is the same as Step 2 of Example 1.

Step 3: Epitaxial GaN main buffer layer with a thickness of 2.5um on the AlN transition layer by MOCVD technology, as shown in Figure 2(b), the process conditions used for epitaxy are: temperature 1050°C, pressure 20Torr, hydrogen flow rate 1500sccm, The flow rate of ammonia gas is 6000 sccm, and the flow rate of gallium source is 220 sccm.

Step 4: Use MOCVD technology to epitaxy an N-type doped Al _0.3 Ga _0.7 N main barrier layer with a thickness of 28nm on the main buffer layer, so that an AlGaN/GaN heterojunction is formed on the AlN transition layer, and at the junction interface Two-dimensional electron gas 2DEG is formed, and the epitaxial wafer structure is shown in Figure 2(c). The process conditions for epitaxy are: temperature 920°C, pressure 40 Torr, hydrogen flow rate 6000 sccm, ammonia gas flow rate 5000 sccm, aluminum source flow rate The gallium source flow rate is 10 sccm, and the gallium source flow rate is 40 sccm, and N-type doping with a doping concentration of 10×10 ¹⁹ cm ^-3 is realized by feeding silane SiH ₄ during the growth process.

Step 5 is the same as Step 5 of Embodiment 1.

Step 6, on the surface of the epitaxial wafer deposited with the _SiO2 layer, the groove window required for etching is formed by positive resist, soft baking, exposure and development, and the epitaxial wafer is etched by reactive ion etching RIE method, The etching depth is 100nm, and the groove structure is formed as shown in Fig. 2(e). The etching process conditions are as follows: the flow rate of chlorine Cl ₂ is 15 sccm, the power is 200W, and the pressure is 10mT.

Step 7 is the same as Step 7 of Embodiment 1.

Step 8 is the same as Step 8 of Embodiment 1.

Step 9, using MOCVD technology, epitaxy a GaN sub-buffer layer with a thickness of 70nm on the epitaxial wafer, as shown in Figure 2(f), the process conditions used for the epitaxy are: temperature 1050°C, pressure 20Torr, hydrogen flow rate 1500sccm, ammonia flow rate is 3000sccm, gallium source flow rate is 150sccm.

Step 10, using MOCVD technology, epitaxially form an N-type doped Al _0.3 Ga _0.7 N sub-barrier layer with a thickness of 28 nm on the GaN sub-buffer layer, so that the Al _0.3 Ga _0.7 N on the bottom surface of the groove and on both sides of the groove The sub-barrier layer and the GaN sub-buffer layer form an AlGaN/GaN heterojunction, and a two-dimensional electron gas 2DEG is formed at the interface of the heterojunction. The structure of the epitaxial wafer formed after epitaxy is shown in Figure 2(g). The process used for epitaxy The conditions are: the temperature is 920°C, the pressure is 40 Torr, the flow rate of hydrogen gas is 6000 sccm, the flow rate of ammonia gas is 5000 sccm, the flow rate of aluminum source is 10 sccm, the flow rate of gallium source is 40 sccm, and silane SiH ₄ is introduced during the growth process to achieve a doping concentration of N-type doping of 10×10 ¹⁹ cm ^-3 .

Step 11, use the plasma enhanced chemical vapor deposition PECVD method to deposit a SiN dielectric layer with a thickness of 10nm, the dielectric layer covers the entire groove, as shown in Figure 2(h), the process conditions used for deposition are: the flow rate of ammonia gas is 2.5sccm, nitrogen flow rate is 900sccm, silane flow rate is 200sccm, temperature is 300°C, pressure is 900mT, power is 25W.

Step 12 is the same as Step 12 of Embodiment 1.

Step 13 is the same as Step 13 in Embodiment 1.

Step 14 is the same as Step 14 in Embodiment 1.

Step 15 is the same as Step 15 of Embodiment 1.

Step 16 is the same as Step 16 in Embodiment 1.

Step 17 is the same as Step 17 in Embodiment 1.

Example 3

The thickness of the GaN main buffer layer is 3.2um, the thickness of the Al _0.18 Ga _0.82 N main barrier layer is 38nm, the groove etching depth is 160nm, the thickness of the GaN sub-buffer layer is 120nm, and the thickness of the Al _0.18 Ga _0.82 N sub-barrier layer GaN-based MS gate-enhanced high electron mobility transistor with a thickness of 38nm and a gate dielectric layer thickness of 20nm, the steps are:

Step A is the same as step one of embodiment 1.

Step B is the same as Step 2 of Example 1.

Step C, using the process conditions of temperature 1050°C, pressure 20 Torr, hydrogen gas flow rate 1500 sccm, ammonia gas flow rate 6000 sccm, gallium source flow rate 220 sccm, epitaxial GaN main body with a thickness of 3.2um on the AlN transition layer by MOCVD technology Buffer layer, as shown in Figure 2(b).

Step D, using the process conditions of temperature 920°C, pressure 40Torr, hydrogen flow rate 6000sccm, ammonia flow rate 5000sccm, aluminum source flow rate 10sccm, gallium source flow rate 40sccm, epitaxial thickness on the main buffer layer by MOCVD technology The N-type doped Al _0.18 Ga _0.82 N main barrier layer is 38nm, and the N-type doping concentration of 10×10 ¹⁹ cm ^-3 is achieved by injecting silane SiH ₄ during the growth process, so that the AlN transition layer An AlGaN/GaN heterojunction is formed on the surface, and a two-dimensional electron gas 2DEG is formed at the junction interface, and the epitaxial wafer structure is shown in Figure 2(c).

Step E is the same as Step 5 of Example 1.

Step 6, on the surface of the epitaxial wafer deposited with the _SiO2 layer, the groove window required for etching is formed by throwing the resist, soft baking, exposure and development, and using the reactive ion etching RIE method, in chlorine _Cl2 The flow rate is 15 sccm, the power is 200W, and the pressure is 10mT, and the epitaxial wafer is etched with an etching depth of 160nm to form a groove structure, as shown in Figure 2(e).

Step F is the same as Step 7 of Embodiment 1.

Step G is the same as Step 8 of Embodiment 1.

In step H, under the process conditions of a temperature of 1050° C., a pressure of 20 Torr, a hydrogen flow rate of 1500 sccm, an ammonia gas flow rate of 3000 sccm, and a gallium source flow rate of 150 sccm, a GaN sub-buffer layer with a thickness of 120 nm is epitaxially formed on the epitaxial wafer by MOCVD technology, Figure 2(f).

In step I, the temperature is 920°C, the pressure is 40 Torr, the flow rate of hydrogen gas is 6000 sccm, the flow rate of ammonia gas is 5000 sccm, the flow rate of aluminum source is 10 sccm, and the flow rate of gallium source is 40 sccm, and silane _SiH is introduced into the growth process to achieve N-type doping with a doping concentration of 10×10 ¹⁹ cm ^-3 , using MOCVD technology, epitaxially formed an N-type doped Al _0.18 Ga _0.82 N sub-barrier layer with a thickness of 38 nm on the GaN sub-buffer layer, so that in the concave The Al _0.18 Ga _0.82 N sub-barrier layer and the GaN sub-buffer layer on the bottom surface of the groove and on both sides of the groove form an AlGaN/GaN heterojunction, and a two-dimensional electron gas 2DEG is formed at the heterojunction interface, which is formed after epitaxy The epitaxial wafer structure is shown in Figure 2(g).

In step J, under the process conditions of ammonia gas flow rate of 2.5 sccm, nitrogen gas flow rate of 900 sccm, silane gas flow rate of 200 sccm, temperature of 300°C, pressure of 900 mT, and power of 25 W, the PECVD method is used to deposit A SiN dielectric layer with a thickness of 20nm covers the entire groove, as shown in Figure 2(h).

Step K is the same as Step 12 of Embodiment 1.

Step L is the same as Step 13 of Embodiment 1.

Step M is the same as Step 14 of Embodiment 1.

Step N is the same as Step 15 of Embodiment 1.

Step 0 is the same as Step 16 of Embodiment 1.

Step P is the same as Step 17 of Embodiment 1.

The above-described embodiments are only several preferred examples of the present invention, and do not constitute any limitation to the present invention. Obviously, for those skilled in the art, after understanding the contents and principles of the present invention, they can Under the circumstances of the present invention, various amendments and changes in form and details are made according to the method of the present invention, but these amendments and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims (6)

1. a MS grid enhancement type high electron mobility transistor for GaN base, comprises: substrate (1), transition zone (2) and GaN host buffer layer (3), is characterized in that from bottom to top:

The centre of GaN host buffer layer (3) is etched with groove (4), the bottom surface of this groove (4) is 0001 polar surface, groove (4) side is non-zero 001, GaN host buffer layer (3) top of groove (4) both sides is the main barrier layer of AlGaN (5), on GaN host buffer layer (3) and the main barrier layer of AlGaN (5) interface, forms main two-dimensional electron gas 2DEG layer (12);

The main barrier layer of AlGaN (5) surface of in the bottom surface of groove (4) and side surface direction and groove both sides, is provided with GaN resilient coating (6) and AlGaN barrier layer (7) successively; On GaN the resilient coating (6) of groove floor top and the interface of AlGaN barrier layer (7), form time two-dimensional electron gas 2DEG layer (13); GaN resilient coating (6) in groove side surface direction and AlGaN barrier layer (7) are the AlGaN/GaN heterojunction of non-zero 001, and this heterojunction boundary place forms the two-dimensional electron gas 2DEG layer of enhancement mode; On GaN the resilient coating (6) of groove both sides and the interface of AlGaN barrier layer (7), form auxiliary two-dimensional electron gas 2DEG layer (14);

Described AlGaN barrier layer (7) is upper is source class (8), leakage level (9), grid (11) and dielectric layer (10), this source class (8) and leakage level (9) lay respectively at the both sides of AlGaN barrier layer (7) top, grid (11) is positioned at the centre of AlGaN barrier layer (7) top, and dielectric layer (10) is distributed in source class, leaks the region outside level, grid level;

Described auxiliary two-dimensional electron gas 2DEG layer (14), the Two-dimensional electron gas-bearing formation of enhancement mode and inferior two-dimensional electron gas 2DEG layer (13), by electron stream through forming the first conducting channel (16); Described main two-dimensional electron gas 2DEG layer (12), the two-dimensional electron gas 2DEG layer of enhancement mode and inferior two-dimensional electron gas 2DEG layer (13), by electron stream, through forming the second conducting channel (17), make the region of groove (4) both sides be double channel structure;

It is 10 * 10 that the main barrier layer of described AlGaN (5) and AlGaN barrier layer (7) are doping content ¹⁹cm ^-3n-type AlGaN.

2. enhancement type high electron mobility transistor according to claim 1, is characterized in that, the horizontal level of inferior two-dimensional electron gas 2DEG layer (13) is lower than the horizontal level of main two-dimensional electron gas 2DEG layer (12).

3. a manufacture method for the MS grid enhancement type high electron mobility transistor of GaN base as claimed in claim 1, comprises the following steps:

1) in reative cell, substrate surface is carried out to preliminary treatment;

2) the GaN host buffer layer that epitaxial thickness is 1.2um-3.2um on substrate;

3) Al of extension N-type doping on GaN epitaxial loayer _xga _1-xthe main barrier layer of N forms AlGaN/GaN heterogenous junction epitaxy layer, this Al on substrate _xga _1-xthe main barrier layer thickness of N is 15nm-38nm, and 0.18≤x≤0.4;

4) photoetching AlGaN/GaN heterogenous junction epitaxy layer, and adopt reactive ion etching RIE method, on AlGaN/GaN epitaxial loayer, etching shape is grown into 0.5um, the groove that the degree of depth is 40nm-160nm;

5) GaN the resilient coating that is 24nm-120nm by the epitaxial loayer after etching by metal organic chemical vapor deposition MOCVD reative cell secondary epitaxy thickness;

6) adopt MOCVD technology at the GaN of secondary epitaxy inferior bufferingthe Al that on layer, epitaxial thickness is 15nm-38nm _xga _1-xn barrier layer, and 0.18≤x≤0.4;

7) at the Al of secondary epitaxy _xga _1-xon N barrier layer, adopt the dielectric layer that plasma-reinforced chemical vapor deposition PECVD method deposition thickness is 1nm-20nm;

8), on dielectric layer, make source, leakage, gate region by lithography, and etching is removed the dielectric layer under window, acquisition source, leakage, grid window;

9) make source, drain region by lithography, adopt the metal of electron beam evaporation technique deposit ohmic contact, the row metal of going forward side by side is peeled off;

10) metal ohmic contact is annealed, formation source, drain contact electrode;

11) make gate region by lithography, and adopt electron beam evaporation technique deposit gate metal, after peeling off, form schottky gate electrode;

12) photoetching has formed the epitaxial wafer of source, leakage, grid, obtains thickening electrode pattern, and adopts electron beam evaporation technique to add thick electrode, completes element manufacturing.

4. the manufacture method of the MS grid enhancement type high electron mobility transistor of GaN base according to claim 3, it is characterized in that, step 2) in, the process conditions of extension GaN host buffer layer are: temperature is 1050 ℃, pressure is 20Torr, hydrogen flowing quantity is 1500sccm, ammonia flow is 6000sccm, and gallium source flux is 220sccm.

5. the manufacture method of the MS grid enhancement type high electron mobility transistor of GaN base according to claim 3, it is characterized in that, step 5) in, the process conditions of GaN resilient coating of secondary epitaxy are: temperature is 1050 ℃, pressure is 20Torr, hydrogen flowing quantity is 1500sccm, ammonia flow is 3000sccm, and gallium source flux is 150sccm.

6. the manufacture method of the MS grid enhancement type high electron mobility transistor of GaN base according to claim 3, it is characterized in that, step 7) in, by the process conditions of plasma-reinforced chemical vapor deposition PECVD method dielectric layer deposited, be: ammonia flow is 2.5sccm, nitrogen flow is 900sccm, silane flow rate is 200sccm, temperature is 300 ℃, and pressure is 900mT, and power is 25W.