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CN108321200B - A three-dimensional enhancement mode high electron mobility transistor based on p-GaN structure and its manufacturing method - Google Patents

A three-dimensional enhancement mode high electron mobility transistor based on p-GaN structure and its manufacturing method Download PDF

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CN108321200B
CN108321200B CN201711462615.6A CN201711462615A CN108321200B CN 108321200 B CN108321200 B CN 108321200B CN 201711462615 A CN201711462615 A CN 201711462615A CN 108321200 B CN108321200 B CN 108321200B
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CN108321200A (en
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张凯
朱广润
孔岑
周建军
陈堂胜
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CETC 55 Research Institute
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
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    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

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Abstract

本发明涉及一种基于p‑GaN结构的三维增强型高电子迁移率晶体管及其制造方法，其结构自下而上依次包括衬底、缓冲层、GaN基三维鳍片、栅极、源极和漏极，其特征在于，还包括内置高阻GaN区，它位于所述栅极的下方与GaN基三维鳍片的两侧区域相邻的缓冲层的上方；所述GaN基三维鳍片的上方和两侧二次外延生长有p‑GaN/AlGaN/GaN异质结；所述栅极包裹在p‑GaN/AlGaN/GaN异质结的上方和两侧，形成三维栅结构；通过刻蚀方式去除栅极两侧区域的p‑GaN层而形成AlGaN/GaN异质结，所述源极和漏极分别设在AlGaN/GaN异质结的两端。本发明能够提高p‑GaN增强型器件的阈值电压与击穿电压。

Figure 201711462615

The invention relates to a three-dimensional enhancement type high electron mobility transistor based on a p-GaN structure and a manufacturing method thereof. The structure includes a substrate, a buffer layer, a GaN-based three-dimensional fin, a gate electrode, a source electrode and a The drain is characterized in that it also includes a built-in high-resistance GaN region, which is located below the gate and above the buffer layer adjacent to the two sides of the GaN-based three-dimensional fin; above the GaN-based three-dimensional fin A p-GaN/AlGaN/GaN heterojunction is secondary epitaxially grown on both sides; the gate is wrapped above and on both sides of the p-GaN/AlGaN/GaN heterojunction to form a three-dimensional gate structure; The p-GaN layer on both sides of the gate is removed to form an AlGaN/GaN heterojunction, and the source electrode and the drain electrode are respectively provided at both ends of the AlGaN/GaN heterojunction. The invention can improve the threshold voltage and breakdown voltage of the p-GaN enhancement type device.

Figure 201711462615

Description

Three-dimensional enhanced high electron mobility transistor based on p-GaN structure and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductor device preparation, and particularly relates to a three-dimensional enhanced high electron mobility transistor based on a p-GaN structure and a manufacturing method thereof.
Technical Field
Because of the advantages of high breakdown field strength, high saturation velocity, high temperature resistance and the like of the third-generation semiconductor GaN material, the high electron mobility transistor prepared based on the GaN material has the characteristics of high power, high efficiency, high velocity, high breakdown voltage and the like, and is considered to be a preferred material for manufacturing the new-generation microwave and high-power electronics.
The conventional GaN hemt intrinsically exhibits depletion mode or normally-on operation due to polarization effects that induce high concentration of 2DEG at the barrier layer-channel layer heterojunction interface. In practical applications such as power switches, electric vehicles, wireless charging, etc., the normally-off mode or enhancement mode GaN transistor is the optimal choice for failure protection, circuit structure simplification of gate drive, and cost reduction. However, it is still the biggest challenge to be able to obtain a high threshold voltage, high performance enhancement mode device simply and efficiently at low cost. Various techniques have been reported to achieve the normally-off operation of devices, such as fluorine ion implantation, p-GaN structures, ultra-thin barrier layer structures, dry, wet and electrochemical oxidation barrier layers, non-polar heterojunction designs, MIS trench gate etching, three-dimensional gate structures, etc.
In 2008, the MIS notched Gate structure proposed by Tohru Oka et al in japan (see document Tohru Oka al, "AlGaN/GaN reprocessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications", IEEE Electron Device let, vol.29, No.7, pp.668-670,2008) is one of the more widely studied and potential structures at present, but has many problems such as etching damage, difficulty in controlling Threshold uniformity, interface stability, and the like.
The most promising structure currently in the industry is the p-GaN Gate structure proposed by Toyota 2007 (see Tohru Oka al., "Gate Injection Transistor (GIT) — A normaly-Off AlGaN/GaN Power Transistor Using reduction Modulation", IEEE Electron Device Lett., vol.54, No.12, pp.3933-3935,2007). The structure realizes an enhancement device with higher threshold by forming a p-type AlGaN or GaN layer under the gate to exhaust channel electrons. The structure has no problems of stability of an MIS groove gate structure and the like, so the structure has attracted much attention in recent years and develops rapidly. However, the thicker undoped AlGaN barrier layer is remained under the gate of the structure and is limited by the p-type doping technology, so that the threshold voltage of the device is lower. In order to increase the threshold voltage, Hideyuki Okita et al proposed a structure of trench Gate combined with p-GaN in 2017 (see the documents Hideyuki Okita al, "Through reproduction and reproduction Gate Technology for reading processing Stability of GaN-Based Gate Injection Transistors", IEEE Trans.
In recent years, attention has been focused on three-dimensional gate GaN devices due to their better gate control capability, and one of their advantages is that the device Threshold Voltage and breakdown Voltage are increased by virtue of the side gate capability (see the document Kota Ohi et al, "Drain Current Stability and control of Threshold Voltage and sub-Threshold Current in a Multi-Mesa-Channel AlGaN/GaN High Electron Mobility Transistor", japan Journal of Applied Physics, vol.48, No.8, pp.081002, 2009). However, the conventional three-dimensional enhancement Devices are all Based on schottky structures or MOS/MIS structures (see "High-Performance GaN-Based Nanochannel transistors With/Without AlGaN/GaN Heterostructure", IEEE trans. electron Devices, vol.60, No.10, pp.3012-3018,2013), and thus have problems of low operating voltage and the above-mentioned stability.
The Chinese patent application discloses a GaN-based fin-gate enhanced device and a manufacturing method thereof, and mainly solves the problem that the threshold voltage of the conventional similar device is small in positive drift. However, the gate structure of the device adopts a schottky gate contact, so that the forward working voltage of the device is very low, and the high-power requirement is difficult to meet.
The Chinese patent application discloses a groove gate enhanced GaN transistor device based on a nano channel, and the transistor has the advantages of strong gate control capability, short channel effect inhibition, enhancement of the device and small on resistance. However, the gate structure of the device adopts a structure of combining a groove with an MOS/MIS, so that the device has the problems of etching uniformity, interface stability and the like, and industrial application is difficult to realize.
Although the above two schemes can realize a GaN enhancement mode device and improve the threshold voltage, there are significant disadvantages: mainly adopts a Schottky or MOS/MIS gate structure, so that the defects of low working voltage, controllability, stability and the like exist.
How to overcome the defects of the prior art becomes one of the key problems to be solved urgently in the technical field of the preparation of the semiconductor device at present.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a three-dimensional enhanced high electron mobility transistor based on a p-GaN structure and a manufacturing method thereof.
2. According to the three-dimensional enhanced high electron mobility transistor based on the p-GaN structure, the structure of the three-dimensional enhanced high electron mobility transistor sequentially comprises a substrate, a buffer layer, a GaN-based three-dimensional fin, a grid electrode, a source electrode and a drain electrode from bottom to top, and is characterized by further comprising a built-in terminal structure, wherein the built-in terminal structure is a built-in high-resistance GaN region formed through ion implantation, and the built-in GaN high-resistance region is positioned below the grid electrode and above the buffer layer adjacent to two side regions of the GaN-based three-dimensional fin; p-GaN/AlGaN/GaN heterojunction structures are grown above and on two sides of the GaN-based three-dimensional fin in a secondary epitaxial mode; the grid electrode is wrapped above and at two sides of the p-GaN/AlGaN/GaN heterojunction to form a three-dimensional grid structure; and removing the p-GaN layers in the areas on the two sides of the grid electrode in an etching mode to form an AlGaN/GaN heterojunction, wherein the source electrode and the drain electrode are respectively arranged at the two ends of the AlGaN/GaN heterojunction.
The invention provides a further preferable scheme of a three-dimensional enhancement type high electron mobility transistor based on a p-GaN structure, which comprises the following steps:
the height of the GaN-based three-dimensional fins is 200-1000 nm, the width of the GaN-based three-dimensional fins is 200-2000 nm, the number n of the GaN-based three-dimensional fins is more than or equal to 1, and the distance between adjacent GaN-based three-dimensional fins is 200-2000 nm. The p-GaN of the p-GaN/AlGaN/GaN heterojunction has a thickness of 40-150 nm and a p-type doping concentration of 1017～5×1020cm-3The p-type doping material is any one of Mg, Fe, Zn, C and Ca; the AlGaN is 5-30 nm thick, the Al component is 10-40%, and the GaN is 20-200 nm thick.
The invention provides a three-dimensional GaN enhancement type high electron mobility transistor and a first manufacturing method of a preferred scheme, which are characterized by comprising the following specific steps of:
1) growing a buffer layer over the substrate;
2) depositing a metal or insulating medium as a hard mask over the buffer layer;
3) defining a photoetching mask of the GaN-based three-dimensional fin above the hard mask, and then etching and removing the hard mask in an RIE (reactive ion etching) and ICP (inductively coupled plasma) mode;
4) etching GaN in an RIE (reactive ion etching) and ICP (inductively coupled plasma) mode to form a three-dimensional GaN fin; the height of the GaN-based three-dimensional fins is 200-1000 nm, the width of the GaN-based three-dimensional fins is 200-2000 nm, and the distance between adjacent GaN-based three-dimensional fins is 200-2000 nm;
5) removing etching damage by adopting a TMAH (mechanical vapor etching) or plasma treatment mode and the like, and then injecting ions into the buffer layer to form a built-in terminal structure; the ion implantation element is any one of Ar, H, B, O, N, He, Zn and F, and the ion implantation energy is 30-300 KeV;
6) removing the hard mask by adopting a wet method or a dry method;
7) growing p-GaN/AlGaN/GaN heterojunction on the surface and the side surface of the buffer layer and the GaN-based three-dimensional fin by adopting MOCVD, MBE, PLD and other modes; the p-GaN of the p-GaN/AlGaN/GaN heterojunction has a thickness of 40-150 nm and a p-type doping concentration of 1017～5×1020cm-3The p-type doping material is any one of Mg, Fe, Zn, C and Ca; the thickness of AlGaN is 5-30 nm, and the Al component is 10-40%; the thickness of the GaN is 20-200 nm;
8) depositing gate metal on the surface of the p-GaN/AlGaN/GaN heterojunction above the GaN-based three-dimensional fin in an evaporation or sputtering mode, and then depositing a blocking dielectric layer in an ALD (atomic layer deposition), PECVD (plasma enhanced chemical vapor deposition), ICP-CVD (inductively coupled plasma-chemical vapor deposition), LPCVD (low pressure chemical vapor deposition) and other modes;
9) photoetching a grid mask, and sequentially etching the blocking dielectric layer and the grid metal by adopting RIE and ICP modes to form a grid;
10) etching and removing the p-type GaN outside the grid region by RIE and ICP modes by taking the blocking medium layer as a mask to form an AlGaN/GaN heterojunction;
11) removing the barrier dielectric layer by wet etching;
12) photoetching a source-drain mask on two sides of the grid, depositing source-drain metal, and annealing at high temperature to form a source electrode and a drain electrode;
13) defining a photoetching isolation mask, and isolating by adopting an etching or ion implantation mode to form an active region;
14) depositing a passivation dielectric layer on the surfaces of the grid electrode, the source electrode, the drain electrode and the AlGaN/GaN heterojunction by adopting ALD (atomic layer deposition), PECVD (plasma enhanced chemical vapor deposition) and ICP-CVD (inductively coupled plasma-chemical vapor deposition) modes;
15) defining an interconnection open hole area mask, and etching to form interconnection open holes;
16) and defining an interconnection metal area mask, and forming interconnection metal through evaporation and stripping processes.
The invention provides a second manufacturing method based on a three-dimensional GaN enhancement type high electron mobility transistor and a preferred scheme, which is characterized by comprising the following specific steps of:
1) growing a buffer layer over the substrate;
2) depositing a metal or insulating medium as a hard mask over the buffer layer;
3) defining a photoetching mask of the GaN-based three-dimensional fin above the hard mask, and then etching and removing the hard mask in an RIE (reactive ion etching) and ICP (inductively coupled plasma) mode;
4) etching GaN by means of RIE and ICP to form a GaN-based three-dimensional fin; the height of the GaN-based three-dimensional fin is 200-1000 nm, and the width of the GaN-based three-dimensional fin is 200-2000 nm; the distance between adjacent GaN-based three-dimensional fins is 200-2000 nm;
5) removing etching damage by adopting a TMAH (mechanical vapor etching) or plasma treatment mode, and then injecting ions into the buffer layer to form a built-in terminal structure; the ion implantation element is any one of Ar, H, B, O, N, He, Zn and F, and the ion implantation energy is 30-300 KeV;
6) removing the hard mask by adopting a wet method or a dry method;
7) growing p-GaN/AlGaN/GaN heterojunction on the buffer layer and the surface and the side surface of the GaN-based three-dimensional fin by adopting MOCVD, MBE and PLD modes; the p-GaN of the p-GaN/AlGaN/GaN heterojunction has a thickness of 40-150 nm and a p-type doping concentration of 1017～5×1020cm-3The p-type doping material is any one of Mg, Fe, Zn, C and Ca; the thickness of AlGaN is 5-30 nm, and the Al component is 10-40%; the thickness of the GaN is 20-200 nm;
8) photoetching source and drain masks at two ends of the p-GaN/AlGaN/GaN heterojunction, then etching and removing p-type GaN in an RIE (reactive ion etching) and ICP (inductively coupled plasma) mode, depositing source and drain metals, and annealing at high temperature to form a source electrode and a drain electrode;
9) photoetching a grid mask on the surface of a p-GaN/AlGaN/GaN heterojunction above the GaN-based three-dimensional fin, depositing grid metal in an evaporation or sputtering mode, and forming a grid through a stripping process;
10) etching and removing the p-type GaN outside the source electrode area, the drain electrode area and the grid electrode area by RIE and ICP modes by taking the source electrode area, the drain electrode area and the grid electrode area as masks to form an AlGaN/GaN heterojunction;
11) defining a photoetching isolation mask, and carrying out device isolation by adopting an etching or ion implantation mode to form an active region;
12) depositing a passivation dielectric layer on the surfaces of the grid electrode, the source electrode, the drain electrode and the AlGaN/GaN heterojunction by adopting ALD (atomic layer deposition), PECVD (plasma enhanced chemical vapor deposition) and ICP-CVD (inductively coupled plasma-chemical vapor deposition) modes;
13) defining an interconnection open hole area mask, and etching to form interconnection open holes;
14) and defining an interconnection metal area mask, and forming interconnection metal through evaporation and stripping processes.
The realization principle of the invention is as follows: according to the invention, a GaN-based three-dimensional fin is formed by an etching method, and a built-in terminal structure initiated in the field is adopted, wherein the built-in terminal structure is a built-in high-resistance region formed by ion implantation, and the built-in GaN high-resistance region is positioned below a grid electrode and above a buffer layer adjacent to two side regions of the GaN-based three-dimensional fin, so that an electric field at the corner of the fin is relieved; and then, a p-GaN/AlGaN/GaN layer is grown in a secondary epitaxial mode, and after the p-GaN outside the grid electrode is etched and removed, a p-GaN/AlGaN/GaN heterogeneous body with a three-dimensional grid structure is formed below the grid electrode, so that the advantages of the three-dimensional grid structure can be utilized, the defects of the existing plane enhancement device based on the p-GaN structure are overcome, and the threshold voltage and the breakdown voltage of the device are improved.
Compared with the prior art, the invention has the remarkable advantages that:
firstly, the three-dimensional gate structure is introduced into a p-GaN enhancement type device, and the threshold voltage of the conventional p-GaN enhancement type device is further improved by utilizing the enhanced gate control capability of the three-dimensional gate structure;
secondly, the device introduces a three-dimensional gate structure into the p-GaN enhancement device, utilizes the three-dimensional gate structure to have better electric field regulation and control capability and introduces a built-in electric field terminal structure, and forms high-resistance regions on two sides of the fin below the gate through ion implantation, so that the electric field peak value at the corner of the fin is relieved, and the breakdown voltage of the conventional p-GaN enhancement device is further improved.
Thirdly, the device of the invention adopts the p-GaN technology, so compared with other MOS/MIS three-dimensional enhancement devices, the controllability and the stability are higher, and the industrial application potential is larger; the invention is suitable for the field of GaN high-voltage power electronics.
Drawings
FIG. 1a is a schematic plan view of a three-dimensional enhanced HEMT based on a p-GaN structure according to the present invention; FIG. 1b is a cross-sectional view taken in the vertical direction a of FIG. 1 a; fig. 1c is a cross-sectional view in the horizontal direction b of fig. 1 a.
Fig. 2a, fig. 2b, fig. 2c, fig. 2d, fig. 2e, fig. 2f, fig. 2g, fig. 2h, and fig. 2i are schematic diagrams sequentially illustrating a flow of a first method for manufacturing a three-dimensional enhancement mode high electron mobility transistor based on a p-GaN structure according to the present invention.
Fig. 3a, fig. 3b, fig. 3c, fig. 3d, fig. 3e, fig. 3f, fig. 3g, and fig. 3h are schematic diagrams sequentially illustrating a second method for fabricating a three-dimensional enhancement mode hemt based on a p-GaN structure according to the present invention.
Detailed Description
The following describes in detail a specific embodiment of the present invention with reference to the drawings and examples.
Referring to fig. 1a, 1b and 1c, the three-dimensional enhancement mode high electron mobility transistor based on the p-GaN structure is based on a group III nitride semiconductor, and comprises a substrate 1, a buffer layer 2, a GaN-based three-dimensional fin 3, a gate 6, a source and a drain from bottom to top, and further comprises a built-in terminal structure 4, wherein the built-in terminal structure 4 is a built-in high-resistance GaN region formed by ion implantation, and the built-in GaN high-resistance region is positioned below the gate 6 and above the buffer layer 2 adjacent to two side regions of the GaN-based three-dimensional fin 3; p-GaN/AlGaN/GaN heterojunction junctions 5 grow above and on two sides of the GaN-based three-dimensional fin 3; the grid electrode 6 is wrapped above and at two sides of the p-GaN/AlGaN/GaN heterojunction to form a three-dimensional grid structure; and removing the p-GaN layers in the areas on the two sides of the grid 6 by etching to form an AlGaN/GaN heterojunction, wherein the source electrode and the drain electrode are respectively arranged at the two ends of the AlGaN/GaN heterojunction. Wherein:
the GaN-based three-dimensional fin 3 has a height of 200-1000 nm (including 200nm, 400nm, 600nm or 1000nm and the like) and a width of 200-2000 nm (including 200nm, 600nm, 1000nm or 2000nm and the like); the number n of the GaN-based three-dimensional fins 3 is more than or equal to 1, and the distance between adjacent GaN-based three-dimensional fins 3 is 200-2000 nm (including 200nm, 800nm, 1500nm or 2000 nm).
The p-GaN of the p-GaN/AlGaN/GaN heterojunction 5 has a thickness of 40-150 nm (including 40nm, 70nm, 100nm or 150 nm), and a doping concentration of 1017～5×1020cm-3The AlGaN is 5-30 nm thick, the Al component is 10-40%, and the GaN is 20-200 nm thick (including 20nm, 50nm, 100nm or 200 nm).
Referring to fig. 2a, fig. 2b, fig. 2c, fig. 2d, fig. 2e, fig. 2f, fig. 2g, fig. 2h and fig. 2i, the first method for manufacturing a three-dimensional enhancement mode hemt based on a p-GaN structure according to the present invention comprises the following steps:
1) growing a buffer layer 2 over said substrate 1, as in fig. 2 a; wherein the substrate 1 is made of any one of Si, diamond, SiC, sapphire and GaN self-supporting substrate;
2) depositing a metal or an insulating medium as a hard mask above the buffer layer 2; the hard mask is Ni, W, SiN and SiO2Any one or more combinations of;
3) defining a photoetching mask of the GaN-based three-dimensional fin above the hard mask, and then etching and removing the hard mask by means of RIE and ICP, as shown in FIG. 2 b;
4) etching GaN by means of RIE and ICP to form GaN-based three-dimensional fins 3, as shown in FIG. 2 c; the GaN-based three-dimensional fin 3 is 200-1000 nm in height and 200-2000 nm in width; the distance between adjacent GaN-based three-dimensional fins 3 is 200-2000 nm;
5) removing etching damage by adopting TMAH (mechanical vapor etching) or plasma treatment and the like, and then injecting ions into the buffer layer 2 to form a built-in terminal structure 4, as shown in FIG. 2 d; the ion implantation element is any one of Ar, H, B, O, N, He, Zn and F, and the ion implantation energy is 30-300 KeV;
6) removing the hard mask by adopting a wet method or a dry method;
7) growing a p-GaN/AlGaN/GaN heterojunction 5 on the surface and the side surface of the buffer layer 2 and the GaN-based three-dimensional fin 3 by adopting MOCVD, MBE, PLD and other modes, as shown in figure 2 e; the p-GaN of the p-GaN/AlGaN/GaN heterojunction 5 has a thickness of 40-150 nm and a p-type doping concentration of 1017～5×1020cm-3The p-type doping material is any one of Mg, Fe, Zn, C and Ca; the thickness of AlGaN is 5-30 nm, and the Al component is 10-40%; the thickness of the GaN is 20-200 nm;
8) depositing gate metal on the surface of the p-GaN/AlGaN/GaN heterojunction 5 above the GaN-based three-dimensional fin 3 by adopting an evaporation or sputtering mode, and then depositing a blocking dielectric layer by adopting an ALD (atomic layer deposition), PECVD (plasma enhanced chemical vapor deposition), ICP-CVD (inductively coupled plasma-chemical vapor deposition) and LPCVD (low pressure chemical vapor deposition) modes, as shown in a figure 2 f; the gate metal comprises any one of multilayer metals or single-layer metals of Pd/Au, W/Al, Ni/Au, Mo/Au, WN/Al, Pt, TiN and W, and the thickness of the gate metal is 50-500 nm;
9) photoetching a grid mask, and sequentially etching the blocking dielectric layer and the grid metal by adopting RIE and ICP modes to form a grid 6 as shown in figure 2 g;
10) etching and removing the p-type GaN outside the gate 6 region by RIE and ICP modes by taking the blocking dielectric layer as a mask to form an AlGaN/GaN heterojunction, as shown in FIG. 2 h;
11) removing the barrier dielectric layer by wet etching;
12) photoetching a source-drain mask on two sides of the grid electrode 6, then depositing source-drain metal, and annealing at high temperature to form a source electrode and a drain electrode, as shown in figure 2 i;
13) defining a photoetching isolation mask, and isolating by adopting an etching or ion implantation mode to form an active region;
14) depositing a passivation dielectric layer on the surfaces of the grid electrode 6, the source electrode, the drain electrode and the AlGaN/GaN heterojunction by adopting modes of ALD, PECVD, ICP-CVD and the like;
15) defining an interconnection open hole area mask, and etching to form interconnection open holes;
16) and defining an interconnection metal area mask, and forming interconnection metal through evaporation and stripping processes.
Referring to fig. 3a, fig. 3b, fig. 3c, fig. 3d, fig. 3e, fig. 3f, fig. 3g and fig. 3h, the second method for manufacturing a three-dimensional enhancement mode high electron mobility transistor based on a p-GaN structure according to the present invention comprises the following steps:
1) growing a buffer layer 2 over the substrate 1, as in fig. 3 a; wherein the substrate 1 is made of any one of Si, diamond, SiC, sapphire and GaN self-supporting substrate;
2) depositing a metal or an insulating medium as a hard mask above the buffer layer 2; the hard mask is Ni, W, SiN and SiO2Any one or more combinations of;
3) defining a photoetching mask of the GaN-based three-dimensional fin 3 above the hard mask, and then etching and removing the hard mask by means of RIE and ICP, as shown in FIG. 3 b;
4) etching GaN by means of RIE and ICP to form GaN-based three-dimensional fins 3, as shown in FIG. 3 c; the GaN-based three-dimensional fin (3) is 200-1000 nm in height and 200-2000 nm in width; the distance between adjacent GaN-based three-dimensional fins (3) is 200-2000 nm;
5) removing etching damage by adopting TMAH (mechanical vapor etching) or plasma treatment and the like, and then injecting ions into the buffer layer 2 to form a built-in terminal structure 4, as shown in FIG. 3 d; the ion implantation element is any one of Ar, H, B, O, N, He, Zn and F, and the ion implantation energy is 30-300 KeV;
6) removing the hard mask by adopting a wet method or a dry method;
7) growing a p-GaN/AlGaN/GaN heterojunction 5 on the surface and the side surface of the buffer layer 2 and the GaN-based three-dimensional fin 3 by adopting MOCVD, MBE, PLD and other modes, as shown in figure 3 e; the p-GaN of the p-GaN/AlGaN/GaN heterojunction 5 has a thickness of 40-150 nm and a p-type doping concentration of 1017～5×1020cm-3The p-type doping material is any one of Mg, Fe, Zn, C and Ca; the thickness of AlGaN is 5-30 nm, and the Al component is 10-40%; the thickness of the GaN is 20-200 nm;
8) photoetching source and drain masks at two ends of the p-GaN/AlGaN/GaN heterojunction 5, then etching and removing the p-type GaN in an RIE (reactive ion etching) and ICP (inductively coupled plasma) mode, depositing source and drain metals, and annealing at high temperature to form a source electrode and a drain electrode, as shown in figure 3 f;
9) photoetching a grid mask on the surface of the p-GaN/AlGaN/GaN heterojunction 5 above the GaN-based three-dimensional fin 3, depositing grid metal in an evaporation or sputtering mode, and forming a grid through a stripping process, as shown in FIG. 3 g; the gate metal comprises any one of multilayer metals or single-layer metals of Pd/Au, W/Al, Ni/Au, Mo/Au, WN/Al, Pt, TiN and W, and the thickness of the gate metal is 50-500 nm;
10) etching and removing the p-type GaN outside the source electrode area, the drain electrode area and the grid electrode area by RIE and ICP modes by taking the source electrode area, the drain electrode area and the grid electrode area as masks to form an AlGaN/GaN heterojunction, as shown in figure 3 h;
11) defining a photoetching isolation mask, and carrying out device isolation by adopting an etching or ion implantation mode to form an active region;
12) depositing a passivation dielectric layer on the surfaces of the grid electrode, the source electrode, the drain electrode and the AlGaN/GaN heterojunction by adopting ALD (atomic layer deposition), PECVD (plasma enhanced chemical vapor deposition) and ICP-CVD (inductively coupled plasma-chemical vapor deposition) modes;
13) defining an interconnection open hole area mask, and etching to form interconnection open holes;
14) and defining an interconnection metal area mask, and forming interconnection metal through evaporation and stripping processes.
According to the above three-dimensional enhancement mode high electron mobility transistor based on p-GaN structure and two manufacturing methods thereof, the present invention further discloses the following embodiments, but not limited to the embodiments.
Example 1: the preparation method comprises the following steps of preparing a substrate 1 from Si, forming a GaN-based three-dimensional fin 3 with the width of 200nm and the height of 1000nm, forming a three-dimensional GaN enhancement type high electron mobility transistor with a built-in terminal structure by Ar ion implantation, wherein the GaN-based three-dimensional fin 3 is 2000nm in adjacent distance, and the gate metal is W, and the preparation method specifically comprises the following steps:
1) on the upper side of a Si substrate 1, by utilizing a Metal Organic Chemical Vapor Deposition (MOCVD) technology, AlN of 200nm is firstly grown at 1050 ℃, and then an AlGaN layer (15 percent of Al group) of 1 mu m which is not intentionally doped and a GaN layer of 1 mu m are grown at 1000 ℃ to form a buffer layer 2;
2) depositing 100nm W metal above the buffer layer 2 by magnetron sputtering in sequence, and depositing 80nm SiN by PECVD as a hard mask; the W sputtering conditions were: vacuum degree ≦ 1.5X 10-6Torr, deposition rate less than
Figure BDA0001530467390000101
The SiN deposition process conditions are as follows: gases are SiH respectively4、NH3He and N2The flow rate is respectively 8sccm, 2sccm, 100sccm and 200sccm, the pressure is 500mTorr, the temperature is 260 ℃, and the power is 25W;
3) defining a photoetching mask of the GaN-based three-dimensional fin 3 above the W/SiN hard mask, and then etching and removing the hard mask in an ICP (inductively coupled plasma) mode; the etching process conditions are as follows: the gas being SF6The flow rate is 20sccm, and the pressure is 0.2 pa;
4) etching GaN by an ICP (inductively coupled plasma) mode to form a GaN-based three-dimensional fin 3; the width of the GaN-based three-dimensional fins 3 is 200nm, and the interval between adjacent GaN-based three-dimensional fins 3 is 2000 nm; the etching process conditions are as follows: the gases are respectively BCl3And Cl2The flow rate is respectively 25sccm and 5sccm, the pressure is 30mTorr, the power of an upper electrode is 100W, the power of a lower electrode is 10W, and the etching depth is 1000 nm;
5) removing etching damage by adopting TMAH, and then injecting Ar ions into the buffer layer 2 to form a built-in terminal structure 4; the energy of Ar ion implantation is 30 KeV;
6) using HF acid and H successively2O2Removing the SiN and W metals;
7) growing a p-GaN/AlGaN/GaN heterojunction 5 on the surface and the side surface of the buffer layer 2 and the GaN-based three-dimensional fin 3 by MOCVD; the thickness of the p-GaN is 150nm, and the doping concentration is 2 multiplied by 1017cm-3The p-type doped material is Mg; the thickness of AlGaN is 5nm, the composition of Al is 40%, and the thickness of GaN is 200 nm;
8) p-GaN/AlGaN/GaN heterojunction 5 above GaN-based three-dimensional fin 3Depositing 50nm W gate metal on the surface by adopting a sputtering mode, and then depositing a 50nm blocking dielectric layer SiN by adopting a PECVD mode; the W sputtering conditions were: vacuum degree ≦ 1.5X 10-6Torr, deposition rate less than
Figure BDA0001530467390000111
The SiN deposition process conditions are as follows: gases are SiH respectively4、NH3He and N2The flow rate is respectively 8sccm, 2sccm, 100sccm and 200sccm, the pressure is 500mTorr, the temperature is 260 ℃, and the power is 25W;
9) photoetching a grid mask, and sequentially etching the SiN blocking dielectric layer and the W grid metal by adopting ICP (inductively coupled plasma) to form a grid 6; the SiN etching process conditions are as follows: the gas being SF6The flow rate is 20sccm, and the pressure is 0.2 pa;
10) removing the p-type GaN outside the grid electrode 6 region by ICP etching by taking the SiN blocking dielectric layer as a mask to form an AlGaN/GaN heterojunction; the etching process conditions are as follows: the gases are respectively BCl3And Cl2The flow is respectively 25sccm and 5sccm, the pressure is 30mTorr, the temperature is 25 ℃, the power of the upper electrode is 100W, and the power of the lower electrode is 10W;
11) removing the SiN layer by adopting BOE;
12) photoetching source and drain electrode masks on two sides of the grid electrode 6, evaporating source and drain electrode metal by using an electron beam, and annealing at high temperature to form a source electrode and a drain electrode; the deposited metals are Ti, Al and TiN from bottom to top, and the thicknesses of the metals are 20nm, 100nm and 200nm respectively; the conditions adopted for electron beam evaporation were: vacuum degree ≦ 2.0X 10-6Torr, deposition rate less than
Figure BDA0001530467390000112
The process conditions of the rapid thermal annealing are as follows: the temperature is 550 ℃ and the time is 90 s;
13) defining a photoetching isolation mask, and carrying out isolation by adopting an ion implantation mode to form an active region; the injection conditions were: the ion is B+Current 10 μ Α, energy 200KeV, dose 5e 14;
14) depositing a 200nm SiN passivation layer on the grid electrode 6, the source electrode, the drain electrode and the surface of the AlGaN/GaN heterojunction by adopting PECVD; the SiN deposition process conditions are as follows: gases are SiH respectively4、NH3He and N2The flow rate is respectively 8sccm, 2sccm, 100sccm and 200sccm, the pressure is 500mTorr, the temperature is 260 ℃, and the power is 25W;
15) defining an interconnection open hole area mask, and etching to form interconnection open holes; the etching process conditions are as follows: the gas being SF6The flow rate is 20sccm, and the pressure is 0.2 pa;
16) defining an interconnection metal area mask, and forming interconnection metal through evaporation and stripping processes; vacuum degree ≦ 1.5X 10- 6Torr, deposition rate less than
Figure BDA0001530467390000113
The deposited metal lamination layers are Ti and Al from bottom to top, and the thicknesses of the metal lamination layers are respectively 30nm and 500 nm.
Example 2: the material for preparing the substrate 1 is GaN, the width of the GaN-based three-dimensional fins 3 is 600nm, the height of the GaN-based three-dimensional fins is 600nm, the distance between the adjacent GaN-based three-dimensional fins is 1500nm, the gate metal is TiN/Al, and the three-dimensional GaN enhancement type high electron mobility transistor with the built-in terminal structure 4 is formed by adopting B ion implantation, wherein the specific steps of the process flow comprise:
1) growing an unintentionally doped GaN layer with the thickness of 2 mu m at the temperature of 1000 ℃ by utilizing the Metal Organic Chemical Vapor Deposition (MOCVD) technology above the GaN substrate 1 to form a buffer layer 2;
2) depositing 100nm Ni as a hard mask above the buffer layer 2 in an electron beam evaporation mode; the evaporation conditions were: vacuum degree ≦ 1.5X 10-6Torr, deposition rate less than
Figure BDA0001530467390000121
3) A photolithographic mask of the GaN-based three-dimensional fin 3 is defined above the Ni hard mask, and then the hard mask is removed by ICP etching. The Ni etching process conditions are as follows: ar is used as gas, the flow rate is 50sccm, and the pressure is 0.4 pa;
4) etching GaN by an ICP (inductively coupled plasma) mode to form a GaN-based three-dimensional fin 3; the width of the GaN-based three-dimensional fins 3 is 600nm, and the interval between adjacent GaN-based three-dimensional fins 3 is 1500 nm; the etching process conditions are as follows: the gases are respectively BCl3And Cl2The flow rate is respectively 25sccm and 5sccm, the pressure is 30mTorr, the power of an upper electrode is 100W, the power of a lower electrode is 10W, and the etching depth is 600 nm;
5) removing etching damage by adopting TMAH, and then injecting B ions into the buffer layer 2 to form a built-in terminal structure; the implantation energy of B ions is 100 KeV;
6) removing Ni metal by nitric acid;
7) MBE is adopted to grow p-GaN/AlGaN/GaN heterojunction 5 on the surface and the side surface of the buffer layer 2 and the GaN-based three-dimensional fin 3; the thickness of the p-GaN is 100nm, and the doping concentration is 5 multiplied by 1018cm-3The p-type doped material is Fe; the thickness of AlGaN is 12nm, the composition of Al is 28%, and the thickness of GaN is 100 nm;
8) sequentially depositing gate metals of 100nm TiN and 250nm Al on the surface of the p-GaN/AlGaN/GaN heterojunction 5 above the GaN-based three-dimensional fin 3 in a sputtering mode, and then depositing a 50nm blocking dielectric layer SiN in a PECVD mode; the TiN sputtering conditions were: vacuum degree ≦ 1.5X 10-6Torr, deposition rate less than
Figure BDA0001530467390000122
The SiN deposition process conditions are as follows: gases are SiH respectively4、NH3He and N2The flow rate is respectively 8sccm, 2sccm, 100sccm and 200sccm, the pressure is 500mTorr, the temperature is 260 ℃, and the power is 25W;
9) photoetching a grid mask, and sequentially etching the SiN blocking dielectric layer and the TiN/Al grid metal by adopting an ICP (inductively coupled plasma) mode to form a grid 6; the etching process conditions of SiN and TiN are as follows: the gas being SF6The flow rate was 20sccm and the pressure was 0.2 pa. The etching process conditions of Al are as follows: the gas being Cl2The flow rate is 35sccm, the pressure is 30mTorr, the power of the upper electrode is 200W, and the power of the lower electrode is 10W;
10) this step is the same as step 10) of example 1;
11) this step is the same as step 11) of example 1;
12) photoetching source and drain electrode masks on two sides of the grid electrode 6, evaporating source and drain electrode metal by an electron beam, and annealing at high temperature to form a source electrode and a drain electrode; the deposited metals are respectively Ti, Al, Ni and Au with the thickness of 20 from bottom to topnm, 150nm, 30nm and 50 nm; the conditions adopted for electron beam evaporation were: vacuum degree ≦ 2.0X 10-6Torr, deposition rate less than
Figure BDA0001530467390000131
The process conditions of the rapid thermal annealing are as follows: the temperature is 850 ℃ and the time is 30 s;
13) this step is the same as step 13) of example 1;
14) this step is the same as step 14) of example 1;
15) this step is the same as step 15) of example 1;
16) defining an interconnection metal area mask, and forming interconnection metal through evaporation and stripping processes; vacuum degree ≦ 1.5X 10- 6Torr, deposition rate less than
Figure BDA0001530467390000132
The deposited metal lamination layers are Ti and Au from bottom to top, and the thicknesses of the metal lamination layers are respectively 30nm and 300 nm.
Example 3: the material for preparing the substrate 1 is SiC, the width of the GaN-based three-dimensional fins 3 is 1000nm, the height of the GaN-based three-dimensional fins is 400nm, the adjacent distance between the GaN-based three-dimensional fins is 800nm, the gate metal is Pt, and F ion implantation is adopted to form the three-dimensional GaN enhancement type high electron mobility transistor with the built-in terminal structure, and the specific steps of the technological process comprise:
1) on the SiC substrate 1, by using the metal organic chemical vapor deposition MOCVD technology, AlN of 250nm is firstly grown at 1050 ℃, and then an unintentionally doped GaN layer of 3 mu m is grown at 1000 ℃ to form a buffer layer 2;
2) depositing 50nm SiN and 300nm SiO on the buffer layer 2 by PECVD in sequence2As a hard mask; the SiN deposition process conditions are as follows: gases are SiH respectively4、NH3He and N2The flow rate is respectively 8sccm, 2sccm, 100sccm and 200sccm, the pressure is 500mTorr, the temperature is 260 ℃, and the power is 25W; SiO 22The deposition process conditions are as follows: gases are SiH respectively4、N2O, He and N2The flow rates are respectively 10sccm, 3sccm, 100sccm and 200sccm, the pressure is 400mTorr, the temperature is 260 ℃,the power is 25W;
3) in SiN/SiO2Defining a photoetching mask of the GaN-based three-dimensional fin 3 above the hard mask, and then etching and removing the hard mask in an ICP (inductively coupled plasma) mode; the etching process conditions are as follows: the gas being SF6The flow rate is 50sccm, and the pressure is 0.5 pa;
4) etching GaN by an ICP (inductively coupled plasma) mode to form a GaN-based three-dimensional fin 3; the width of the GaN-based three-dimensional fins 3 is 1000nm, and the interval between adjacent GaN-based three-dimensional fins 3 is 800 nm; the etching process conditions are as follows: the gases are respectively BCl3And Cl2The flow rate is respectively 25sccm and 5sccm, the pressure is 30mTorr, the power of an upper electrode is 100W, the power of a lower electrode is 10W, and the etching depth is 400 nm;
5) removing etching damage by adopting TMAH, and then injecting F ions into the buffer layer 2 to form a built-in terminal structure 4; the energy of F ion implantation is 200 KeV;
6) removing SiN and SiO by HF acid2；
7) Growing a p-GaN/AlGaN/GaN heterojunction 5 on the surface and the side surface of the buffer layer 2 and the GaN-based three-dimensional fin 3 by MOCVD; the thickness of the p-GaN is 70nm, and the doping concentration is 4 multiplied by 1019cm-3The p-type doped material is Ca; AlGaN has a thickness of 20nm, Al has a composition of 20%, and GaN has a thickness of 50 nm.
8) Photoetching source and drain masks at two ends of the p-GaN/AlGaN/GaN heterojunction 5, then etching and removing p-type GaN in an ICP mode, depositing source and drain metals through magnetron sputtering, and annealing at high temperature to form a source electrode and a drain electrode; the p-GaN etching process conditions are as follows: the gases are respectively BCl3And Cl2The flow rate is respectively 25sccm and 5sccm, the pressure is 30mTorr, the power of the upper electrode is 100W, and the power of the lower electrode is 10W; the sputtered source drain metals are Ti, Al and W from bottom to top, and the thicknesses of the sputtered source drain metals are 20nm, 100nm and 100nm respectively; the conditions adopted for sputtering are as follows: vacuum degree ≦ 2.0X 10-6Torr, deposition rate less than
Figure BDA0001530467390000141
The process conditions of the rapid thermal annealing are as follows: the temperature is 900 ℃, and the time is 30 s;
9) photoetching a grid mask on the surface of the p-GaN/AlGaN/GaN heterojunction 5 above the GaN-based three-dimensional fin 3, and adoptingDepositing Pt metal in an evaporation mode, and forming a grid electrode 6 through a stripping process; the conditions adopted for Pt evaporation were: vacuum degree ≦ 2.0X 10- 6Torr, deposition rate less than
Figure BDA0001530467390000142
The thickness is 130 nm;
10) etching and removing the p-type GaN outside the source electrode, the drain electrode and the grid electrode region in an ICP mode by taking the source electrode, the drain electrode and the grid electrode 6 as masks to form an AlGaN/GaN heterojunction; the p-GaN etching process conditions are as follows: the gases are respectively BCl3And Cl2The flow rate is respectively 25sccm and 5sccm, the pressure is 30mTorr, the power of the upper electrode is 100W, and the power of the lower electrode is 10W;
11) defining a photoetching isolation mask, and carrying out isolation by adopting an ion implantation mode to form an active region; the injection conditions were: the ion being Ar+Current 10 μ Α, energy 300KeV, dose 8e 14;
12) this step is the same as step 14) of example 1;
13) this step is the same as step 15) of example 1;
14) this step is the same as step 16) of example 1.
Example 4: the material for preparing the substrate 1 is diamond, the width of the GaN-based three-dimensional fins 3 is 2000nm, the height of the GaN-based three-dimensional fins is 200nm, the adjacent distance between the GaN-based three-dimensional fins is 200nm, the gate metal is Ni/Au, O ion injection is adopted to form the three-dimensional GaN enhancement type high electron mobility transistor with a built-in terminal structure, and the specific steps of the technical process comprise:
1) on the diamond substrate 1, by utilizing the metal organic chemical vapor deposition MOCVD technology, AlN of 50nm is firstly grown at 900 ℃, and then an unintentionally doped GaN layer of 2.6 mu m is grown at 1000 ℃ to form a buffer layer 2;
2) depositing 50nm Ge and 300nm SiO above the buffer layer 2 by magnetron sputtering2As a hard mask; the sputtering conditions were: vacuum degree ≦ 1.5X 10-6Torr, deposition rate less than
Figure BDA0001530467390000151
3) In Ge/SiO2Defining a photoetching mask of the GaN-based three-dimensional fin 3 above the hard mask, and then etching and removing the hard mask in an ICP (inductively coupled plasma) mode; the etching process conditions are as follows: the gas being SF6The flow rate is 50sccm, and the pressure is 0.5 pa;
4) etching GaN by an ICP (inductively coupled plasma) mode to form a GaN-based three-dimensional fin 3; the width of the GaN-based three-dimensional fins 3 is 2000nm, and the interval between adjacent GaN-based three-dimensional fins 3 is 200 nm; the etching process conditions are as follows: the gases are respectively BCl3And Cl2The flow rate is respectively 25sccm and 5sccm, the pressure is 30mTorr, the power of an upper electrode is 100W, the power of a lower electrode is 10W, and the etching depth is 200 nm;
5) removing etching damage by adopting wet HCl, and then injecting O ions into the buffer layer 2 to form a built-in terminal structure 4; the energy of O ion implantation is 300 KeV;
6) successively using BOE and H2O2Removal of SiO2And Ge metal;
7) MBE is adopted to grow p-GaN/AlGaN/GaN heterojunction 5 on the surface and the side surface of the buffer layer 2 and the GaN-based three-dimensional fin 3; the thickness of the p-GaN is 40nm, and the doping concentration is 5 multiplied by 1020cm-3The p-type doped material is C; AlGaN has a thickness of 30nm, Al has a composition of 15%, and GaN has a thickness of 50 nm.
8) This step is the same as step 8) of example 3;
9) photoetching a grid mask on the surface of a p-GaN/AlGaN/GaN heterojunction 5 above a GaN-based three-dimensional fin 3, sequentially depositing Ni and Au grid metal in an evaporation mode, and forming a grid 6 through a stripping process; the conditions adopted for evaporating Ni and Au were: vacuum degree ≦ 2.0X 10-6Torr, deposition rate less than
Figure BDA0001530467390000152
The thicknesses of the film are respectively 30nm and 470 nm;
10) this step is the same as step 10) of example 3;
11) defining a photoetching isolation mask, and carrying out device isolation by adopting an ion implantation mode to form an active region; the injection conditions were: the ion being O+Current 15 muA, energy 150KeV, dose 2e15；
12) This step is the same as step 14) of example 1;
13) this step is the same as step 15) of example 1;
14) this step is the same as step 16) of example 2.
Descriptions not related to the embodiments of the present invention are well known in the art, and may be implemented by referring to the well-known techniques.
The above embodiments and examples are specific supports for the technical ideas of the three-dimensional enhanced high electron mobility transistor based on the p-GaN structure and the manufacturing method thereof, and the protection scope of the present invention is not limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical scheme according to the technical ideas presented by the present invention still belong to the protection scope of the technical scheme of the present invention.

Claims (9)

1.一种基于p-GaN结构的三维增强型高电子迁移率晶体管，所述三维增强型高电子迁移率晶体管的结构自下而上依次包括衬底(1)、缓冲层(2)、GaN基三维鳍片(3)、栅极(6)、源极和漏极，其特征在于，还包括内置终端结构(4)，所述内置终端结构(4)为通过离子注入形成的内置高阻GaN区，所述内置GaN高阻区位于所述栅极(6)的下方与GaN基三维鳍片(3)的两侧区域相邻的缓冲层(2)的上方；所述GaN基三维鳍片(3)的上方及两侧二次外延生长有p-GaN/AlGaN/GaN异质结(5)；所述栅极(6)包裹在p-GaN/AlGaN/GaN异质结(5)的上方和两侧，形成三维栅结构；通过刻蚀方式去除栅极(6)两侧区域的p-GaN层而形成AlGaN/GaN异质结，所述源极和漏极分别设在AlGaN/GaN异质结的两端。1. A three-dimensional enhancement type high electron mobility transistor based on a p-GaN structure, the structure of the three-dimensional enhancement type high electron mobility transistor sequentially comprises a substrate (1), a buffer layer (2), a GaN layer from bottom to top A base three-dimensional fin (3), a gate (6), a source electrode and a drain electrode, characterized in that it further comprises a built-in terminal structure (4), wherein the built-in terminal structure (4) is a built-in high resistance formed by ion implantation GaN region, the built-in GaN high-resistance region is located below the gate (6) and above the buffer layer (2) adjacent to the two sides of the GaN-based three-dimensional fin (3); the GaN-based three-dimensional fin A p-GaN/AlGaN/GaN heterojunction (5) is secondary epitaxially grown on the top and both sides of the sheet (3); the gate (6) is wrapped in the p-GaN/AlGaN/GaN heterojunction (5) Above and on both sides of the gate, a three-dimensional gate structure is formed; the p-GaN layer on both sides of the gate (6) is removed by etching to form an AlGaN/GaN heterojunction, and the source and drain electrodes are respectively set on the AlGaN/GaN Both ends of a GaN heterojunction. 2.根据权利要求1所述的一种基于p-GaN结构的三维增强型高电子迁移率晶体管，其特征在于，所述GaN基三维鳍片(3)的高度为200～1000nm、宽度为200～2000nm；所述GaN基三维鳍片(3)的数量为n≥1，所述GaN基三维鳍片(3)的相邻之间的间距为200～2000nm。2 . A three-dimensional enhancement mode high electron mobility transistor based on a p-GaN structure according to claim 1 , wherein the GaN-based three-dimensional fins ( 3 ) have a height of 200-1000 nm and a width of 200 nm. 3 . ~2000 nm; the number of the GaN-based three-dimensional fins (3) is n≧1, and the spacing between adjacent ones of the GaN-based three-dimensional fins (3) is 200-2000 nm. 3.根据权利要求2所述的一种基于p-GaN结构的三维增强型高电子迁移率晶体管，其特征在于，所述p-GaN/AlGaN/GaN异质结(5)的p-GaN的厚度为40～150nm、p型掺杂浓度为1017～5×1020cm-3、p型掺杂元素为Mg、Fe、Zn、C和Ca中的任一种；AlGaN的厚度为5～30nm、Al的组分为10～40％；GaN的厚度为20～200nm。3. A three-dimensional enhancement mode high electron mobility transistor based on a p-GaN structure according to claim 2, wherein the p-GaN of the p-GaN/AlGaN/GaN heterojunction (5) has a The thickness is 40～150nm, the p-type doping concentration is 10 17 ～5×10 20 cm -3 , the p-type doping element is any one of Mg, Fe, Zn, C and Ca; the thickness of AlGaN is 5～ 30nm, the composition of Al is 10-40%; the thickness of GaN is 20-200nm. 4.根据权利要求1所述的一种基于p-GaN结构的三维增强型高电子迁移率晶体管的制造方法，其特征在于，包括如下具体步骤：4. a kind of manufacture method of the three-dimensional enhancement type high electron mobility transistor based on p-GaN structure according to claim 1, is characterized in that, comprises following concrete steps: 1)在所述衬底(1)的上方生长缓冲层(2)；1) growing a buffer layer (2) on the substrate (1); 2)在所述缓冲层(2)的上方沉积金属或绝缘介质作为硬掩模；2) depositing a metal or insulating medium as a hard mask on the buffer layer (2); 3)在所述硬掩模的上方定义GaN基三维鳍片(3)的光刻掩模，随后通过RIE和ICP方式刻蚀去除硬掩模；3) defining a photolithography mask for the GaN-based three-dimensional fin (3) above the hard mask, and then removing the hard mask by RIE and ICP etching; 4)通过RIE和ICP方式刻蚀GaN，形成GaN基三维鳍片(3)；所述GaN基三维鳍片(3)的高度为200～1000nm、宽度为200～2000nm；所述GaN基三维鳍片(3)的相邻之间的间距为200～2000nm；4) Etching GaN by RIE and ICP to form a GaN-based three-dimensional fin (3); the GaN-based three-dimensional fin (3) has a height of 200-1000 nm and a width of 200-2000 nm; the GaN-based three-dimensional fin (3) is The spacing between adjacent pieces (3) is 200-2000 nm; 5)采用TMAH或等离子处理方式去除刻蚀损伤，随后将离子注入缓冲层(2)形成内置终端结构(4)；所述离子注入的元素为Ar、H、B、O、N、He、Zn和F中的任一种，所述离子注入的能量为30～300KeV；5) The etching damage is removed by TMAH or plasma treatment, and then ions are implanted into the buffer layer (2) to form a built-in terminal structure (4); the ion implanted elements are Ar, H, B, O, N, He, Zn and F, the energy of the ion implantation is 30-300KeV; 6)采用湿法或干法方式去除硬掩模；6) Remove the hard mask by wet or dry method; 7)在所述缓冲层(2)和GaN基三维鳍片(3)的表面和侧面，采用MOCVD、MBE和PLD方式生长p-GaN/AlGaN/GaN异质结(5)；所述p-GaN/AlGaN/GaN异质结(5)的p-GaN的厚度为40～150nm、p型掺杂浓度为1017～5×1020cm-3、p型掺杂材料为Mg、Fe、Zn、C和Ca中的任一种；AlGaN的厚度为5～30nm、Al的组分为10～40％；GaN的厚度为20～200nm；7) On the surface and side surfaces of the buffer layer (2) and the GaN-based three-dimensional fin (3), a p-GaN/AlGaN/GaN heterojunction (5) is grown by MOCVD, MBE and PLD; The thickness of the p-GaN of the GaN/AlGaN/GaN heterojunction (5) is 40-150 nm, the p-type doping concentration is 10 17 -5×10 20 cm -3 , and the p-type doping materials are Mg, Fe, Zn , any one of C and Ca; the thickness of AlGaN is 5-30nm, the composition of Al is 10-40%; the thickness of GaN is 20-200nm; 8)在GaN基三维鳍片(3)上方的p-GaN/AlGaN/GaN异质结(5)表面采用蒸发或溅射方式沉积栅金属，随后采用ALD、PECVD、ICP-CVD和LPCVD方式沉积阻挡介质层；8) The gate metal is deposited by evaporation or sputtering on the surface of the p-GaN/AlGaN/GaN heterojunction (5) above the GaN-based three-dimensional fin (3), and then deposited by ALD, PECVD, ICP-CVD and LPCVD barrier dielectric layer; 9)光刻栅极掩模，采用RIE和ICP方式依次刻蚀阻挡介质层和栅金属，形成栅极(6)；9) photolithography gate mask, using RIE and ICP to sequentially etch the blocking dielectric layer and the gate metal to form the gate (6); 10)以所述阻挡介质层作为掩模，通过RIE和ICP方式刻蚀去除栅极(6)区域之外的p型GaN，形成AlGaN/GaN异质结；10) Using the blocking dielectric layer as a mask, the p-type GaN outside the gate (6) region is removed by RIE and ICP etching to form an AlGaN/GaN heterojunction; 11)采用湿法腐蚀去除阻挡介质层；11) Remove the barrier dielectric layer by wet etching; 12)在栅极(6)的两侧，光刻源漏掩模，随后沉积源漏金属，高温退火形成源极和漏极；12) On both sides of the gate electrode (6), source and drain masks are lithographically etched, then source and drain metal are deposited, and source and drain electrodes are formed by high temperature annealing; 13)定义光刻隔离掩模，采用刻蚀或离子注入方式进行隔离，形成有源区；13) Define a photolithography isolation mask, and isolate it by etching or ion implantation to form an active region; 14)在栅极(6)、源极、漏极和AlGaN/GaN异质结的表面，采用ALD、PECVD和ICP-CVD方式沉积钝化介质层；14) On the surfaces of the gate (6), the source, the drain and the AlGaN/GaN heterojunction, a passivation dielectric layer is deposited by ALD, PECVD and ICP-CVD; 15)定义互联开孔区掩模，刻蚀形成互联开孔；15) Define the mask of the interconnect opening area, and etch to form the interconnect opening; 16)定义互联金属区掩模，通过蒸发与剥离工艺形成互联金属。16) Define an interconnect metal region mask, and form interconnect metal through evaporation and lift-off processes. 5.根据权利要求1任一项所述的一种基于p-GaN结构的三维增强型高电子迁移率晶体管的制造方法，其特征在于，包括如下具体步骤：5. The manufacturing method of a three-dimensional enhancement mode high electron mobility transistor based on a p-GaN structure according to any one of claims 1, wherein the method comprises the following specific steps: 1)在所述衬底(1)的上方生长缓冲层(2)；1) growing a buffer layer (2) on the substrate (1); 2)在所述缓冲层(2)的上方沉积金属或绝缘介质作为硬掩模；2) depositing a metal or insulating medium as a hard mask on the buffer layer (2); 3)在所述硬掩模的上方定义GaN基三维鳍片(3)的光刻掩模，随后通过RIE和ICP方式刻蚀去除硬掩模；3) defining a photolithography mask for the GaN-based three-dimensional fin (3) above the hard mask, and then removing the hard mask by RIE and ICP etching; 4)通过RIE和ICP方式刻蚀GaN，形成GaN基三维鳍片(3)；所述GaN基三维鳍片(3)的高度为200～1000nm、宽度为200～2000nm；所述GaN基三维鳍片(3)的相邻之间的间距为200～2000nm；4) Etching GaN by RIE and ICP to form a GaN-based three-dimensional fin (3); the GaN-based three-dimensional fin (3) has a height of 200-1000 nm and a width of 200-2000 nm; the GaN-based three-dimensional fin (3) is The spacing between adjacent pieces (3) is 200-2000 nm; 5)采用TMAH或等离子处理方式去除刻蚀损伤，随后将离子注入缓冲层(2)形成内置终端结构(4)；所述离子注入的元素为Ar、H、B、O、N、He、Zn和F中的任一种，所述离子注入的能量为30～300KeV；5) The etching damage is removed by TMAH or plasma treatment, and then ions are implanted into the buffer layer (2) to form a built-in terminal structure (4); the ion implanted elements are Ar, H, B, O, N, He, Zn and F, the energy of the ion implantation is 30-300KeV; 6)采用湿法或干法方式去除硬掩模；6) Remove the hard mask by wet or dry method; 7)在所述缓冲层(2)和GaN基三维鳍片(3)的表面和侧面，采用MOCVD、MBE和PLD方式生长p-GaN/AlGaN/GaN异质结(5)；所述p-GaN/AlGaN/GaN异质结(5)的p-GaN的厚度为40～150nm、p型掺杂浓度为1017～5×1020cm-3、p型掺杂材料为Mg、Fe、Zn、C和Ca中的任一种；AlGaN的厚度为5～30nm、Al的组分为10～40％；GaN的厚度为20～200nm；7) On the surface and side surfaces of the buffer layer (2) and the GaN-based three-dimensional fin (3), a p-GaN/AlGaN/GaN heterojunction (5) is grown by MOCVD, MBE and PLD; The thickness of the p-GaN of the GaN/AlGaN/GaN heterojunction (5) is 40-150 nm, the p-type doping concentration is 10 17 -5×10 20 cm -3 , and the p-type doping materials are Mg, Fe, Zn , any one of C and Ca; the thickness of AlGaN is 5-30 nm, the composition of Al is 10-40%; the thickness of GaN is 20-200 nm; 8)在所述p-GaN/AlGaN/GaN异质结(5)两端光刻源漏掩模，随后通过RIE和ICP方式刻蚀去除p型GaN，沉积源漏金属，高温退火形成源极和漏极；8) Photolithography source-drain masks at both ends of the p-GaN/AlGaN/GaN heterojunction (5), then remove p-type GaN by RIE and ICP etching, deposit source-drain metal, and anneal at high temperature to form source electrodes and drain; 9)在GaN基三维鳍片(3)上方的p-GaN/AlGaN/GaN异质结(5)表面光刻栅极掩模，采用蒸发或溅射方式沉积栅金属，通过剥离工艺，形成栅极(6)；9) Photolithography gate mask on the surface of the p-GaN/AlGaN/GaN heterojunction (5) above the GaN-based three-dimensional fin (3), deposit gate metal by evaporation or sputtering, and form a gate through a lift-off process pole(6); 10)以所述源极、漏极和栅极(6)作为掩模，通过RIE和ICP方式刻蚀去除源极、漏极和栅极(6)区域之外的p型GaN，形成AlGaN/GaN异质结；10) Using the source, drain and gate (6) as masks, the p-type GaN outside the source, drain and gate (6) regions is removed by RIE and ICP etching to form AlGaN/ GaN heterojunction; 11)定义光刻隔离掩模，采用刻蚀或离子注入方式进行器件隔离，形成有源区；11) Define a photolithography isolation mask, and use etching or ion implantation to isolate devices to form active regions; 12)在栅极(6)、源极、漏极和AlGaN/GaN异质结表面，采用ALD、PECVD和ICP-CVD方式沉积钝化介质层；12) On the gate (6), the source, the drain and the surface of the AlGaN/GaN heterojunction, adopt ALD, PECVD and ICP-CVD to deposit a passivation dielectric layer; 13)定义互联开孔区掩模，刻蚀形成互联开孔；13) Define the mask of the interconnection opening area, and etch to form the interconnection opening; 14)定义互联金属区掩模，通过蒸发与剥离工艺形成互联金属。14) Define an interconnect metal region mask, and form interconnect metal through evaporation and lift-off processes. 6.根据权利要求4或5所述的一种基于p-GaN结构的三维增强型高电子迁移率晶体管的制造方法，其特征在于，步骤1)所述衬底(1)的材质为Si、金刚石、SiC、蓝宝石和GaN自支撑衬底中的任一种。6. The method for manufacturing a three-dimensional enhancement mode high electron mobility transistor based on a p-GaN structure according to claim 4 or 5, wherein in step 1) the substrate (1) is made of Si, Any of diamond, SiC, sapphire and GaN free-standing substrates. 7.根据权利要求4或5所述的一种基于p-GaN结构的三维增强型高电子迁移率晶体管的制造方法，其特征在于，步骤2)所述硬掩模的材质为Ni、W、Ge、SiN和SiO2中的任一种或多种组合。7. The method for manufacturing a three-dimensional enhancement mode high electron mobility transistor based on a p-GaN structure according to claim 4 or 5, wherein in step 2) the material of the hard mask is Ni, W, Any one or a combination of Ge, SiN and SiO 2 . 8.根据权利要求4所述的一种基于p-GaN结构的三维增强型高电子迁移率晶体管的制造方法，其特征在于，步骤8)所述栅金属包括Pd/Au、W/Al、Ni/Au、Mo/Au、WN/Al、Pt、TiN和W中的任一种多层金属或单层金属，所述栅金属的厚度为50～500nm。8. The method for manufacturing a three-dimensional enhancement mode high electron mobility transistor based on a p-GaN structure according to claim 4, wherein in step 8) the gate metal comprises Pd/Au, W/Al, Ni /Au, Mo/Au, WN/Al, Pt, TiN and W any multi-layer metal or single-layer metal, the thickness of the gate metal is 50-500 nm. 9.根据权利要求5所述的一种基于p-GaN结构的三维增强型高电子迁移率晶体管的制造方法，其特征在于，步骤9)所述栅金属包括Pd/Au、W/Al、Ni/Au、Mo/Au、WN/Al、Pt、TiN和W中的任一种多层金属或单层金属，所述栅金属的厚度为50～500nm。9. The method for manufacturing a three-dimensional enhancement mode high electron mobility transistor based on a p-GaN structure according to claim 5, wherein in step 9) the gate metal comprises Pd/Au, W/Al, Ni /Au, Mo/Au, WN/Al, Pt, TiN and W any multi-layer metal or single-layer metal, the thickness of the gate metal is 50-500 nm.
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