CN100495682C - A Method for Monolithic Integration of RTD and HEMT Using Dry Etching Technology - Google Patents

Abstract

A method for realizing monolithic integration of RTD and HEMT by using dry etching technology, including such as: growing a typical HEMT material structure and RTD material structure sequentially on a substrate; photoetching out the pattern of the RTD emission region to prepare an AuGeNi metal layer, Form the RTD metal emitter; photolithography, form the active region; photolithography out the source and drain electrodes of the HEMT; high temperature annealing; layer passivation dielectric layer; photoetching the gate electrode pattern of HEMT to generate TiPtAu metal as the gate electrode of HEMT device; photoetching the lead hole; photoetching the lead interconnection area, evaporating or sputtering thick TiAlTiAu metal electrode, peeling off the glue .

Description

A Method for Monolithic Integration of RTD and HEMT Using Dry Etching Technology

technical field

The invention belongs to the technical field of semiconductors, in particular to the technology of preparing resonant tunneling diodes and transistor monolithic integrated circuits on III-V substrates.

Background technique

Since the industrialized mass production of silicon large-scale integrated circuits in the 1960s, Moore's Law has been followed to improve circuit performance through the reduction of feature size, achieving higher integration, faster speed and lower power consumption. Because of this, at the end of the last century, Intel delivered Pentium processor chips and personal computers with unprecedented levels of integration and performance to users. At present, the characteristic size of MOSFET has reached 45nm, and then as the characteristic size approaches the nanometer scale, quantum effects gradually appear and dominate, and some problems such as metal interconnection, current tunneling and power consumption are becoming more and more prominent, which will greatly hinder its development. Proceeding with the development process, the scaling down approach will be more difficult to continue. Theoretical analysis points out that 20-30nm may be the physical limit of the feature size of CMOS devices. This not only refers to the physical limitations and lithography technology limitations brought about by the influence of quantum size effects on the characteristics of existing devices, but more importantly, it will be affected by the material limitations of its own nature.

In order to reduce the feature size of the device, thereby achieving the purpose of improving the performance of the device as a whole, people hope to find other methods to avoid the above-mentioned difficulties. In experiments that sought to suppress short-channel effects, it was found that tunneling devices based on quantum tunneling outperform conventional MOSFETs when the feature size approaches the physical limit. In other words, quantum devices based on tunneling devices are more suitable for the development of nanoelectronics than MOSFETs.

Resonant tunneling diode (RTD) is a quantum device that utilizes the tunneling effect on the nanometer scale to achieve switching characteristics. As the first practical and currently most mature nanoelectronic device, the theoretical value of RTD peak-to-valley transition frequency is as high as 2.5THz, the actual device oscillation frequency reaches 712GHz, and the actual device switching time reaches 1.5ps. Because of its high speed and low power consumption, and its unique differential negative resistance characteristics can simplify the complexity of the circuit, it attracts people's attention. The main advantage of RTD is that its multiple steady-state characteristics can be used to make very compact circuits, and its intrinsic speed can enter the GHz range. RTDs are used today in many applications such as A/D and D/A converters, flip-flops, clock quantizers, frequency dividers, shift registers, adders, memories, programmable logic gates, and many others.

In terms of materials, RTD mainly uses molecular beam epitaxy (MBE) technology or metal organic compound vapor deposition (MOCVD) technology to grow a thin layer of narrow-bandgap semiconductor with a suitable thickness to form a quantum well region, and then grow a wide-bandgap semiconductor on it. layer to get the barrier layer. Since the thickness of the thin layer grown by MOCVD and MBE technology can be controlled within a few nanometers, the thickness of quantum wells and potential barriers can be controlled within a few nanometers. The barrier thickness of the RTD is equivalent to the length of the "channel" of the MOSFET. The electrons crossing the "channel" rely on the quantum tunneling motion which is much faster than the drift motion, so the speed performance of the RTD should be better than that of the MOSFET. In fact, RTD does not have a channel like MOSFET, so there will be no short channel effect. Its unique differential resistance characteristics can be used to complete equivalent functions with a small number of devices: for example, two RTDs connected back-to-back and a transistor are used to form an SRAM unit, which not only saves chip area but also reduces power consumption. The materials for making RTD are mainly III-V compound semiconductors, and the most suitable material is the InAlAs/InGaAs material system, that is, the quantum well is the narrow bandgap semiconductor InGaAs, and the potential barrier is the wide bandgap semiconductor AlAs. InP and GaAs are different from silicon, they are all direct bandgap materials, which have the characteristics of high electron saturation drift speed, high temperature resistance, and radiation resistance. It has unique advantages in ultra-high-speed, ultra-high-frequency, low-power, low-noise devices and circuits, especially in optoelectronic devices and optoelectronic integration.

Since RTD is a two-terminal device and cannot realize current modulation, it needs to be combined with a three-terminal device when forming a circuit. Due to the high electron mobility, high-speed devices made of compound semiconductor materials such as GaAs and InP are widely used in the microwave and millimeter wave range, and the high electron mobility transistor (HEMT) is one of the representatives. Using semiconductor planar technology to integrate RTDs and HEMTs based on quantum tunneling effects on GaAs or InP substrates, the formed circuits not only maintain the characteristics of high frequency, low noise and low power consumption, but also achieve the same function The number of components required by other device circuits is much smaller, so the circuit structure is greatly simplified, the chip area is reduced, and the integration level is improved. It has important applications in digital and hybrid circuits.

At present, the monolithic integration of RTD and HEMT is mainly realized by wet etching. However, due to the common lateral corrosion in the wet process, the size of the device cannot be accurately controlled, and it is not suitable for the production of small-sized device circuits. Moreover, due to the consistency of the wet method, uniform corrosion cannot be achieved on the entire wafer (especially above 4 inches), which is not conducive to the integration of large-scale devices, and does not meet the needs of industrialized mass production.

Contents of the invention

The object of the present invention is to provide a method for monolithic integration of RTD and HEMT using dry etching technology, which causes less damage to the device, and has better directionality, and is more suitable for the production of tiny sizes; It can be realized, the yield rate is improved, and it is suitable for the needs of industrial production of micro-nano-sized RTD and HEMT monolithic integrated circuits in the future.

A kind of method adopting dry etching technique of the present invention to realize RTD and HEMT monolithic integration is characterized in that, comprises the following steps:

Step 1: sequentially grow a typical HEMT material structure and RTD material structure on the substrate by molecular beam epitaxy or metal organic chemical vapor electrode;

Step 2: Lithograph the pattern of the RTD emission area, prepare the AuGeNi metal layer by evaporation or sputtering, remove the glue and peel off, and form the RTD metal emitter;

Step 3: Using non-selective ICP dry etching technology, using the RTD metal emitter as a mask, etch the RTD structure to the heavily doped InGaAs collector contact layer;

Step 4: using a highly selective wet etching solution to remove the residual InGaAs layer to expose the middle selective etching stop layer;

Step 5: removing the selective etch stop layer;

Step 6: Photolithography, forming the active area, using ICP dry etching technology to etch the outer part of the active area to the semi-insulating InP substrate, and removing the glue;

Step 7: Photoetching the source and drain electrodes of the HEMT, evaporating or sputtering AuGeNi metal to prepare the source and drain electrodes of the HEMT;

Step 8: performing rapid high-temperature annealing under a protective gas atmosphere;

Step 9: Photoetch the HEMT gate groove pattern, use selective ICP dry etching technology to etch away part of the heavily doped cap layer, stop the etching on the InAlAs barrier, and remove the glue;

Step 10: Depositing and growing a passivation dielectric layer on the surface of the device;

Step 11: photoetching the gate electrode pattern of the HEMT, digging out part of the passivation medium layer, and using evaporation or sputtering to generate TiPtAu metal as the gate electrode of the HEMT device;

Step 12: Lithographically cut out the lead hole, dig out the passivation medium layer on the metal electrode, and remove the glue;

Step 13: Photoetching out the lead interconnection area, evaporating or sputtering thick TiAlTiAu metal electrodes, and removing the glue.

The substrate is a semi-insulating InPIII-V substrate.

The HEMT material structure includes an InAlAs buffer layer, an InGaAs channel, an InAlAs isolation layer, a delta doped layer, an InAlAs barrier, a heavily doped InGaAs cap layer, and an InP selective etching stop layer grown sequentially.

The RTD material structure includes sequentially grown heavily doped InGaAs collector contact layer, InGaAs collector isolation layer, AlAs barrier, InGaAs/InAs/InGaAs well, AlAs barrier, InGaAs emitter isolation layer and heavily doped InGaAs Emitter contact layer.

The photolithography step is realized by conventional optical method or electron beam projection lithography or immersion photolithography.

Among them, the final lead wire interconnection is performed by conventional metal interconnection on dielectric layer or by air bridge technology.

The substrate can be either InP or GaAs, GaN and other compound semiconductors;

The growth of the HEMT material structure and the RTD material structure adopts the method of MBE or the method of MOCVD, or a combination of the two methods.

Among them, the highly selective wet etching solution is an inorganic acid solution or an organic acid solution.

The annealing time is 10 seconds to 30 minutes, and the annealing temperature is 200-500 degrees Celsius.

Wherein the passivation medium layer is an insulating medium layer of silicon oxide or silicon nitride or silicon oxynitride.

Compared with the wet etching technology, the dry etching method of the present invention has great advantages in the aspects of etching uniformity, directionality and improved yield, and is widely used in industrialized production. Inductively coupled plasma (ICP) etching produces higher plasma concentration under low voltage bias, and causes less damage to devices than general dry etching techniques such as reactive ion beam etching (RIE). At the same time, the directionality is better, and it is more suitable for the production of small sizes. Due to the better etching uniformity, the interface of the HEMT structure below is kept flat, which is beneficial to the improvement of the consistency of the threshold voltage and transconductance of the HEMT. The low-damage, repeatable ICP dry etching process is used to replace the traditional wet etching, and the anisotropic etching is used instead of the isotropic etching, which not only solves the problem of the consistency of the entire etching, but also enables the small line process to be realized. The yield rate is improved, and it is suitable for the industrial production of micro-nano size RTD and HEMT monolithic integrated circuits in the future.

Description of drawings

In order to further illustrate content of the present invention, the present invention is described in detail below in conjunction with embodiment, wherein:

Fig. 1 is a material structure diagram of the present invention;

Fig. 2 is the cross-sectional view of the device after the photolithography of the present invention generates the RTD mesa;

Figure 3 is a cross-sectional view of the photolithographic device of the present invention after isolation;

Fig. 4 is the sectional view of the device after photolithography of the present invention generates HEMT source and drain electrodes;

Fig. 5 is the cross-sectional view of the device after photoetching the gate groove of the present invention;

Figure 6 is a device cross-sectional view after depositing a silicon oxide passivation dielectric layer of the present invention;

Fig. 7 is a cross-sectional view of the device after the HEMT gate electrode is generated by photolithography of the present invention;

Fig. 8 is a cross-sectional view of the device after the lead hole is dug out by photolithography of the present invention;

Figure 9 is a final cross-sectional view of the device after thickening of the photolithographic lead interconnects of the present invention.

Detailed ways

Please refer to Fig. 1 to Fig. 9, a method for realizing monolithic integration of RTD and HEMT using dry etching technology in the present invention includes the following steps:

Step 1: sequentially grow a typical HEMT material structure 200 and an RTD material structure 300 (in FIG. 1 ) on the substrate 100 by means of molecular beam epitaxy or metal-organic chemical vapor electrodes, and the substrate 100 is a semi-insulating InPIII-V family Substrate; the HEMT material structure 200 includes sequentially grown InAlAs buffer layer 101, InGaAs channel 102, InAlAs isolation layer 103, delta doped layer, InAlAs potential barrier 104, heavily doped InGaAs cap layer 10

5 and an InP selective etching stop layer 106; the RTD material structure includes a heavily doped InGaAs collection region contact layer 107, an InGaAs collection region isolation layer 108, an AlAs barrier 109, an InGaAs110/InAs grown in sequence

111/InGaAs112 well, AlAs potential barrier 113, InGaAs emitter isolation layer 114 and heavily doped InGaAs emitter contact layer 115; the substrate can be either InP or GaAs, GaN and other compound semiconductors;

The growth of the HEMT material structure 200 and the RTD material structure 300 is grown by MBE method or MOCVD method, or a combination of both

Step 2: Photoetching out the pattern of the RTD emission area, preparing the AuGeNi metal layer 120 by evaporation or sputtering, removing the glue and peeling off, and forming the RTD metal emitter (in FIG. 2 ), the photolithography step adopts conventional optical method or by means of electron beam projection lithography or immersion lithography;

Step 3: using non-selective ICP dry etching technology, using the RTD metal emitter as a mask, etching the RTD structure to the heavily doped InGaAs collector contact layer 107;

Step 4: using a highly selective wet etching solution to remove the remaining InGaAs layer 107 to expose the intermediate selective etching stop layer 106; the highly selective wet etching solution is an inorganic acid solution or an organic acid solution;

Step 5: removing the selective etch stop layer 106;

Step 6: photolithography, forming an active region, using ICP dry etching technology to etch the outer part of the active region to the semi-insulating InP substrate 100, and removing the glue (in FIG. 3);

Step 7: Photoetching the source and drain electrodes of the HEMT, evaporating or sputtering AuGeNi metal to prepare the HEMT source electrode 121 and drain electrode 122 (in FIG. 4 );

Step 8: Perform rapid high-temperature annealing under a protective gas atmosphere, the annealing time is 10 seconds to 30 minutes, and the annealing temperature is 200-500 degrees Celsius;

Step 9: Photoetching out the HEMT gate groove pattern, using selective ICP dry etching technology to etch away part of the heavily doped cap layer 105, stopping the etching on the InAlAs barrier 104, and removing the glue (in FIG. 5);

Step 10: Deposit and grow a passivation dielectric layer 130 (in FIG. 6 ) on the device surface, wherein the passivation dielectric layer 130 is an insulating dielectric layer of silicon oxide or silicon nitride or silicon oxynitride;

Step 11: Photoetching the gate electrode pattern of the HEMT, digging out part of the passivation medium layer 130, and using evaporation or sputtering to generate TiPtAu metal as the gate electrode 123 of the HEMT device (in FIG. 7);

Step 12: photoetching lead holes, digging out the passivation medium layer 130 above the metal electrodes, and removing the glue (in FIG. 8);

Step 13: Lithograph the lead interconnection area, evaporate or sputter the thick TiAlTiAu metal electrode, remove the glue and peel off (in Figure 9), and finally conduct the lead interconnection by conventional metal interconnection on the dielectric layer or air bridge technology interconnection.

Example

Please refer to Fig. 1-Fig. 9 again, a kind of method that adopts dry etching technology to realize RTD and HEMT monolithic integration of the present invention, comprises the following steps:

Step 1: On the semi-insulating InP substrate 100, the material structure of HEMT and RTD is sequentially grown by molecular beam epitaxy: the HEMT structure includes a 2000A non-doped InAlAs buffer layer 101, a 150A non-doped InGaAs channel 102, and a 30A non-doped Doped InAlAs isolation layer 103, 4×1012cm-2delta planar doped layer, 200A non-doped InAlAs potential barrier 104 and 200A heavily doped InGaAs cap layer 105. This is followed by a 50AInP selective etch stop layer 106, and an RTD structure including a heavily doped 500AInGaAs collector contact layer 107, a 50A undoped collector spacer 108, a 16A undoped AlAs barrier 109, and a 13A undoped Doped InGaAs well 110, 18A non-doped InAs sub-well 111, 13A non-doped InGaAs well 112, 16A non-doped AlAs barrier 113, 50A non-doped InGaAs emitter isolation layer 114 and 500A heavily doped InGaAs emitter contact layer 115 . The structure of the grown material is shown in Figure 1;

Step 2: Use electron beam projection to lithography the pattern of the RTD emission area, with an area of 1×1um2, and use electron beam evaporation to evaporate Ni/Ge/Au/Ni/Au (50A/300A/800A/50A/1000A) metal , remove the glue and peel off to form the RTD emitter 120 . Electron beam projection lithography is conducive to the production of small sizes, and this step of lithography can also be realized by ordinary optical lithography or immersion exposure;

Step 3: Using ICP dry etching technology, using the RTD emitter 120 as a mask, etch the RTD structure to the heavily doped InGaAs collector contact layer 107, this step is non-selective etching, the reaction gas is Cl2, radio frequency The power is 15W with a DC bias of 30V. ICP etching can generate high plasma density under low DC bias voltage. Compared with wet etching, it has the advantages of good directionality and good etching surface consistency. It is widely used in compound semiconductor and deep silicon etching processes;

Step 4: using a highly selective citric acid etching solution to remove the remaining InGaAs layer to expose the InP selective etching stop layer 106 . The ratio of the citric acid corrosion solution is C6H807:H202=2:1, and the pH value is 5.5. In addition, organic acids represented by succinic acid can also be used for selective corrosion in this step;

Step 5: remove the InP selective corrosion stop layer 106 by bleaching in 1:10 dilute hydrochloric acid for 5 seconds, as shown in FIG. 2 ;

Step 6: Photoetch the parts to be isolated, and etch the semi-insulating InP substrate 100 by ICP dry method. This step is non-selective etching, the reaction gas is Cl2, the radio frequency power is 15W, and the DC bias voltage is 30V. After removing the glue, it is shown in Figure 3;

Step 7: Photoetching the source and drain electrodes of the HEMT, evaporating Ni/Ge/Au/Ni/Au (50A/300A/800A/50A/1000A) metal to form the HEMT drain electrode 121 and source electrode 122, as shown in FIG. 4 ;

Step 8: Under the mixed atmosphere of N2:H2=2:1, anneal at 500 degrees Celsius for 10 seconds. Excessive annealing causes impurity ions to enter the non-doped well region, resulting in a decrease in the RTD peak-to-valley current ratio, while insufficient annealing is not easy to form a good ohmic contact, resulting in a decrease in the DC characteristics of the device;

Under the mixed atmosphere of N2:H2=2:1, anneal at 360 degrees Celsius for 1 minute. Excessive annealing causes impurity ions to enter the non-doped well region, resulting in a decrease in the RTD peak-to-valley current ratio, while insufficient annealing is not easy to form a good ohmic contact, resulting in a decrease in the DC characteristics of the device;

Under the mixed atmosphere of N2:H2=2:1, anneal at 200 degrees Celsius for 30 minutes. Excessive annealing causes impurity ions to enter the non-doped well region, resulting in a decrease in the RTD peak-to-valley current ratio, while insufficient annealing is not easy to form a good ohmic contact, resulting in a decrease in the DC characteristics of the device;

Step 9: Photoetching the gate groove pattern of the HEMT, using selective ICP dry etching technology to etch the heavily doped cap layer 105, and the etching stops on the InAlAs barrier 104. This step of etching is selective etching, the reaction gas is a mixture of SF6 and BCl3 at a ratio of 1:3, the RF power is 15W, and the DC bias voltage is 30V. After deglue is shown in Figure 5. Dry etching can achieve selective etching of different materials through the selection of reactive gases, and ICP has the characteristics of low damage. Using ICP technology for selective etching not only maintains high selectivity for different material structures, but also It has been improved in terms of directionality and surface consistency, and is suitable for the needs of future small-scale large-scale integrated circuits;

Step 10: A layer of SiO ₂ passivation dielectric layer 130 is grown by PECVD with a thickness of 3000 Å, as shown in FIG. 6 . The growth temperature is 300 degrees Celsius, the power is 15W, and the thick silicon oxide is beneficial to reduce the junction capacitance;

Step 11: Photoetching the gate electrode pattern of HEMT, using B OE silicon oxide etching solution to remove the _SiO2 passivation dielectric layer 130 on the surface, and evaporating Ti/Pt/Au (500A/500A/2000A) metal by electron beam evaporation As the gate electrode 123 of the HEMT device, as shown in FIG. 7;

Step 12: photolithography lead hole pattern, use BOE silicon oxide etching solution to remove the SiO ₂ passivation medium layer 130 on the metal electrode, as shown in Figure 8 after deglue;

Step 13: Lithograph the thickened area of the lead interconnection, evaporate Ti/Al/Ti/Au (500A/8000A/1500A/2000A) electrodes by electron beam evaporation, remove the glue and peel off, and finally form as shown in Figure 9 Structure. Thicken the electrodes as much as possible if the process allows. Thick interconnect electrodes can reduce the series resistance, thereby improving the DC and high frequency performance of the circuit.

Claims (11)

1, a kind of employing dry etching technology is realized RTD and the single chip integrated method of HEMT, it is characterized in that, comprises the steps:

Step 1: on substrate, adopt the method for molecular beam epitaxy or Organometallic Chemistry gas phase electrode grow successively HEMT material structure and RTD material structure;

Step 2: make the figure of RTD emitter region by lithography, adopt the method for evaporation or sputter to prepare the AuGeNi metal level, remove photoresist and peel off, form the RTD metal emitting;

Step 3: adopt non-selection ICP dry etching technology, with the RTD metal emitting as sheltering the heavily doped InGaAs collecting region contact layer in the etching RTD material structure;

Step 4: adopt the wet etching liquid of high selectivity to remove remaining InGaAs layer, the selective corrosion in the middle of exposing stops layer;

Step 5: remove selective corrosion and stop layer;

Step 6: photoetching, be formed with the source region, adopt the ICP dry etching technology to be etched with extremely semi-insulating InP substrate of part in the source region outside, remove photoresist;

Step 7: make source, the drain electrode of HEMT by lithography, evaporation or sputter AuGeNi metal prepare HEMT source electrode, drain electrode;

Step 8: under protective gas atmosphere, carry out quick high-temp annealing;

Step 9: make HEMT grid groove figure by lithography, adopt selectivity ICP dry etching technology to etch away part heavy doping cap layer, etching stopping is removed photoresist on the InAlAs potential barrier;

Step 10: at device surface deposit growth one deck passivation dielectric layer;

Step 11: make the gate electrode figure of HEMT by lithography, the passivation dielectric layer of cutouts adopts the method for evaporation or sputter to generate the gate electrode of TiPtAu metal as the HEMT device;

Step 12: make fairlead by lithography, cut out the passivation dielectric layer above the metal electrode, remove photoresist;

Step 13: make the pin interconnection zone by lithography, evaporation or the thick TiAlTiAu metal electrode of sputter remove photoresist and peel off again.

2, employing dry etching technology according to claim 1 is realized RTD and the single chip integrated method of HEMT, it is characterized in that, wherein substrate is a semi-insulating InPIII-V family substrate.

3, employing dry etching technology according to claim 1 is realized RTD and the single chip integrated method of HEMT, it is characterized in that wherein the HEMT material structure comprises that InAlAs resilient coating, InGaAs raceway groove, InAlAs separator, delta doped layer, InAlAs potential barrier, heavy doping InGaAs cap layer and the InP selective corrosion of growth stop layer successively.

4, employing dry etching technology according to claim 1 is realized RTD and the single chip integrated method of HEMT, it is characterized in that wherein the RTD material structure comprises heavily doped InGaAs collecting region contact layer, InGaAs collecting region separator, AlAs potential barrier, InGaAs/InAs/InGaAs trap, AlAs potential barrier, InGaAs emitter region separator and the heavily doped InGaAs emitter region contact layer of growth successively.

5, employing dry etching technology according to claim 1 is realized RTD and the single chip integrated method of HEMT, it is characterized in that, wherein lithography step adopts conventional optical means or adopts the method for electron beam projection lithography or immersion lithography technology to realize.

6, employing dry etching technology according to claim 1 is realized RTD and the single chip integrated method of HEMT, it is characterized in that wherein last pin interconnection adopts that metal interconnected or employing air bridge technology interconnects on the conventional dielectric layer.

7, employing dry etching technology according to claim 1 is realized RTD and the single chip integrated method of HEMT, it is characterized in that wherein substrate both can be InP, also can be GaAs, the GaN compound semiconductor.

8, realize RTD and the single chip integrated method of HEMT according to claim 1 or 3 or 4 described employing dry etching technologies, it is characterized in that, the wherein growth of HEMT material structure and RTD material structure is used the method for MBE or is used the MOCVD method, or the growth of the method for the two combination.

9, employing dry etching technology according to claim 1 is realized RTD and the single chip integrated method of HEMT, it is characterized in that wherein the wet etching liquid of high selectivity is inorganic acid solution or organic acid soln.

10, employing dry etching technology according to claim 1 is realized RTD and the single chip integrated method of HEMT, it is characterized in that wherein said annealing time is 10 seconds to 30 minutes, and annealing temperature is 200-500 degree centigrade.

11, employing dry etching technology according to claim 1 is realized RTD and the single chip integrated method of HEMT, it is characterized in that wherein passivation dielectric layer is silica or silicon nitride or silicon oxynitride insulating medium layer.

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