CN106024712B - A kind of production method of autoregistration GaAs PMOS device - Google Patents

Abstract

The invention provides a method for manufacturing a self-aligned gallium arsenide PMOS device. The steps of the method are as follows: (1) growing a _SiO2 medium of 300 nanometers on the gallium arsenide channel layer; (2) etching the _SiO2 medium (3) growing alumina dielectric on the surface of gallium arsenide; (4) forming titanium gate metal on the sidewall of SiO ₂ ; (5) forming tungsten gate metal; (6) removing the gate metal covering area Aluminum oxide dielectric and SiO ₂ dielectric; (9) self-aligned ion implantation to form source and drain regions; (10) depositing source and drain metal electrodes in the source and drain regions.

Description

A method of fabricating a self-aligned gallium arsenide PMOS device

technical field

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for manufacturing a self-aligned gallium arsenide PMOS device, which is applied to the high-performance III-V semiconductor CMOS technology.

Background technique

Compared with silicon materials, Ⅲ-Ⅴ compound semiconductor materials have the advantages of high carrier mobility, large forbidden band width, etc., and have good characteristics in thermal, optical and electromagnetic aspects. The lack of PMOS devices matching NMOS devices has been one of the major obstacles to the application of III-V semiconductors in large-scale CMOS integrated circuits. The latest research reports show that the large source-drain parasitic resistance is an important factor affecting the performance improvement of III-V PMOS devices. Therefore, there is a need for a new approach to realize self-aligned PMOS devices on the structure of III-V semiconductor devices, reduce the source-drain parasitic resistance of PMOS devices, and improve device performance to meet the requirements of high-performance III-V semiconductor CMOS technology. Require.

Contents of the invention

(1) Technical problems to be solved

The main purpose of the present invention is to provide a method for making a self-aligned gallium arsenide PMOS device, so as to realize a self-aligned PMOS device with gallium arsenide as the channel material and double-gate metal electrodes, and achieve a channel with high electron mobility. The III-V semiconductor NMOS device of the channel material is matched to meet the requirements of the high-performance III-V semiconductor CMOS technology.

(2) Technical solution

To achieve the above object, the present invention provides a method for manufacturing a self-aligned gallium arsenide PMOS device. Its preparation method steps are as follows:

(1) On an N-type doped gallium arsenide channel layer, grow SiO ₂ medium 300 nanometers;

(2) using the method of ICP etching to form 85 degree steps on the SiO ₂ dielectric layer;

(3) Carry out surface cleaning and passivation to the sample, and grow alumina medium 3 nanometers on the surface;

(4) adopt the method for sputtering to deposit titanium metal 60 nanometers on the sample sheet;

(5) Etch the titanium metal by ICP etching, and form a gate metal electrode with a thickness of 30 nanometers on the side wall of the step;

(6) adopt the method for sputtering to deposit 60 nanometers of tungsten metal on the sample sheet;

(7) Etching tungsten metal by ICP etching method, forming a gate metal electrode with a thickness of 30 nanometers on the side wall of the step;

(8) Adopt photoresist mask and plasma etching to etch and remove the aluminum oxide medium and _SiO2 medium other than the gate metal;

(9) Self-aligned ion implantation is performed on the sample, the implanted ions are Mg, and the implantation is activated to form a source-drain region;

(10) Depositing Pt/Ti/Au source and drain metal electrodes in the source and drain regions.

In the above solution, the N-type doped GaAs channel layer is doped with silicon as the impurity, and the doping concentration is 3×10 ¹⁷ cm ^-3 ;

In the above scheme, the etching of the _SiO2 dielectric layer adopts an ICP etching system to etch;

In the above scheme, before growing the alumina gate dielectric, the surface of the GaAs channel is cleaned and passivated to achieve a good MOS interface without Fermi level pinning;

In the above solution, the gate metal Ti is formed by sputtering to ensure good sidewall coverage and sidewall Ti metal thickness;

In the above solution, the gate metal W is formed by sputtering to ensure its coverage on the side wall and the metal thickness of the side wall W;

In the above scheme, the removal of the aluminum oxide and _SiO2 all adopts the method of fluorine-based plasma etching, wherein the removal of _SiO2 adopts low-damage etching;

In the above scheme, the distribution of the gate metal electrodes is such that the titanium metal electrode is close to the source end, and the tungsten metal electrode is close to the drain end.

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

A method for manufacturing a GaAs channel PMOS device provided by the present invention uses the GaP interface control layer technology to passivate the dangling bonds at the interface to achieve a low interface state density and reduce the scattering of carriers in the channel. At the same time, the GaP interface layer is also It is a potential barrier layer, which increases the concentration of two-dimensional electron gas in the channel layer, and realizes the dual functions of high mobility and high electron concentration; the use of beryllium ion implantation technology makes the overall process temperature of the device lower than 500 ° C, and the process compatibility is good; Since the electron mobility and hole mobility of gallium arsenide materials are relatively balanced, this GaAs channel PMOS device was invented to meet the requirements of high-performance III-V semiconductor CMOS technology.

Description of drawings

Fig. 1 is a GaAs channel PMOS process flow chart provided by the present invention;

Fig. 2-11 is the embodiment drawing of the GaAs channel PMOS device that the present invention improves;

Among them, 101 is the gallium arsenide channel layer, 102 is the SiO2 mask layer, 103 is the aluminum oxide dielectric layer, 104 is the titanium gate metal layer, 105 is the tungsten gate metal layer, 106 is the source-drain ion implantation area, and 107 is the source-drain metal electrodes.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

As shown in FIG. 2-11, FIG. 2-11 is a method for manufacturing a gallium arsenide PMOS device provided by this embodiment. Its production steps are as follows:

(1) As shown in Figure 2, form SiO ₂ medium with a thickness of 300 nanometers on the N-type doped gallium arsenide channel (101), and the growth method is PECVD;

(2) As shown in Figure 3, a step of 85 degrees is formed on the _SiO2 medium by ICP etching;

(3) As shown in Figure 4, 3 nanometers of aluminum oxide media are grown on the sample surface, and the growth method is atomic layer deposition;

(4) as shown in Figure 5, adopt the method for sputtering to deposit titanium metal 60 nanometers on the sample sheet on the sample surface;

(5) As shown in Figure 6, the titanium metal is etched by ICP etching, and a gate metal electrode with a thickness of 30 nanometers is formed on the side wall of the step;

(6) As shown in Figure 7, on the sample sheet, adopt the method for sputtering to deposit tungsten metal 60 nanometers;

(7) As shown in Figure 8, the tungsten metal is etched by ICP etching, and a gate metal electrode with a thickness of 30 nanometers is formed on the side wall of the step;

(8) As shown in Figure 9, the aluminum oxide medium and _SiO2 medium other than the gate metal are etched and removed by plasma etching;

(9) As shown in Figure 10, using the gate metal and photoresist as a mask, perform self-aligned ion implantation on the sample, the implanted ions are magnesium, and perform implant activation to form source and drain regions;

(10) As shown in FIG. 11 , deposit platinum/titanium/gold (5/10/200 nm) source and drain metal electrodes in the source and drain regions.

In the above embodiment, SiO2 is removed by ICP system etching, the etching gas is CHF3, the gas flow is 30 sccm, the radio frequency power is 15 watts, the ICP power is 150 watts, and the cavity pressure is 0.8 Pa.

In the above-mentioned embodiment, the removal of aluminum oxide adopts ICP system etching, the etching gas is CHF3, the gas flow rate is 30 sccm, the radio frequency power is 40 watts, the ICP power is 180 watts, and the cavity pressure is 0.8 Pa.

In the above embodiment, the etching of titanium metal and tungsten metal adopts the ICP system, the etching gas is SF6, the gas flow rate is 20 sccm, the radio frequency power is 20 watts, the ICP power is 120 watts, and the cavity pressure is 0.3 Pa.

In the above embodiment, the dose of magnesium ion implantation is 1×10 ¹³ , and the energy is 30KeV.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. a kind of production method of autoregistration GaAs PMOS device, production method step are successively：

(1) SiO is grown on N-type gallium arsenide channel layer₂300 nanometers of medium；

(2) SiO is etched₂Dielectric layer forms 85 degree of steps；

(3) alumina medium is grown in gallium arsenide surface, the alumina medium is as gate medium；

(4) 60 nanometers of titanium is deposited；

(5) it uses ICP to etch titanium, titanium grid metal is formed in mesa sidewall；

(6) 60 nanometers of depositing tungsten metal；

(7) it uses ICP to etch tungsten metal, tungsten grid metal is formed in mesa sidewall；

(8) remove the alumina medium and SiO other than grid metal overlay area₂Medium；

(9) autoregistration ion implanting forms source and drain areas；

(10) source and drain metal electrodes are deposited in source and drain areas.

2. a kind of production method of autoregistration GaAs PMOS device according to claim 1, it is characterised in that the oxygen The thickness for changing aluminium medium is 3 nanometers.

3. a kind of production method of autoregistration GaAs PMOS device according to claim 1, it is characterised in that the titanium The grid length of MOS device has been codetermined with the width and gate dielectric layer sidewall thickness of two grid metals of tungsten.

4. a kind of production method of autoregistration GaAs PMOS device according to claim 1, it is characterised in that the titanium All it is to be deposited using the method for magnetron sputtering, and molding is etched using the method for ICP etchings with tungsten grid metal.

5. a kind of production method of autoregistration GaAs PMOS device described in claim 1, it is characterised in that the titanium The source and drain spacing of GaAs PMOS device is determined with the width of tungsten metal.

6. a kind of production method of autoregistration GaAs PMOS device described in claim 1, it is characterised in that the titanium End is located at close to the source side of PMOS device.