CN102569399A - Source-drain self-aligned MOS device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a source-drain self-aligned MOS device and a manufacturing method thereof. The source-drain self-aligned MOS device comprises: a single crystal substrate layer; a III-V semiconductor layer formed on the single crystal substrate; An ohmic contact layer formed on the III-V semiconductor layer; a low-K dielectric layer formed on the ohmic contact layer; etching the ohmic contact layer and the low-K dielectric layer to form a gate groove, and the gate groove formed in the gate groove A spacer structure made of an insulating medium; a high-K gate dielectric layer formed on the epitaxial wafer forming the spacer structure; a gate metal electrode formed on the high-K gate dielectric layer in the gate groove region; and the gate metal electrode Etching the high-K gate dielectric layer and the low-K dielectric layer for masking to expose the ohmic contact layer, and forming source-drain metal electrodes on the exposed ohmic contact layer. The invention reduces the parasitic resistance of the source and drain, improves the consistency of the device, and improves the radio frequency performance of the device.

Description

Source-drain self-aligned MOS device and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a source-drain self-aligned MOS device and a manufacturing method thereof.

Background technique

Compared with silicon materials, III-V compound semiconductor materials have the advantages of high carrier mobility, large forbidden band width, etc., and have good characteristics in thermal, optical and electromagnetic aspects. After silicon-based CMOS technology is approaching its physical limit, III-V compound semiconductor materials may become candidate channel materials due to their high electron mobility characteristics for making CMOS devices. However, III-V semiconductor devices have many different physical and chemical properties from silicon devices, and the MOS structure and fabrication process suitable for silicon devices may not necessarily be applicable to III-V semiconductor devices. Therefore, it is necessary to adopt new device structures and new manufacturing processes on III-V semiconductors to give full play to the material properties of III-V semiconductor materials, improve the DC characteristics and radio frequency characteristics of MOS devices, and meet the requirements of high-performance III-V semiconductors. Group V semiconductor CMOS technology requirements.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to provide a source-drain self-aligned MOS device and its manufacturing method, to achieve low source-drain resistance, while controlling the distance between gate-source and gate-drain, improving III-V MOS The current drive capability of the device meets the application requirements of high-performance III-V CMOS technology in digital and radio frequency.

(2) Technical solutions

To achieve the above object, the present invention provides a source-drain self-aligned MOS device, comprising: a single crystal substrate layer 101; a III-V semiconductor layer 102 formed on the single crystal substrate 101; The ohmic contact layer 103 formed on the semiconductor layer 102; the low-K dielectric layer 104 formed on the ohmic contact layer 103; the ohmic contact layer 103 and the low-K dielectric layer 104 are etched to form a gate groove, and a gate groove is formed in the gate groove A spacer structure 105 made of an insulating medium; a high-K gate dielectric layer 106 formed on the epitaxial wafer forming the spacer structure 105; a gate metal electrode 107 formed on the high-K gate dielectric layer 106 in the gate groove region; And using the gate metal electrode 107 as a mask to etch the high-K gate dielectric layer 106 and the low-K dielectric layer 104 to expose the ohmic contact layer 103 , and form the source-drain metal electrode 108 on the exposed ohmic contact layer 103 .

In order to achieve the above object, the present invention also provides a method for making a source-drain self-aligned MOS device, comprising: step 1: selecting a single crystal substrate layer 101; step 2: forming III on the single crystal substrate 101 -V semiconductor layer 102; step 3: form ohmic contact layer 103 on III-V semiconductor layer 102; step 4: form low-K dielectric layer 104 on ohmic contact layer 103; step 5: etch ohmic contact layer 103 and low K dielectric layer 104, forming a gate groove; step 6: forming a sidewall structure 105 made of an insulating medium in the gate groove; step 7: forming a high-K gate dielectric layer 106 on the epitaxial wafer forming the sidewall structure 105; step 8: Form a gate metal electrode 107 on the high-K gate dielectric layer 106 in the gate groove area; step 9: use the gate metal electrode 107 as a mask to etch the high-K gate dielectric layer 106 and the low-K dielectric layer 104 to expose the ohmic contact layer 103 ; Step 10 : forming source-drain metal electrodes 108 on the exposed ohmic contact layer 103 .

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

The source-drain self-aligned MOS device and its manufacturing method provided by the present invention use multi-layer source-drain metal layers to directly form low-resistance ohmic contacts on the III-V semiconductor layer, reducing the parasitic resistance of the source-drain; through The sidewall process realizes the self-alignment of the gate-source and gate-drain structures, and improves the consistency of the device; by using low-K dielectric materials to separate the gate metal from the source-drain metal, the parasitic capacitance of the gate-source and gate-drain is further reduced, thereby improving the device RF performance.

Description of drawings

1 is a schematic diagram of a source-drain self-aligned MOS device according to an embodiment of the present invention;

2 is a flowchart of a method for fabricating a source-drain self-aligned MOS device according to an embodiment of the present invention;

FIG. 3-1 to FIG. 3-9 are process flow charts for fabricating a source-drain self-aligned MOS device according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The source-drain self-aligned MOS device provided by the present invention uses multi-layer source-drain metal layers to directly form low-resistance ohmic contacts on the III-V semiconductor layer, reducing the parasitic resistance of source-drain; realizing gate-source through sidewall technology Self-alignment with the gate-drain structure improves the consistency of the device; by using low-K dielectric materials to separate the gate metal from the source-drain metal, the parasitic capacitance of the gate-source and gate-drain is further reduced, thereby improving the RF performance of the device.

As shown in FIG. 1, FIG. 1 shows a schematic diagram of a source-drain self-aligned MOS device according to an embodiment of the present invention. The source-drain self-aligned MOS device includes: a single crystal substrate layer 101; The III-V semiconductor layer 102 formed on the bottom 101; the ohmic contact layer 103 formed on the III-V semiconductor layer 102; the low-K dielectric layer 104 formed on the ohmic contact layer 103; the etching of the ohmic contact layer 103 and the low-K The dielectric layer 104 forms a gate groove, and a spacer structure 105 made of an insulating dielectric is formed in the gate groove; a high-K gate dielectric layer 106 is formed on the epitaxial wafer forming the spacer structure 105; a high-K gate dielectric layer 106 is formed in the gate groove region. The gate metal electrode 107 formed on the dielectric layer 106; and using the gate metal electrode 107 as a mask to etch the high-K gate dielectric layer 106 and the low-K dielectric layer 104 to expose the ohmic contact layer 103, and to form on the exposed ohmic contact layer 103 source and drain metal electrodes 108 .

Wherein, the single crystal substrate 101 includes silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), aluminum nitride (AlN), silicon carbide (SiC) or alumina (Al2O3) substrates. The III-V semiconductor layer 102 adopts III-V group semiconductor thin-layer materials, and the III-V group semiconductor thin-layer materials include gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), Any compound in the group consisting of indium arsenide (InAs), gallium antimonide (GaSb), gallium nitride (GaN) and indium nitride (InN), and a multi-element alloy of multiple compounds in the group; The III-V semiconductor layer 102 includes one III-V semiconductor or multiple alloys of multiple III-V semiconductors, or a composite channel composed of multiple III-V semiconductors and alloy thin layers.

The ohmic contact layer 103 is made of directly deposited metal, epitaxially grown narrow-bandgap III-V semiconductor thin film material, or low-resistance nitride, and the metal or nitride can directly form an ohmic contact on the III-V semiconductor layer 102 , and the ohmic contact resistance is less than 5Ωmm, thereby reducing the source-drain parasitic resistance.

The low-K dielectric 104, which can be such as SiNx, SiO2 and other dielectric materials, has a dielectric constant K less than 4, and can be directly deposited on the ohmic contact layer by ALD or PECVD to separate the gate metal electrode 107 from the ohmic contact layer. 103.

Deposit a conformal insulating medium in the gate groove, that is, the insulating medium constituting the sidewall structure 105 mainly adopts PECVD to grow SiN _x , or ALD deposited low-K dielectric, and the thickness of the sidewall structure is between 10 nanometers and 500 nanometers. The method adopts the characteristics of large etching rate and aspect ratio during dry etching.

The main feature of the high-K gate dielectric layer 106 is that the dielectric constant K is greater than 20, which is much higher than SiO ₂ with a dielectric constant k=3.9, so as to ensure that the equivalent oxide layer thickness of the high-K gate dielectric layer 106 has the same Capable of scaling down, the material used for the high-K gate dielectric layer 106 includes oxide, nitride, oxynitride, any mixture thereof, or any combination of layers.

The distance between the gate metal electrode 107 and the source-drain metal electrode 108 is determined by the width of the spacer structure 105 and the thickness of the high-K gate dielectric layer 106, and the distance can vary from a few nanometers to hundreds of nanometers, and is not limited by the photolithography process. The shape of the gate metal electrode 107 is a T-shaped structure, and its material structure includes a work function metal layer and a low resistance gate metal.

Based on the schematic diagram of a source-drain self-aligned MOS device shown in FIG. 1, FIG. 2 shows a flow chart of a method for manufacturing a source-drain self-aligned MOS device according to an embodiment of the present invention. The method includes the following steps:

Step 1: Select a single crystal substrate layer 101;

Step 2: forming a III-V semiconductor layer 102 on the single crystal substrate 101;

Step 3: forming an ohmic contact layer 103 on the III-V semiconductor layer 102;

Step 4: forming a low-K dielectric layer 104 on the ohmic contact layer 103;

Step 5: Etching the ohmic contact layer 103 and the low-K dielectric layer 104 to form gate grooves;

Step 6: forming a side wall structure 105 made of an insulating medium in the gate groove;

Step 7: forming a high-K gate dielectric layer 106 on the epitaxial wafer forming the spacer structure 105;

Step 8: forming a gate metal electrode 107 on the high-K gate dielectric layer 106 in the gate groove region;

Step 9: using the gate metal electrode 107 as a mask to etch the high-K gate dielectric layer 106 and the low-K dielectric layer 104 to expose the ohmic contact layer 103;

Step 10: forming source-drain metal electrodes 108 on the exposed ohmic contact layer 103 .

Wherein, the formation of the III-V semiconductor layer 102 on the single crystal substrate 101 mentioned in step 2 is realized by epitaxial methods such as MOCVD or MBE. The formation of the ohmic contact layer 103 on the III-V semiconductor layer 102 in step 3 is achieved by direct metal deposition, epitaxial growth of narrow-bandgap III-V semiconductor thin film materials or low-resistance nitrides. The formation of the low-K dielectric layer 104 on the ohmic contact layer 103 in step 4 is realized by using a low-temperature deposition method such as PECVD or ALD. The etching of the ohmic contact layer 103 and the low-K dielectric layer 104 in step 5 to form gate grooves is realized by dry etching. In step 6, in the step of forming the spacer structure 105 made of insulating medium in the gate trench, the insulating medium constituting the spacer structure 105 is formed by growing SiN _x in the gate trench by PECVD, or by using ALD to form the spacer structure 105 in the gate trench. It is formed by depositing a low-K dielectric in the trench. The formation of the high-K gate dielectric layer 106 on the epitaxial wafer on which the spacer structure 105 is formed in step 7 is realized by using ALD deposition technology, sputtering or other methods. The formation of the gate metal electrode 107 on the high-K gate dielectric layer 106 in the gate groove region in step 8 is realized by electron beam evaporation, sputtering, ALD, or a combination of these three methods. Etching the high-K gate dielectric layer 106 and the low-K dielectric layer 104 using the gate metal electrode 107 as a mask in step 9 is to use ICP or RIE dry etching, wet etching, and dry etching and wet etching. It is realized by the combination of method and corrosion. The formation of the source-drain metal electrodes 108 on the exposed ohmic contact layer 103 in step 10 is realized by electron beam evaporation and sputtering, or a combination of the two methods.

Based on the source-drain self-aligned MOS device and its manufacturing method shown in FIG. 1 and FIG. 2, FIG. 3-1 to FIG. 3-9 show the process of manufacturing a source-drain self-aligned MOS device according to an embodiment of the present invention Process flow chart, specifically including:

As shown in FIG. 3-1, a single crystal silicon substrate 101 is selected, and an InAlAs/InGaAs semiconductor layer 102 is grown heteroepitaxially on the single crystal substrate 101;

As shown in FIG. 3-2, a source-drain metal Mo layer 103 is formed on the InAlAs/InGaAs semiconductor layer 102;

As shown in FIG. 3-3, a low-K dielectric SiO ₂ thin film 104 is deposited on the source-drain metal Mo layer 103;

As shown in Figure 3-4, use photolithography to define the gate groove, etch the low-K dielectric SiO ₂ thin film 104 and the source-drain metal Mo layer 103, to expose the InAlAs/InGaAs semiconductor layer 102, and form the gate groove;

As shown in Figure 3-5, PECVD _SiNx dielectric is deposited in the gate trench, and anisotropic dry etching is used to form _SiNx dielectric sidewalls 105;

As shown in Fig. 3-6, the high-K gate dielectric LaAlO ₃ 106 is deposited on the epitaxial wafer forming the SiN _X dielectric spacer 105 by ALD technology;

As shown in Figure 3-7, the gate metal layer TiAl107 is deposited on the high-K gate dielectric LaAlO ₃ 106 in the gate trench area by PVD method;

As shown in Figure 3-8, the high-K gate dielectric LaAlO ₃ 106 and the low-K dielectric SiO ₂ thin film 104 are etched with the gate metal layer TiAl107 as a mask by dry etching to expose the source-drain metal Mo layer 103;

As shown in FIGS. 3-9 , a source-drain metal electrode 108 is fabricated on the exposed source-drain metal Mo layer 103 .

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (20)

1. a provenance is leaked self aligned MOS device, it is characterized in that, comprising:

Single crystalline substrate layer (101);

Go up the III-V semiconductor layer (102) that forms in this single crystalline substrate (101);

Go up the ohmic contact layer (103) that forms at this III-V semiconductor layer (102);

Go up the low-K dielectric layer (104) that forms at this ohmic contact layer (103);

This ohmic contact layer of etching (103) forms the grid groove with this low-K dielectric layer (104), the sidewall structure (105) by the dielectric making that in this grid groove, forms;

The high-K gate dielectric layer (106) that on the epitaxial wafer that forms sidewall structure (105), forms;

The grid metal electrode (107) that on this high-K gate dielectric layer (106) in grid groove zone, forms; And

With this grid metal electrode (107) is that this high-K gate dielectric layer of mask etching (106) and this low-K dielectric layer (104) expose ohmic contact layer (103), goes up the source that forms at this ohmic contact layer (103) that exposes and leaks metal electrode (108).

2. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, said single crystalline substrate (101) is for adopting silicon Si, germanium Ge, GaAs GaAs, indium phosphide InP, gallium nitride GaN, aluminium nitride AlN, carborundum SiC or aluminium oxide Al ₂O ₃The substrate of material.

3. self aligned MOS device is leaked in source according to claim 1; It is characterized in that; Said III-V semiconductor layer (102) adopts III-V family semiconductor film layer material; This III-V family semiconductor film layer material comprises any compound in the group that is made up of GaAs GaAs, indium phosphide InP, indium antimonide InSb, indium arsenide InAs, gallium antimonide GaSb, gallium nitride GaN and indium nitride InN, and the multicomponent alloy of a plurality of compounds in this group.

4. self aligned MOS device is leaked in source according to claim 3; It is characterized in that; Said III-V semiconductor layer (102) comprises a kind of III-V family's semiconductor or the semi-conductive multicomponent alloy of multiple III-V family, perhaps comprises the compound raceway groove that is combined by multiple III-V family's semiconductor and alloy thin layer.

5. self aligned MOS device is leaked in source according to claim 1; It is characterized in that; Said ohmic contact layer (103) adopts the directly metal of deposition; Or adopt epitaxially grown low energy gap III-V semiconductor film material, or adopt epitaxially grown low-resistance nitride, the ohmic contact resistance of this low-resistance nitride is less than 5 Ω mm.

6. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, said low-K dielectric (104) is SiO ₂Perhaps SiN _x, be the insulating barrier that directly is deposited on the ohmic contact layer (103), with separate gate metal electrode (107) and ohmic contact layer (103).

7. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, the dielectric of said formation sidewall structure (105) is the SiN that adopts the PECVD growth _x, between 500 nanometers, said etching ohmic contact layer (103) forms the grid groove with low-K dielectric layer (104) and adopts dry etching in 10 nanometers for the low-K dielectric that perhaps adopts ALD to deposit, the thickness of said sidewall structure (105).

8. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, the dielectric constant k of said high-K gate dielectric layer (106) is higher than the SiO of dielectric constant k=3.9 greater than 20 ₂The ability that has scaled down with the equivalent oxide thickness that guarantees this high-K gate dielectric layer 106; The material that this high-K gate dielectric layer (106) adopts comprises oxide, nitride or nitrogen oxide; And any mixing of oxide, nitride or nitrogen oxide, perhaps the multilayer combination in any of oxide, nitride or nitrogen oxide.

9. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, the T type that the is shaped as structure of said grid metal electrode (107), and its material is workfunction layers or low resistance grid metal.

10. self aligned MOS device is leaked in source according to claim 1, it is characterized in that, said grid metal electrode (107) leaks the thickness decision of the spacing of metal electrode (108) by the width and the high-K gate dielectric layer (106) of sidewall structure (105) with the source.

11. the method for self aligned MOS device is leaked in the source of making, and leaks self aligned MOS device with each described source in the making claim 1 to 10, comprising:

Step 1: select a single crystalline substrate layer (101);

Step 2: go up formation III-V semiconductor layer (102) in this single crystalline substrate (101);

Step 3: go up formation ohmic contact layer (103) at III-V semiconductor layer (102);

Step 4: go up formation low-K dielectric layer (104) at ohmic contact layer (103);

Step 5: etching ohmic contact layer (103) and low-K dielectric layer (104) form the grid groove;

Step 6: in the grid groove, form the sidewall structure of making by dielectric (105);

Step 7: on the epitaxial wafer that forms sidewall structure (105), form high-K gate dielectric layer (106);

Step 8: on the high-K gate dielectric layer (106) in grid groove zone, form grid metal electrodes (107);

Step 9: with grid metal electrode (107) is this high-K gate dielectric layer of mask etching (106) and low-K dielectric layer (104), exposes ohmic contact layer (103);

Step 10: go up the formation source at the ohmic contact layer that exposes (103) and leak metal electrode (108).

12. the method that self aligned MOS device is leaked in making according to claim 11 source is characterized in that, said going up in this single crystalline substrate (101) forms III-V semiconductor layer (102), is to adopt MBE or MOCVD method to realize.

13. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; Said going up at III-V semiconductor layer (102) forms ohmic contact layer (103), is to adopt the method for direct plated metal, epitaxial growth low energy gap III-V semiconductor film material or low resistance nitride to realize.

14. the method that self aligned MOS device is leaked in making according to claim 11 source is characterized in that, said going up at ohmic contact layer (103) forms low-K dielectric layer (104), is to adopt PECVD or ALD method to realize.

15. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; Said etching ohmic contact layer (103) and low-K dielectric layer (104) form the grid groove, be to adopt dry etching, wet etching, or the method realization that combines with wet etching of dry etching.

16. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; In the said step that in the grid groove, forms the sidewall structure of being made by dielectric (105), the dielectric that constitutes sidewall structure (105) is to adopt the PECVD SiN that in the grid groove, grows _xForm, or adopt ALD in the grid groove, deposit low-K dielectric formation.

17. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; Saidly on the epitaxial wafer that forms sidewall structure (105), form high-K gate dielectric layer (106); Be to adopt the ALD depositing system, perhaps sputtering method, perhaps the method that combines of these two kinds of methods realizes.

18. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; The said grid metal electrodes (107) that on the high-K gate dielectric layer (106) in grid groove zone, form; Be to adopt electron beam evaporation, sputter, ALD deposition process to form separately, or above three kinds of methods methods of combining realize.

19. the method that self aligned MOS device is leaked in making according to claim 11 source; It is characterized in that; Said is this high-K gate dielectric layer of mask etching (106) and low-K dielectric layer (104) with grid metal electrode (107); Be the method that adopts dry etching ICP, RIE, or wet etching method, or the two method that the combines realization of dry etching and wet etching.

20. the method that self aligned MOS device is leaked in making according to claim 11 source is characterized in that, and is said at the last formation source leakage of the ohmic contact layer that exposes (103) metal electrode (108), is to adopt the method for electron beam evaporation or sputter to realize.

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