CN101180717A - 焊料补片形成方法及半导体元件的安装方法 - Google Patents
焊料补片形成方法及半导体元件的安装方法 Download PDFInfo
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- CN101180717A CN101180717A CNA2006800180099A CN200680018009A CN101180717A CN 101180717 A CN101180717 A CN 101180717A CN A2006800180099 A CNA2006800180099 A CN A2006800180099A CN 200680018009 A CN200680018009 A CN 200680018009A CN 101180717 A CN101180717 A CN 101180717A
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- solder
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Abstract
本发明提供一种可进行高密度安装的焊料补片形成方法,同时提供一种可靠性高的半导体元件的安装方法。准备在表面形成有多个突起部(12)或凹部(32)的平板(10、30),将平板与电子部件(14、34)对置配置,并向平板和电子部件的间隙供给含有焊料粉末(22、23)的树脂组成物(18、19),将树脂组成物加热,使树脂组成物中所含的焊料粉末熔融,使熔融后的焊料粉末自聚集到端子部(16、36)上,成长到平板的表面,由此在端子部上形成焊料补片(24、38),在将补片冷却硬化后,将平板去除,由此形成具有与突起部(12)对应的洼部(24a)、或与凹部(32)对应的突状部(38a)的焊料补片(24、38)。
Description
技术领域
本发明涉及一种用于在配线基板上安装半导体元件的焊料补片形成方法、及在配线基板上安装具有通过该形成方法制作而成的焊料补片的半导体元件的半导体元件的安装方法。
背景技术
近年来,随着电子设备的小型化、高功能化,信号处理的数字化、高频化正在发展之中。在这些电子设备中,对于核心部件即半导体元件而言,随着电路规模的增大,要求连接端子的多针脚化、窄节距化。进而在半导体元件和配线基板间的配线延迟的降低及噪声的防止也成为重要的课题。因此,对于半导体元件和配线基板的连接方式而言,代替以现有的引线接合为主体的安装方式而采用倒装片安装方式。
而且,在该倒装片安装方式中,在半导体元件的电极端子上形成作为突起电极的焊料补片,并经由该焊料补片与配线基板上形成的连接端子一并接合的焊料补片连接法被广泛使用。但是,在现有的焊料补片形成方法中,由于需要将焊料暂时熔融,故只能得到半球状补片。因此,难以应对窄节距化、多针脚化。
另一方面,也采用在半导体元件的电极端子上形成由金(Au)等金属构成的补片,并利用导电性粘接剂及各向异性导电性粘接剂将该补片和配线基板的连接端子连接的方法。但是,在这些方法中,与现有的采用焊料补片的连接相同,不能充分应对窄节距化、多针脚化。
另外,近年来的电子电路是以半导体元件为主体构成的。因此,将这些半导体元件高密度且廉价地安装在配线基板上是在实现电子设备的低成本化及小型化、高功能化方面所要求的。
对于这样的要求,专利文献1中记载有将形成于电极端子上的补片形状作成底面的一边例如为10~60μm且其前端尖的四棱锥状的技术。通过将补片的前端作成尖的形状,不会发生配线基板和半导体元件连接时的导通不良,从而可实现高密度安装。
另外,专利文献2中记载有如下技术,即,将配线基板的连接端子形成为突起状,另一方面,在半导体元件的电极端子上形成配线基板侧的突起部可嵌合的凹部,并在该半导体元件侧的凹部嵌合了配线基板侧的突起部的状态下,在配线基板上安装半导体元件。需要说明的是,端子间的接合通过使设于凹部的低融点金属回流而进行。由此,可进行能够应对电极端子间的窄小化且连接强度高的高密度安装。
另外,作为类似的技术,专利文献3中记载有如下技术,即,在配线基板的连接端子上设置与半导体元件的突起电极形状吻合的形状的凹部,并通过将半导体元件的突起电极嵌合到配线基板的凹部而在配线基板上安装半导体元件。由此,可进行配线基板和半导体元件的接合强度强且可靠性优良的高密度安装。
而且,在专利文献4中记载有如下技术,即,在配线基板上形成在配线基板的连接端子处设置了开口的绝缘树脂层,通过将半导体元件侧的突起电极嵌合到配线基板侧的开口部而在配线基板上安装半导体元件。需要说明的是,端子间的接合是通过使装填到开口部的焊料回流而进行的。由此,可进行无连接不良且可靠性优良的高密度安装。
专利文献1:日本特开2002-93842号公报;
专利文献2:日本特开平5-13496号公报;
专利文献3:日本特开平11-17050号公报;
专利文献4:日本特开2000-100868号公报。
发明内容
专利文献1中记载的技术中,补片形状的加工是通过在形成于基板上的孔内形成锡膜,由此形成前端尖的锡膜,并将该锡膜转印到半导体元件的连接端子上与之接合而进行的,因此,制造工序复杂,难以降低补片形成成本。
另外,专利文献2~4中记载的技术中,在配线基板或半导体元件的其中的一个端子上形成凹部,并在该凹部内嵌合在配线基板或半导体元件的另一个端子上形成的突起部,从而在配线基板上安装半导体元件这一方面是共通的,但该凹部的形成工序都复杂,因此难以降低补片形成成本。
即,在专利文献2中,形成于半导体元件的连接端子上的凹部是通过在连接端子上将金突起部环状镀敷而形成的。该情况下,也难以与配线基板的突起电极一致地形成凹部形状。
另外,在专利文献3中,形成于配线基板的电极端子上的凹部是如下形成的,即,通过在利用丝网印刷而供给到配线基板上的导电膏上按压半导体元件的突起电极来形成凹部,之后将导电膏烧结。该情况下,需要将导电膏的厚度形成为与突起电极的高度相同,从而也难以进行导电膏(电极端子)的加工。
另外,在专利文献4中,形成于配线基板的电极端子上的凹部是通过在电极端子上将配线基板上形成的绝缘树脂层开口而形成的。该情况下,需要将绝缘树脂层的厚度形成为与半导体元件的突起电极的高度相同,从而难以进行绝缘树脂层的加工,同时也难以使凹部的形状形成地与半导体元件的突起电极一致。
本发明是鉴于这样的问题点而构成的,其主要目的在于,提供一种可进行高密度安装的焊料补片形成方法,同时提供一种可靠性高的半导体元件的安装方法。
本发明的焊料补片形成方法是在具有多个端子部的电子部件的该端子部上形成焊料补片的方法,其特征在于,包括:准备在表面形成有多个突起部或凹部的平板的工序;将平板与电子部件相对配置,并向平板和电子部件的间隙供给含有焊料粉末及对流添加剂的树脂组成物的工序;加热树脂组成物,使树脂组成物中含有的焊料粉末熔融,通过使熔融的焊料粉末自聚集到端子部上而使之成长到平板的表面,由此在端子部上形成焊料补片的工序;以及在冷却焊料补片并使其硬化后,去除平板的工序,其中,焊料补片具有与突起部对应的洼部或与凹部对应的突状部。
根据该方法,通过使树脂组成物中所含的熔融后的焊料粉末自聚集到电子部件的端子上,可容易地形成具有突状部或洼部的焊料补片。另外,可利用平板来限制形成的焊料补片的高度,从而可形成均匀高度的焊料补片。由此,通过在半导体元件或/及配线基板的端子上形成采用本方法的焊料补片,可进行可靠性高的半导体元件的高密度安装。
在某优选实施方式中,供给所述树脂组成物的工序由向电子部件上供给树脂组成物的工序、和与电子部件对置地使平板抵接所述树脂组成物的表面的工序构成。
在使所述平板与树脂组成物抵接的工序中,优选使突起部与端子部接触,使平板与树脂组成物的表面抵接。这样,在从焊料粉末的自聚集到焊料补片硬化为止,可利用突起部将端子部和平板的间隔保持一定,从而可形成具有更均匀的高度的焊料补片。
在某优选实施方式中,所述基板是配线基板或半导体元件。
优选在所述突起部或凹部的表面形成有相对于焊料具有润湿性的金属膜。据此,在熔融后的焊料粉末自聚集到端子上时,与突起部或凹部接触的焊料粉末固定在润湿性良好的金属膜上成长,因此,可形成均匀形状的焊料补片。
另外,优选在所述突起部或凹部的表面形成有相对于突起部或凹部具有起模性的起模层。由此,在形成于端子上的焊料补片硬化后,可容易地去除平板。
另外,优选还含有在去除所述平板的工序之后,将树脂组成物去除的工序。
在某优选实施方式中,形成所述焊料补片的工序包括:将树脂组成物加热,使树脂组成物自聚集到端子部上,然后,进一步加热树脂组成物,使树脂组成物中所含的焊料粉末熔融,通过使熔融后的焊料粉末自聚集到端子部上,成长到平板的表面,由此,在端子部上形成焊料补片的工序。
本发明提的半导体元件的安装方法在配线基板上安装半导体元件,其特征在于,包括:在半导体元件或配线基板的一个的端子部上形成具有洼部的焊料补片的工序;在半导体元件或配线基板的另一个的端子部上形成具有突状部的焊料补片的工序;将半导体元件的端子部上形成的焊料补片和配线基板的端子部上形成的焊料补片彼此嵌合并接合的工序,具有洼部的焊料补片及具有突状部的焊料补片的至少其中之一是通过本发明的焊料补片形成方法形成的。
通过利用该方法使具有突状部及洼部的焊料补片彼此嵌合并接合,可简单且可靠地将半导体元件安装于配线基板上。另外,由于焊料补片不是熔融地进行接合,而是嵌合式接合,故可在低温下进行半导体安装。
在某优选实施方式中,将所述焊料补片彼此嵌合并接合的工序含有使彼此嵌合的焊料补片的至少一方熔融的加热工序。据此,可使焊料补片的接合更强固,从而可进行可靠性高的半导体安装。需要说明的是,在该情况下,优选半导体元件的焊料补片和配线基板的焊料补片由不同的焊料材料构成。
发明效果
根据本发明,通过使树脂组成物中所含的焊料粉末熔融,并使熔融后的焊料粉末自聚集到基板的端子上,可容易地形成具有突状部或洼部的焊料补片。另外,由于可利用平板限制形成的焊料补片的高度,故可形成均匀高度的焊料补片。由此,通过在半导体元件或/及配线基板的端子上形成本发明的焊料补片,可进行可靠性高的半导体元件的高密度的安装。
另外,通过将具有通过本发明形成的突状部或/及洼部的焊料补片彼此嵌合接合,可容易且可靠地将半导体元件安装在配线基板上,因此,可进行可靠性高的半导体安装。
附图说明
图1(a)~(e)是示意性示出本发明第一实施方式的焊料补片形成方法的工序剖面图;
图2(a)~(e)是示意性示出本发明第二实施方式的焊料补片形成方法的工序剖面图;
图3(a)~(e)是示意性示出本发明第三实施方式的焊料补片形成方法的工序剖面图;
图4是同实施方式的半导体元件的安装方法的变形例的半导体元件安装构造体的剖面图;
图5是同实施方式的半导体元件的安装方法的其它变形例的半导体元件安装构造体的剖面图;
图6(a)~(e)是示意性示出本发明第四实施方式的焊料补片形成方法的工序剖面图;
图7是同实施方式的在表面形成有起模层及金属膜的突起部的局部放大剖面图;
图8是示出同实施方式的半导体元件的安装构造体的剖面图。
符号说明
10、30、50 平板
12、52 突起部
14、54 配线基板
16、36、56、68 端子部
18、19、58 树脂组成物
20、21、60 树脂
22、23、62 焊料粉末
24、38、64 焊料补片
24a、64a 洼部
30 平板
32 凹部
34、66 半导体元件
38a 突状部
40 焊料补片形成配线基板
42 焊料补片形成半导体元件
44 一体化补片
46 欠装树脂
70 补片
72 起模层
74 金属膜
具体实施方式
下面,参照附图对本发明的实施方式进行说明。下图中,为简化说明,由同一参照符号表示实质上具有同一功能的结构要素。本发明不限于以下的实施方式。
(第一实施方式)
图1是示意性示出本发明第一实施方式的焊料补片形成方法的工序剖面图。需要说明的是,在本实施方式中,对使用配线基板作为电子部件的情况进行说明。
如图1(a)所示,在平板10的一侧面上,在与配线基板14的补片形成用的端子部16对应的位置形成突起部12。就这样的突起部12而言,例如使用光刻工艺在平板10上形成规定的图案后,以该图案为掩模,通过蚀刻或喷砂等去除平板10的不需要的部分,由此能够以规定的节距形成具有一定高度的突起部12。或者也可以通过印刷方式形成突起部12。需要说明的是,作为平板10,例如可使用玻璃板、陶瓷板、硅板或具有耐热性的塑料板等。
另外,配线基板14既可以为多层基板,也可以为两面配线基板。作为基材,只要是耐受补片的熔融温度的材料,就没有特别限制,可以是玻璃环氧基板、聚酰亚胺基板等树脂基板、陶瓷基板或玻璃基板、进而也可以是硅基板。
另外,在配线基板14的形成有端子部16的面上也可以形成未图示的导体配线。在导体配线上也形成后述的树脂组成物18的情况下,优选在导体配线的表面预先形成未涂敷补片的材料,例如抗镀敷剂等树脂膜或无机绝缘膜等。另外,为高精度地规定后述的补片成长的端子部16的区域,优选在端子部16的周围也形成抗镀敷剂等。
其次,如图1(b)所示,在配线基板14的形成有端子部16的区域涂敷规定量的树脂组成物18。具体而言,在平板10抵接树脂组成物18时,树脂组成物18扩散涂敷,将配线基板14的端子部16全部覆盖,且设定为填充到设于平板10和配线基板14之间的一定间隙的量。此时的树脂组成物18使用膏状且粘度较大的物质。该树脂组成物18是在树脂20中含有焊料粉末22的物质。另外,树脂组成物18不仅为膏状,而且在室温下也可以为片状。
需要说明的是,理想的是,在涂敷树脂组成物18之前,用例如丙酮及乙醇等有机溶剂或清洗液对配线基板14的表面、特别是端子部16的表面进行清洁化处理。
其次,如图1(c)所示,按照配线基板14的端子部16和平板10的突起部12对置的方式将配线基板14和平板10对位,使平板10抵接在树脂组成物18上。通过该抵接,树脂组成物18在配线基板14和平板10之间均匀地扩散,且保持规定厚度,形成大致密闭空间。即使这样抵接,平板10的突起部12也可以设定为不与配线基板14的端子部16接触。即,突起部12的高度形成为比平板10与树脂组成物18抵接时的树脂组成物18的厚度小。
此时,为将平板10和配线基板14保持一定的间隙,优选将配线基板14和平板10机械固定。而且,在该情况下,若保持平板10和配线基板14之间的平行度,则是更优选的。
需要说明的是,作为将树脂组成物18供给平板10和配线基板14的间隙的方法,也可以使用如下方法,即,在将平板10和配线基板14预先彼此对置配置后,使用例如喷嘴等在平板10和配线基板14之间的间隙注入树脂组成物18。
其次,如图1(d)所示,至少将树脂组成物18加热到焊料粉末22熔融的温度。需要说明的是,就树脂组成物18的加热而言,既可以从配线基板14侧用加热器加热,也可以从平板10侧用加热器加热。或者也可以是将整体置入加热炉中全面进行加热的方法。或者也可以照射微波,只是将树脂组成物18及其附近加热。
在该加热温度下,构成树脂组成物18的树脂20的粘度减小,流动性增加。熔融的焊料粉末22在树脂20中移动,自聚集到润湿性高的端子部16上。这样,通过使焊料在端子部16上逐渐成长,最终以包围突起部12的方式成长到平板10的表面,形成焊料补片24。
在此,树脂组成物18中也可以含有在该加热温度下沸腾或分解从而排出气体的添加剂。由于含有排出气体的树脂组成物18被填充到由平板10和配线基板14封闭成的空间内,故气体引起树脂组成物18移动(即对流),使焊料粉末22强制移动。最终气体从平板10和配线基板14之间的外周部的间隙排出到外部空间。
需要说明的是,添加剂(下面称为对流添加剂)的沸腾或分解可以未必在达到焊料粉末22的熔融温度后进行。也可以以比焊料粉末22的熔融温度低的温度沸腾或分解,产生气体。
在树脂组成物18中产生的气体边在树脂组成物18中对流边到达外周部并向外部排出,因此,焊料粉末22受到由该气体引起的对流能量,也在树脂组成物18中移动。通过该效果,焊料粉末22自聚集在端子部16,形成均匀的补片形状。这样,焊料在端子部16上成长,最终以包围突起部12的方式成长到平板10的表面,形成焊料补片24。
其次,如图1(e)所示,在形成焊料补片24后(在树脂组成物18中加入了对流添加剂的情况下,没有对流添加剂引起的气体排出后),使树脂20硬化。在树脂20硬化后,停止加热,将焊料补片24冷却使其硬化。硬化结束之后,将平板10去除,由此在配线基板14的端子部16上形成中央部具有洼部24a的焊料补片24。
由此,得到在配线基板14的端子部16上形成有中央部具有洼部24a的焊料补片24的焊料补片形成配线基板40。
该焊料补片24由于其高度由平板10和配线基板14的间隙规定,故可使焊料补片24的高度非常均匀。另外,横向直径由端子部16的形状大致规定。该端子部16的形状由于可通过光刻工艺高精度地形成,故有关其横向的直径,也可以非常均匀地形成。而且,洼部24a的形状由突起部12规定,但只要通过光刻工艺加工突起部12,就同样能够形成均匀形状的洼部24a。
因此,本实施方式中形成的焊料补片24的高度、横向直径及洼部24a均能够非常均匀地形成。由此,可使用该焊料补片形成配线基板,在配线基板上成品率高地安装半导体元件等。
需要说明的是,在配线基板14上,也可以在形成焊料补片的区域以外的面上安装半导体元件及无源部件等。
(第二实施方式)
图2是示意性示出本发明的第二实施方式的焊料补片形成方法的工序剖面图。需要说明的是,在本实施方式中,对使用半导体元件34作为电子部件的情况进行说明。另外,对于与第一实施方式共同的工序,不限于本实施方式中的说明,也可以适当使用第一实施方式中所说明的各种条件、材料等。
如图2(a)所示,在平板30的一侧面上,在与半导体元件34的补片形成用端子部36对应的位置处形成凹部32。就这样的凹部32而言,例如使用光刻工艺在平板30上形成规定的图案后,以该图案为掩模,进行蚀刻或喷砂等,若这样的话,就能够以规定的节距形成具有规定深度的凹部32。需要说明的是,作为平板30,例如可使用玻璃板、陶瓷板、硅板或具有耐热性的塑料板等。
其次,如图2(b)所示,在半导体元件34的形成有端子部36的区域涂敷规定量的树脂组成物19。具体而言,在抵接平板30时,树脂组成物19扩散涂敷,将半导体元件34的端子部36全部覆盖,且设定为填充到设于平板30和半导体元件34之间的一定间隙的量。此时的树脂组成物19使用膏状且粘度较大的物质。该树脂组成物19的构成为,以焊料粉末23、对流添加剂(未图示)及树脂21为主要成分。树脂组成物19不仅为膏状,在室温下也可以为片状。
需要说明的是,理想的是,在涂敷树脂组成物19之前,用例如丙酮及乙醇等有机溶剂或清洗液对半导体元件34的表面、特别是端子部36的表面进行清洁化处理。
其次,如图2(c)所示,按照半导体元件34的端子部36和平板30的凹部32对置的方式将半导体元件34和平板30对位,使平板30抵接在树脂组成物19上。通过该抵接,树脂组成物19在半导体元件34和平板30之间均匀地扩散,且保持规定厚度,形成大致密闭区域。
此时,为将平板30和半导体元件34保持一定的间隙,优选将半导体元件34和平板30机械固定。而且,该情况下,若保持平板30和半导体元件34之间的平行度,则是更优选的。
其次,如图2(d)所示,至少将树脂组成物19加热到焊料粉末23熔融的温度。需要说明的是,就树脂组成物19的加热而言,既可以从半导体元件34侧用加热器加热,也可以从平板30侧用加热器加热。或者也可以是将整体置入加热炉中全面进行加热的方法。或者也可以照射微波,仅将树脂组成物19和其附近加热。
在该加热温度下,构成树脂组成物19的树脂21的粘度减小,流动性增加。同时,在该温度下对流添加剂沸腾或分解,排出气体。此时,由于含有排出气体的树脂组成物19被填充到由平板30和半导体元件34封闭的区域内,故气体引起树脂组成物19移动(即对流),使焊料粉末23强制移动。最终气体从平板30和半导体元件34之间的外周部的间隙排出到外部空间。
需要说明的是,对流添加剂的沸腾或分解可以未必在达到焊料粉末23的熔融温度后进行。也可以以比焊料粉末23的熔融温度低的温度沸腾或分解,产生气体。
在树脂组成物19中产生的气体边在树脂组成物19中对流边到达外周部并向外部排出,因此,焊料粉末23受到该气体引起的对流能量,也在树脂组成物1 9中移动。通过该效果,焊料粉末23自聚集在端子部36,形成均匀的补片形状。这样,补片在端子部36上成长,最终成长到平板30的凹部32,形成两段形状的焊料补片38。
其次,如图2(e)所示,在形成焊料补片38后,停止加热,将焊料补片38冷却使其硬化。硬化结束之后,将平板30去除,由此在半导体元件34的端子部36上形成中央部具有突状部38a的焊料补片38。之后,若通过蚀刻等将树脂21去除,则得到形成有图2(e)所示那样的两段形状的焊料补片38的焊料补片形成半导体元件42。
该焊料补片38由于其高度由平板30和半导体元件34的间隙规定,故可设为非常均匀的高度。另外,横向的直径由端子部36的形状大致规定。该端子部36的形状由于可通过光刻工艺高精度地形成,故有关其横向的直径,也可以非常均匀地形成。而且,突状部38a的形状由凹部32规定,但只要通过光刻工艺加工凹部32,就同样能够形成均匀形状的突状部38a。因此,本实施方式中制作的焊料补片38的高度、横向的直径及突状部38a均能够非常均匀地形成。
在上述第一及第二实施方式中,作为配线基板14或半导体元件34的加热温度,优选根据构成树脂组成物18、19的成分设定最佳的温度曲线。例如,在使用锡-银-铜(Sn-Ag-Cu)合金焊料作为焊料粉末22、23,使用异丙醇作为对流添加剂的情况下,作为最终到达温度,优选设定为230℃~240℃的温度范围。
另外,当在连接结束后使树脂21热硬化时,例如在使用环氧树脂时,优选加热到100℃~250℃的范围。
需要说明的是,作为焊料粉末22、23,不限于上述的Sn-Ag-Cu合金。例如也可以使用锡-锌(Sn-Zn)系合金焊料、锡-铋(Sn-Bi)系合金焊料、铜-银(Cu-Ag)系合金焊料、锡(Sn)焊料、铟(In)焊料、或铅(Pb)系焊料等。
另外,作为对流添加剂,只要是乙醇及酯等脂肪族及芳香族系的溶剂等加热到作业温度时因沸腾或分解而产生气体的物质即可。也可以是在加热作为电子部件的配线基板14及半导体元件34,在使焊料粉末22、23熔融的温度下沸腾或分解从而排出气体的材料。需要说明的是,树脂组成物18、19中,为去除焊料粉末22、23的表面及端子部16、36的面上形成的氧化膜,也可以含有松香等氧化膜去除剂。
另外,在第一及第二实施方式中,焊料粉末22、23自聚集而成长的端子部16、36为圆形状。在该圆形部,焊料补片选择性地自聚集而成长。该端子部16、36的至少表面优选形成相对焊料润湿性好的金属材料、例如金(Au)。另外,不仅使用银(Ag)、铜(Cu)、钯(Pb)、铑(Rh)、铂(Pt)、铱(Ir)等金属材料,也可以使用构成焊料的锡(Sn)及铟(In)等。需要说明的是,端子部16、36的形状除圆形状以外,也可以为椭圆形状、四边形、线状等,没有特别限定。
再有,理想的是,在含有导体配线等且想要抑制焊料自聚集成长的区域形成例如由氧化膜或氮化膜、氧化氮化膜等无机材料构成的表面保护膜、或由聚酰亚胺、环氧树脂等树脂构成的表面保护膜。
另外,在第一及第二实施方式中,在树脂组成物18、19上抵接平板10、30,以施加压力的状态加热配线基板14及半导体元件34,但未必需要加压。只要具有配线基板14及半导体元件34不会因来自对流添加剂的气体而动作的程度的形状和重量,则也可以不特别加压。
另外,在第一及第二实施方式中,加热树脂组成物18、19,使树脂组成物中含有的焊料粉末22、23熔融,但也可以加热到焊料粉末不熔融的温度,使树脂组成物18、19中含有的添加剂沸腾或分解而排出气体,该排出的气体使树脂组成物18、19进一步移动,通过表面张力使树脂组成物18、19自聚集到端子部16、36上。该情况下,进一步加热自聚集后的树脂组成物18、19,使树脂组成物中含有的焊料粉末22、23熔融,使焊料自聚集到端子部16、36上,由此可形成焊料补片24、38。
这样,在使含有焊料粉末的树脂组成物自聚集到端子部上而形成焊料补片的情况下,例如在使用形成有凹部32的平板30实施第二实施方式时,由于流动的树脂组成物19容易滞留在凹部32处,故可使树脂组成物19容易地自聚集到端子部36上,然后,通过使焊料粉末23熔融,可在端子部36上形成焊料补片38。该情况下,焊料补片38可不增大平板30和半导体元件34(或配线基板14)之间的间隙,形成高度高的焊料补片38。需要说明的是,若在将焊料补片38硬化前去除平板30,则也可以在大致维持高度的同时形成没有突状部38a(不是两段形状)的焊料补片38。
(第三实施方式)
图3是示意性示出本发明的第三实施方式的半导体元件的安装方法的工序剖面图。需要说明的是,本实施方式的半导体元件的安装方法的特征在于,使用利用第一实施方式的方法形成的焊料补片形成配线基板40和利用第二实施方式的方法形成的焊料补片形成半导体元件42进行安装。
图3(a)是将形成有中央具有突状部38a的焊料补片38的半导体元件34和形成有中央具有洼部24a的焊料补片22的配线基板14进行了对位的状态。此时,形成洼部24a的内径比突状部38a的外径稍小。另外,半导体元件34的焊料补片38使用比配线基板12的焊料补片24的融点高的材料。
图3(b)示出将半导体元件34的焊料补片38的突状部38a嵌合于配线基板14的焊料补片24的洼部24a的状态。由于半导体元件34的补片38为高融点材料,故通常比配线基板14的焊料补片24硬。因此,将焊料补片38的突状部38a按照压开焊料补片24的洼部24a的方式嵌合。这样,虽然在配线基板14的焊料补片24上施加大面积的力,但由于在焊料补片24的外周部具有树脂20,故焊料补片24的形状不会被破坏。
而且,当将配线基板14的焊料补片24加热到其不会熔融的程度的温度时,可更顺畅地进行嵌合。通过这样进行嵌合,进行电连接、机械连接。
通过以上那样的安装方法,可将半导体元件34安装在配线基板14上。根据该方法,即使在常温下也可以连接,但若加热到配线基板14的焊料补片24不熔融的程度的温度,则能够以更小的负荷进行连接。
需要说明的是,在本实施方式中,对采用嵌合方式的连接进行了说明,但本发明不限于此。例如,也可以在将半导体元件34的焊料补片38的突状部38a嵌合到配线基板14的焊料补片24的洼部24a后,将低融点侧的焊料补片加热到熔融温度后再接合。或者也可以将高融点侧的焊料补片加热到熔融温度后再接合。若这样加热接合,则各焊料补片的焊料熔融而一体化,因此,也能够进一步增大机械强度。
另外,在进行这样的连接后,通过进一步填充欠装树脂,可进一步增大半导体元件34和配线基板14的机械连接强度。
另外,在本实施方式中,对半导体元件34的焊料补片38和配线基板14的焊料补片24的材料不同的情况进行了说明,但本发明不限于此。
另外,配线基板40的具有凹部的焊料补片24及半导体元件34的具有的突状部的焊料补片38使用利用第一及第二实施方式的方法形成的部件,但在只形成任一个焊料补片时,也可以应用第一或第二实施方式的方法。另外,也可以将凹部和突状部相反地形成。
图4是示出本实施方式的半导体元件的安装方法的变形例的半导体元件安装构造体的剖面图。该安装构造体中,半导体元件的焊料补片和配线基板的焊料补片使用相同的焊料材料。
在该安装方法中,在将半导体元件34的焊料补片的突状部嵌合到配线基板14的焊料补片的凹部之后,将其加热到焊料的熔融温度,从而连接两者。通过熔融,各焊料补片熔融而成为一体化补片44。该情况下,在配线基板14的焊料补片的外周部设有树脂20,该树脂20在焊料的熔融温度下也保持其形状。另外,也可以在形成一体化补片44后,注入欠装树脂46来增强半导体元件安装构造体。
由此,一体化补片44可不形成为半球形状而是维持纵长形状。另外,在熔融之前,由于半导体元件34的焊料补片和配线基板14的焊料补片嵌合,故难以产生位置偏移。其结果是,与现有的安装方法相比,可进行精密节距的连接。
图5是示出本实施方式的半导体元件的安装方法的其它变形例的半导体元件安装构造体的剖面图。在该安装构造体中,半导体元件的焊料补片和配线基板的焊料补片使用不同的焊料材料。另外,在半导体元件34侧也残留有树脂21。
在该安装方法中,将半导体元件34的焊料补片38的突状部38a嵌合并连接于配线基板14的焊料补片24的洼部24a。进而通过将整体加热,将配线基板14侧的树脂20和半导体元件34侧的树脂21粘接而确保机械强度。因此,只要使配线基板14侧的树脂20或半导体元件34侧的树脂21的任一个为热塑性树脂或B级状态的树脂即可。由于可以利用这些树脂20、21在焊料安装时进行密封,故可将工序简化。
需要说明的是,在本实施方式的安装方法中使用了不同的焊料材料,但也可以在使用相同的焊料材料进行嵌合后再熔融而一体化。即使是这样熔融,树脂20、21也能够将焊料补片的周围包围,因此,一体化的焊料补片不会成为半球形状,对于精密节距而言也不会有短路不良产生。
(第四实施方式)
图6是示意性示出本发明的第四实施方式的焊料补片形成方法的工序剖面图。在本实施方式中,对使用配线基板54作为电子部件的情况进行说明。另外,与第一或第二实施方式相同的工序不限于本实施方式中的说明,可适当应用第一或第二实施方式中所说明的各种条件、材料等。
如图6(a)所示,在平板50的一侧面上,在与配线基板54的补片形成用的端子部56对应的位置处形成突起部52。该突起部52的高度与涂敷于端子部56上的树脂组成物58的厚度大致相同。
就这样的突起部52而言,例如在平板50上进行光刻工艺,形成规定的图案后,以该图案为掩模,通过进行蚀刻或喷砂等出去不需要的部分,据此,能够以规定的节距形成具有一定高度的突起部52。或者也可以使用树脂基材作为平板50,将具有突起部52的形状的针脚埋入树脂基材中立设形成。在通过蚀刻及喷砂形成的情况下,作为平板10,例如可使用玻璃板、陶瓷板、或硅板等。另外,不只是埋入针脚的方式,也可以通过粘接而形成突起部52。该情况下,不限于使用树脂基材,也可以使用玻璃板等。
另外,如图7所示,在突起部52上形成有起模层72,在该起模层72的面上形成有相对于补片润湿性好的金属膜74。图7是示出形成有相对于在突起部的表面层上形成的起模层和焊料润湿性优良的金属膜的状态的局部放大剖面图。作为起模层72,例如只要涂敷氟树脂等具有耐热性的树脂材料即可。该起模层72如图7所示,也可以在平板50的表面形成。另外,作为金属膜74,例如也可以通过蒸镀等形成与树脂组成物58中所含的焊料粉末62相同的焊料来使用。或者也可以使用构成焊料粉末62的单体元素。或者也可以通过蒸镀或镀敷等形成相对于焊料润湿性好的金(Au)、银(Ag)等金属。在通过蒸镀进行形成时,只要在整个面上形成后利用光刻工艺和蚀刻工艺将形成在平板50的表面上的金属膜去除即可。另外,也可以只是形成起模层72或金属膜74中的任一个。需要说明的是,起模层72和金属膜74在图6中未图示。
另外,配线基板54既可以为多层结构,也可以为两面配线基板。作为基材,只要是耐受焊料的熔融温度的材料,就没有特别限制,可以是玻璃环氧树脂基板、聚酰亚胺基板等树脂基板、陶瓷基板或玻璃基板、进而也可以是硅基板。
在配线基板54的形成有端子部56的面上也形成有未图示的导体配线。当在这些导体配线上也形成有树脂组成物58时,优选在形成于该面上的导体配线的表面上形成未涂敷焊料的材料、例如抗镀敷剂等树脂膜或无机绝缘膜等。另外,为了高精度地规定焊料成长的端子部56的区域,优选在端子部56的周围也形成抗镀敷剂等。
其次,如图6(b)所示,在配线基板54的形成有端子部56的区域涂敷规定量的树脂组成物58。具体而言,在抵接平板50时,树脂组成物58扩散涂敷,将配线基板54的端子部56全部覆盖,且设定为填充到设于平板50和配线基板54之间的一定间隙的量。此时的树脂组成物58使用膏状且粘度较大的物质。该树脂组成物58为含有焊料粉末62、对流添加剂(未图示)及树脂60为主成分的构成。需要说明的是,树脂组成物58不仅为膏状,而且在室温下也可以为片状。另外,理想的是,在涂敷树脂组成物58之前,配线基板54的表面特别是端子部56的表面用例如丙酮及乙醇等有机溶剂或清洗液进行清洁化处理。
其次,如图6(c)所示,按照配线基板54的端子部56和平板50的突起部52对置的方式将配线基板54和平板50对位。然后,按照平板50的突起部52接触端子部56的方式压下端子部56,同时使平板50的表面抵接在树脂组成物58上。通过该抵接,树脂组成物58在配线基板54和平板50之间均匀地扩散,且保持规定的厚度,形成大致密闭空间。通过这样抵接,利用平板50的突起部52,可将配线基板54和平板50的间隔保持一定。此时,理想的是,平板50和配线基板54机械固定。
其次,如图6(d)所示,至少将树脂组成物58加热到焊料粉末62熔融的温度。就树脂组成物58的加热而言,既可以从配线基板54侧用加热器加热,也可以从平板50侧用加热器加热。或者也可以是将整体置入加热炉中全面进行加热的方法。或者也可以照射微波,仅将树脂组成物58和其附近加热。
在该加热温度下,构成树脂组成物58的树脂60的粘度减小,流动性增加。同时,在该温度下,对流添加剂沸腾或分解,排出气体。此时,由于含有排出气体的树脂组成物58被填充到由平板50和配线基板54封闭成的空间内,故气体从平板50和配线基板54之间的外周部的间隙排出到外部空间。
对流添加剂的沸腾或分解可以未必在达到焊料粉末62的熔融温度后进行。也可以以比焊料粉末62的熔融温度低的温度沸腾或分解,产生气体。
在树脂组成物58中产生的气体边在树脂组成物58中对流边到达外周部并向外部排出,因此,焊料粉末62受到该气体引起的对流能量,也激烈地在树脂组成物58中移动。通过该效果,焊料粉末62自聚集在端子部56,形成均匀的补片形状。另外,由于在突起部52的表面形成有相对于焊料润湿性良好的金属膜74,故焊料粉末62也自聚集在突起部52。因此,在本实施方式中,在端子部56和突起部52的区域,焊料同时成长。
这样,焊料在端子部56和突起部52的表面上成长,最终以包围突起部52的方式成长到平板50的表面,形成焊料补片64。
其次,如图6(e)所示,在形成焊料补片64后,停止加热,将焊料补片64冷却使其硬化。硬化结束之后,将平板50去除,由此在配线基板54的端子部56上形成中央部具有达到端子部56的洼部64a的焊料补片64。由于在突起部52的表面形成有起模层72,故在去除平板50时,可在起模层72和金属膜74之间容易离开。
在使用热塑性树脂作为树脂组成物58的树脂60时,停止加热并使其冷却,由此树脂60也硬化。
由此,可得到在配线基板54的端子部56上形成有中央部具有到达端子部56的洼部64a的焊料补片64的焊料补片形成电子部件、即焊料补片形成配线基板。
该焊料补片64由于其高度由平板50和配线基板54的间隙规定,故可使焊料补片64的高度非常均匀。另外,由于焊料的成长是在端子部56和突起部52的多个区域成长的,故横向的直径不太宽,从而可形成高的焊料补片64。另外,中央部具有到达端子部56的洼部64a,例如若安装半导体元件,则能够成品率高地进行安装。
图8是示出在具有本实施方式中制作的焊料补片64的配线基板54上安装了半导体元件66的安装构造体的剖面图。在半导体元件66上,在端子部68的表面设有与焊料补片64的洼部64a的形状大致相同的补片70。例如也可以通过镀敷金(Au)来形成补片70。或者也可以以双端补片的方式形成。
当将半导体元件66的补片70嵌合于配线基板54的焊料补片64的洼部64a时,进行电连接、机械连接。之后,当加热热可塑性或B级状态的树脂60并对其进行按压时,树脂60软化,也粘接在半导体元件66的表面。由此,将安装区域密封。
在本实施方式中,在配线基板上形成有焊料补片,但本发明不限于此,也可以在半导体元件上形成上述那样的焊料补片。该情况下,由于可以以晶片状态形成,故可更有效地进行焊料补片的形成。
另外,在本实施方式中,对凸型及凹型的焊料补片的形成进行了说明,但本发明不限于此,也可以形成为三棱柱、四棱柱、火山口形状、两段突起等复杂的形状。
以上用优选实施方式说明了本发明,但这种表述不是限定事项,当然可进行各种改变。
本实施方式中的“嵌合”是指,将在半导体元件或配线基板的一方形成的焊料补片的突状部插入到在半导体元件或配线基板的另一方形成的凹部的状态,未必是无间隙嵌合的状态。
另外,本实施方式中的“对流”是指作为运动状态的对流,由于排出到树脂组成物中的气体运动,从而给予分散到树脂组成物中的焊料粉末动能,只要是给予促进焊料粉末移动的作用的运动,则可以为任意运动方式。
工业实用性
本发明的焊料补片形成方法及半导体元件的安装方法可提供能够进行高密度安装的焊料补片形成方法、同时可提供可靠性高的半导体元件的安装方法。
Claims (12)
1.一种焊料补片形成方法,是在具有多个端子部的电子部件的该端子部上形成焊料补片的方法,其特征在于,包括:
准备在表面形成有多个突起部或凹部的平板的工序;
将所述平板与所述电子部件相对配置,并向所述平板和所述电子部件的间隙供给含有焊料粉末的树脂组成物的工序;
加热所述树脂组成物,使该树脂组成物中含有的所述焊料粉末熔融,通过使该熔融的焊料粉末自聚集到所述端子部上而使之成长到所述平板的表面,由此在所述端子部上形成焊料补片的工序;以及
在冷却所述焊料补片并使其硬化后,去除所述平板的工序,
其中,所述焊料补片具有与所述突起部对应的洼部或与所述凹部对应的突状部。
2.如权利要求1所述的焊料补片形成方法,其特征在于,所述树脂组成物在形成所述焊料补片的工序中还含有加热所述树脂组成物时沸腾或分解并排出气体的对流添加剂。
3.如权利要求1所述的焊料补片形成方法,其特征在于,供给所述树脂组成物的工序包括:
向所述电子部件上供给所述树脂组成物的工序;和
与所述电子部件对置地使所述平板抵接所述树脂组成物的表面的工序。
4.如权利要求3所述的焊料补片形成方法,其特征在于,在使所述平板与所述树脂组成物抵接的工序中,
使所述突起部与所述端子部接触地使所述平板与所述树脂组成物的表面抵接。
5.如权利要求1所述的焊料补片形成方法,其特征在于,所述电子部件是配线基板或半导体元件。
6.如权利要求1所述的焊料补片形成方法,其特征在于,在所述突起部或所述凹部的表面形成有相对于焊料具有润湿性的金属膜。
7.如权利要求1所述的焊料补片形成方法,其特征在于,在所述突起部或所述凹部的表面形成有相对于该突起部或该凹部具有起模性的起模层。
8.如权利要求1所述的焊料补片形成方法,其特征在于,在去除所述平板的工序之后,还含有去除所述树脂组成物的工序。
9.如权利要求1所述的焊料补片形成方法,其特征在于,形成所述焊料补片的工序包括下述工序:
加热所述树脂组成物,使所述树脂组成物自聚集到所述端子部上,然后,进一步加热所述树脂组成物,使该树脂组成物中含有的所述焊料粉末熔融,通过使该熔融的焊料粉末自聚集到所述端子部上而使之成长到所述平板的表面,由此,在所述端子部上形成焊料补片。
10.一种半导体元件的安装方法,是在配线基板上安装半导体元件的方法,其特征在于,包括:
在所述半导体元件或所述配线基板中的一个的端子部上形成具有洼部的焊料补片的工序;
在所述半导体元件或所述配线基板的另一个的端子部上形成具有突状部的焊料补片的工序;以及
将在所述半导体元件的端子部上形成的焊料补片和在所述配线基板的端子部上形成的焊料补片彼此嵌合并接合的工序,
其中,具有所述洼部的焊料补片及具有所述突状部的焊料补片的至少其中之一是通过所述权利要求1所述的焊料补片形成方法形成的。
11.如权利要求10所述的半导体元件的安装方法,其特征在于,将所述焊料补片彼此嵌合并接合的工序含有使彼此嵌合的所述焊料补片的至少一方熔融的加热工序。
12.如权利要求11所述的半导体元件的安装方法,其特征在于,所述半导体元件的焊料补片和所述配线基板的焊料补片由不同的焊料材料构成。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006109407A1 (ja) * | 2005-04-06 | 2006-10-19 | Matsushita Electric Industrial Co., Ltd. | フリップチップ実装方法及びバンプ形成方法 |
WO2006123554A1 (ja) * | 2005-05-17 | 2006-11-23 | Matsushita Electric Industrial Co., Ltd. | フリップチップ実装体およびフリップチップ実装方法 |
JP4251458B2 (ja) * | 2005-12-21 | 2009-04-08 | Tdk株式会社 | チップ部品の実装方法及び回路基板 |
WO2007122868A1 (ja) * | 2006-03-28 | 2007-11-01 | Matsushita Electric Industrial Co., Ltd. | バンプ形成方法およびバンプ形成装置 |
US7823762B2 (en) * | 2006-09-28 | 2010-11-02 | Ibiden Co., Ltd. | Manufacturing method and manufacturing apparatus of printed wiring board |
US8887383B2 (en) | 2006-12-18 | 2014-11-18 | Panasonic Corporation | Electrode structure and method for forming bump |
JP4618260B2 (ja) * | 2007-02-21 | 2011-01-26 | 日本テキサス・インスツルメンツ株式会社 | 導体パターンの形成方法、半導体装置の製造方法、並びに半導体装置 |
US20090057378A1 (en) * | 2007-08-27 | 2009-03-05 | Chi-Won Hwang | In-situ chip attachment using self-organizing solder |
US20090250814A1 (en) * | 2008-04-03 | 2009-10-08 | Stats Chippac, Ltd. | Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof |
US20100044416A1 (en) * | 2008-08-21 | 2010-02-25 | Nec Corporation | Method of manufacturing electronic components having bump |
TWI455263B (zh) * | 2009-02-16 | 2014-10-01 | Ind Tech Res Inst | 晶片封裝結構及晶片封裝方法 |
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US8912651B2 (en) | 2011-11-30 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) structure including stud bulbs and method |
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US10020275B2 (en) * | 2013-12-26 | 2018-07-10 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductive packaging device and manufacturing method thereof |
US9437566B2 (en) * | 2014-05-12 | 2016-09-06 | Invensas Corporation | Conductive connections, structures with such connections, and methods of manufacture |
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TWI644408B (zh) * | 2016-12-05 | 2018-12-11 | 美商美光科技公司 | 中介層及半導體封裝體 |
JP7086702B2 (ja) * | 2018-05-08 | 2022-06-20 | 新光電気工業株式会社 | 配線基板及びその製造方法、半導体装置 |
TWI697078B (zh) * | 2018-08-03 | 2020-06-21 | 欣興電子股份有限公司 | 封裝基板結構與其接合方法 |
JP6767665B1 (ja) * | 2020-06-10 | 2020-10-14 | 千住金属工業株式会社 | バンプ電極基板の形成方法 |
US11715716B2 (en) * | 2021-07-16 | 2023-08-01 | Advanced Semiconductor Engineering, Inc. | Electronic device, package structure and electronic manufacturing method |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5130779A (en) * | 1990-06-19 | 1992-07-14 | International Business Machines Corporation | Solder mass having conductive encapsulating arrangement |
JP2880825B2 (ja) | 1991-06-28 | 1999-04-12 | 株式会社東芝 | 半導体素子の実装方法 |
US5286417A (en) * | 1991-12-06 | 1994-02-15 | International Business Machines Corporation | Method and composition for making mechanical and electrical contact |
JPH06310565A (ja) * | 1993-04-20 | 1994-11-04 | Fujitsu Ltd | フリップチップボンディング方法 |
US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
US6025258A (en) * | 1994-01-20 | 2000-02-15 | Fujitsu Limited | Method for fabricating solder bumps by forming solder balls with a solder ball forming member |
US5958590A (en) * | 1995-03-31 | 1999-09-28 | International Business Machines Corporation | Dendritic powder materials for high conductivity paste applications |
TW336371B (en) * | 1995-07-13 | 1998-07-11 | Motorola Inc | Method for forming bumps on a substrate the invention relates to a method for forming bumps on a substrate |
US5872051A (en) * | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
US6609652B2 (en) * | 1997-05-27 | 2003-08-26 | Spheretek, Llc | Ball bumping substrates, particuarly wafers |
JPH1117050A (ja) | 1997-06-20 | 1999-01-22 | Matsushita Electric Ind Co Ltd | 回路基板及び回路基板の製造方法 |
US5961032A (en) * | 1997-06-30 | 1999-10-05 | International Business Machines Corporation | Method of fabrication of a multi-component solder column by blocking a portion of a through hole in a mold |
JPH11243106A (ja) * | 1998-02-26 | 1999-09-07 | Nichiden Mach Ltd | 半田ボールの製造治具およびそれを用いた半田ボールの製造方法並びにその半田ボールを用いた半田バンプの形成方法 |
US6137063A (en) * | 1998-02-27 | 2000-10-24 | Micron Technology, Inc. | Electrical interconnections |
JP2000100868A (ja) | 1998-09-22 | 2000-04-07 | Toshiba Corp | 半導体装置およびその製造方法 |
JP3204319B2 (ja) * | 1999-01-22 | 2001-09-04 | 日本電気株式会社 | ディスプレイパネルの製造方法 |
US6225206B1 (en) * | 1999-05-10 | 2001-05-01 | International Business Machines Corporation | Flip chip C4 extension structure and process |
US6295730B1 (en) * | 1999-09-02 | 2001-10-02 | Micron Technology, Inc. | Method and apparatus for forming metal contacts on a substrate |
JP2002093842A (ja) | 2000-09-12 | 2002-03-29 | Hitachi Ltd | 半導体デバイスおよびその製造方法 |
SG99877A1 (en) * | 2001-01-04 | 2003-11-27 | Inst Materials Research & Eng | Forming an electrical contact on an electronic component |
US6674647B2 (en) * | 2002-01-07 | 2004-01-06 | International Business Machines Corporation | Low or no-force bump flattening structure and method |
JP2004103928A (ja) * | 2002-09-11 | 2004-04-02 | Fujitsu Ltd | 基板及びハンダボールの形成方法及びその実装構造 |
JP2004158701A (ja) * | 2002-11-07 | 2004-06-03 | Seiko Epson Corp | 素子チップ実装用のバンプ構造及びその形成方法 |
JP3769688B2 (ja) * | 2003-02-05 | 2006-04-26 | 独立行政法人科学技術振興機構 | 端子間の接続方法及び半導体装置の実装方法 |
EP1729334A4 (en) * | 2004-03-22 | 2010-06-02 | Tamura Seisakusho Kk | LOT COMPOSITION AND METHOD FOR HILLING THEREFOR |
US20060108402A1 (en) * | 2004-11-19 | 2006-05-25 | Tessera, Inc. | Solder ball formation and transfer method |
US7273806B2 (en) * | 2004-12-09 | 2007-09-25 | International Business Machines Corporation | Forming of high aspect ratio conductive structure using injection molded solder |
US7332423B2 (en) * | 2005-06-29 | 2008-02-19 | Intel Corporation | Soldering a die to a substrate |
-
2006
- 2006-04-25 WO PCT/JP2006/308616 patent/WO2006126361A1/ja active Application Filing
- 2006-04-25 CN CNB2006800180099A patent/CN100501957C/zh not_active Expired - Fee Related
- 2006-04-25 US US11/579,505 patent/US7611040B2/en active Active
- 2006-04-25 JP JP2006522160A patent/JP4401386B2/ja active Active
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WO2006126361A1 (ja) | 2006-11-30 |
US20080197173A1 (en) | 2008-08-21 |
JPWO2006126361A1 (ja) | 2008-12-25 |
CN100501957C (zh) | 2009-06-17 |
US7611040B2 (en) | 2009-11-03 |
JP4401386B2 (ja) | 2010-01-20 |
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