CN100570835C - Metal-insulator-semiconductor device fabrication method - Google Patents

Abstract

The present invention relates to adopt low temperature process to make the MIS semiconductor device of high reliability.A kind of method of the MIS of manufacturing semiconductor device is disclosed, wherein, in semiconductor chip or semiconductive thin film, form doped region selectively, so take preventive measures, so that laser or suitable high strength luminous energy shine the border between the doped region active area adjacent with it, and, and reach the effect of activation from the light of last surface irradiation laser or suitable high light intensity.

Description

Metal-insulator-semiconductor device fabrication method

technical field

The present invention relates to a metal (M)-insulator (I)-semiconductor (S) device generally called a MIS semiconductor device (also called an insulated gate semiconductor device). The above-mentioned MIS semiconductor devices include, for example, MOS transistors and thin film transistors and the like.

Background technique

In the prior art, a self-alignment technology is used to manufacture MIS semiconductor devices. According to the above technique, a gate electrode is formed on a semiconductor substrate or a semiconductor film, and a gate insulating film is provided between them, and impurities are introduced into the semiconductor substrate or semiconductor film by using the gate electrode as a mask. Thermal diffusion, ion implantation, plasma doping, and laser doping are typical methods for introducing impurities. Using self-alignment technology, it is basically possible to align the edges of the doped region (source and drain) with the edge of the gate electrode, eliminating the overlap between the gate electrode and the doped region (the structure that may generate parasitic capacitance) and the gate electrode Separation by distance from doped regions (which may reduce effective mobility).

However, the prior art process has a problem that the spatial carrier concentration gradient formed between the doped regions and their adjacent active regions (channel forming regions) formed under the gate electrode is too steep, so , generates a very large electric field, especially when a reverse bias is applied to the gate electrode, increasing the leakage current (OFF current).

In order to solve the above-mentioned problems, the present inventors and others have found that by slightly offsetting the gate electrode relative to the doped region, the above-mentioned problems can be improved, and that the gate electrode is formed of an anodizable material and the anode The oxide film is used as a mask to introduce impurities, and it is possible to obtain a shift of 300nm or less with good repeatability.

In addition, in the case of ion implantation, plasma doping and other methods, including the case of implanting ions into a semiconductor substrate or a semiconductor film at a high speed, the crystallinity of the semiconductor substrate or film needs to be improved (activated) because the implanted ions The crystallinity of the structure at the site is damaged due to the penetrating ions. In the prior art, it has been practiced to improve crystallinity by employing a heating method at a temperature of 600° C. or higher, and a lower processing temperature is required according to a recent trend. In light of the foregoing, the present inventors and others have shown that activation can also be performed using laser light or comparable high intensity light, and that such activation has significant advantages for mass production.

FIG. 2 shows the process steps of manufacturing a thin film transistor according to the above basic principles. First, a bottom insulating film 202 is deposited over the entire substrate 201, and then, an island-shaped crystalline semiconductor region 203 is formed, and an insulating film 204 as a gate insulating film is formed thereon. The gate connection 205 is then formed using an anodizable material (FIG. 2(A)).

Next, the gate wiring is anodized to form an anodized film 206 having a thickness of 300 nm or less, preferably 250 nm or less, on the surface of the gate wiring. Using the anodized film as a mask, impurities such as phosphorus (P) are introduced by a method such as ion implantation or ion doping to form doped regions 207 (FIG. 2(B)).

In addition, high-intensity light such as laser light is irradiated from above in order to activate the region where the impurity is introduced (FIG. 2(C)).

Finally, an interlayer insulator 208 is deposited, contact holes are opened on the doped region, and an electrode 209 for connecting the doped region is formed, thus completing the manufacture of the thin film transistor (FIG. 2(D)).

However, it was found that in the above process, the boundary (indicated by x in FIG. 2(C)) between the doped region and the active region (the semiconductor region just below the gate and surrounded by the two doped regions) It is unstable, and after a long time of use, the reliability will be reduced due to the increase of leakage current and so on. That is, it can be seen from the process that the crystallinity of the active region remains basically unchanged throughout the process; on the other hand, the doped region adjacent to the active region has the same crystallinity as the active region at the beginning, However, their crystallinity is impaired during the process of introducing impurities. In successive laser irradiation steps, the doped region is repaired, but it is difficult to restore the original crystallinity. Furthermore, it was found that especially the part of the doped region which is in contact with the active region cannot be sufficiently activated, since that part tends to remain unirradiated by laser light. This creates a discontinuity in crystallinity between the doped and active regions, trapping, etc. Especially when impurities are introduced by a method including implanting high-speed ions, impurity ions scatter and penetrate regions under the gate, so as to damage the crystallinity of these regions. It is not possible to laser or otherwise light activate the regions below the gate electrode because they are under the mask of the gate electrode.

One way to solve this problem is to radiate laser or other light from the reverse side in order to activate these areas. In this way, the boundary between the active region and the doped region can be sufficiently activated because the gate wiring does not block light. However, this method requires the substrate material to be light-transmitting. Of course, when using a silicon wafer or the like as a substrate, this method cannot be used. In addition, most glass materials are not easy to transmit ultraviolet light with a wavelength of less than 300nm, so , for example, KrF excimer laser light (wavelength 248 nm), which realizes extremely high productivity, cannot be utilized.

Contents of the invention

In view of the above problems, an object of the present invention is to provide a MIS semiconductor device, such as a MOS transistor and a thin film transistor, in which the reliability of the device is enhanced due to the continuity in crystal growth between the active region and the doped region. .

The invention makes the device such that energy emitted by a high-intensity light source, such as a laser or a flash lamp, irradiates the doped region from above for activating the doped region, not only the doped region, but also a part of the active region adjacent to it , especially the boundary between the active region and the doped region, is also irradiated by light energy. To achieve this, a portion of the material forming the gate electrode is removed.

According to the first solution of the present invention, the following process steps are included: In the first step, in order to form a doped region, a material for masking is formed on the crystal semiconductor substrate or semiconductor film, and then the material is used as a mask, and the introduction of impurities into the semiconductor substrate or semiconductor film, a second step, wherein the masking material is removed such that light energy can be irradiated to the doped region and the active region, in this case, the irradiated light energy is used for activation; the second step Step 3, wherein a gate electrode (gate wiring) is formed on the active region.

When using this process, if an offset region is to be formed, the mask pattern for forming the doped region should have a width greater than that of the gate electrode pattern. If the width of the gate electrode pattern is larger than that of the mask pattern implanted with impurities, the resulting gate electrode will overlap the doped region.

Furthermore, when different photomasks are used in each step, it is difficult to place the masks precisely at the same position. Especially in mass production it is not possible to achieve the offset condition of 1 μm or less as required by the present invention. On the other hand, overlaying with the same photomask is quite easy. For example, assume that a certain photomask is used to form a wiring pattern, and then use this pattern as a mask to form a doped region, and then remove the connection region. When wiring was subsequently formed using the same photomask as described above, almost no offset occurred. However, subsequent anodization of the wiring surface results in a reduction in the conductive surface of the wiring and achieves the desired offset.

On the other hand, if the formed wiring is anodized first, the resulting anodized surface advances; if the anodized wiring is used as a mask to form the doped region, the doped region is formed outside the initially formed wiring pattern. Then, anodize the 2nd wire, the shrinkage of the conductive surface of the wire will increase the offset.

Thus, the desired offset can be relatively easily obtained by forming the gate electrode from an anodizable material and then anodizing the gate electrode. It is recognized that the resulting anodized layer can also be used to prevent short circuits between layers. It was also recognized that, in addition to anodizing, covering the gate electrode (wiring) with an interlayer insulator or the like can reduce the coupling capacitance with the upper wiring.

According to the second solution of the present invention, the process steps include: a first step, wherein an insulating film as a gate electrode insulating film is formed on a crystalline semiconductor or a semiconductor film, and then the insulating film is used as a mask, and the Impurities are introduced into the semiconductor substrate or semiconductor film; 2nd step, wherein the boundary of the gate electrode is selectively etched so that the gate electrode is offset relative to the doped region, so that light energy can be radiated to the doped region and the active region The boundary between, under this condition, the irradiated light can play an activation role.

Preferably, the gate electrode is formed of an anodizable material, and after exposure to light energy, the gate electrode is anodized to cover its surface with a high-resistance anodic oxide layer, and the anodic oxide is further covered with an interlayer insulator or the like to Reduce the coupling capacitance with the upper layer wiring.

According to the third solution of the present invention, the following process steps are included: the first step, wherein, on the crystalline semiconductor substrate or the semiconductor film, an insulating film as a gate insulating film is formed, and then a gate connection line ( gate electrode), use the gate connection wire as the gate electrode, and electrochemically coat the surface of the electrode with a conductive material or the like by an electrochemical reaction method (ie, electroplating); in the second step, use the thus-treated gate electrode region (gate electrode and the conductive material deposited on its surface) as a mask, introducing impurities into the semiconductor substrate or semiconductor film by a self-alignment method; and a 3rd step, wherein, thus removing part or all of the previously deposited material , so that the light energy can be irradiated to the boundary between the doped region and the active region. Under this condition, the irradiated light energy plays an activation role.

Preferably, the gate electrode is formed from an anodized material, and after being irradiated with light energy, the gate electrode is anodized to cover its surface with a high-resistance anodized layer, and then the anodized layer is covered with an interlayer insulator or the like so as to reduce contact with the upper layer. The coupling capacitance of the connection.

Preferred anodizable materials for use in the present invention include aluminum, titanium, tantalum, silicon, tungsten and molybdenum. These materials may be used alone or in an alloy form to form a gate electrode of a single-layer or multi-layer structure. It is known that minor amounts of other elements can be added to the aforementioned materials. For anodizing, a wet process is generally used in which the anodizing is done in an electrolytic solution, but it is also known that the well-known plasma anodizing method (oxidation in a reduced pressure plasma atmosphere) can be used. It should also be understood that the oxidation process is not limited to the above-mentioned anodic oxidation, and other suitable oxidation methods can also be used.

Optical energy sources suitable for use in the present invention include: excimer lasers. For example, KrF laser (wave light is 248nm), XeCl laser (308nm), ArF laser (193nm), XeF laser (353nm), etc.; Nd:YAG laser (1064nm) and its 2nd, 3rd and 4th harmonics; coherent Light source, for example, carbon dioxide gas laser, argon ion laser, copper vapor laser, etc.; incoherent light source, for example, xenon flash lamp, krypton arc lamp, etc.

The MIS semiconductor device manufactured by the above process is characterized in that the junction of the doped region (source and drain) and the gate electrode region (including the gate electrode and its connected anodic oxide layer) are basically the same when viewed from the top and the bottom The shape (similar shape) offsets the gate electrode (area defined by the conductive surface and isolated connected anodic oxide) relative to the doped region.

When the gate electrode has no oxide layer formed thereon such as an anodic oxide layer, there is no oxide layer formed around the gate electrode, the gate electrode is offset relative to the impurity region, and the width of the offset is preferably 0.1 to 0.5 [mu]m.

The present invention also enables control of, for example, the thickness of anodic oxide layers, such as individual oxide layers formed on the same substrate, for example, by applying a voltage to each wiring. In this case, appropriate values for the thickness of the oxide layer of the gate region portion and the thickness of the capacitor portion (or the portion at the intersection between the wiring lines) suitable for the respective purposes can be set independently of each other.

Description of drawings

1(A) to 1(E) show an embodiment (sectional view) of the present invention.

2(A) to 2(D) show an embodiment (sectional view) of the prior art.

3(A) to 3(F) show an embodiment (sectional view) of the present invention.

4(A) to 4(C) show an embodiment of the present invention (top plan view).

5(A) to 5(E) show an embodiment (sectional view) of the present invention.

6(A) to 6(F) show an embodiment (sectional view) of the present invention.

7(A) to 7(E) show an embodiment (sectional view) of the present invention.

8(A) to 8(F) show an embodiment (sectional view) of the present invention.

9(A) to 9(C) show an embodiment of the present invention (top plan view).

10(A) to 10(F) show an embodiment (sectional view) of the present invention.

Detailed ways

Example 1

Fig. 1 shows the process of this embodiment. This embodiment relates to a manufacturing process for manufacturing a thin film transistor on an insulating substrate. The substrate 101 shown is formed of glass; the substrate is formed using non-alkali glass such as Coning 7059 or quartz, or the like. In this embodiment, the Coning7509 substrate is used in consideration of cost. A silicon oxide film 102 is deposited on the substrate as an underlying oxide film. The silicon oxide film is deposited using sputtering or chemical vapor deposition (CVD) techniques. In this embodiment, the deposition of the film is performed by plasma CVD using tetraethoxysilane (TEOS) and oxygen as source gases. The substrate is heated to a temperature of 200 to 400°C. Deposit a silicon oxide base film to a thickness of 500 to 2000 Angstroms.

Next, an amorphous silicon film is deposited, and an island pattern is formed. Such amorphous silicon films are typically deposited using plasma CVD and low pressure CVD techniques. In this embodiment, an amorphous silicon film is deposited by plasma CVD using monosilane (SiH ₄ ) as a source gas. An amorphous silicon film is deposited to a thickness of 200 to 700 angstroms. The film was irradiated with laser light (KrF laser with a wavelength of 248 nm and a pulse width of 20 nsec). Before irradiating laser light, the substrate is heated in a vacuum at 300 to 550°C for 0.1 to 3 hours to extract hydrogen gas contained in the amorphous silicon film. The energy density of the laser is 250 to 450 mJ/cm ² . During laser irradiation, the substrate was kept at a temperature of 250 to 550°C. As a result, the amorphous silicon film is crystallized to form the crystalline silicon film 103 .

Next, a silicon oxide film 104 is formed as a gate insulating film to a thickness of 800 to 1200 angstroms. In this embodiment, the same method as that used for forming the silicon oxide base film 102 is used to deposit this film. A mask material is then applied, typically formed from an organic material such as polyimide, a conductive material such as aluminum, tantalum, titanium, or other metal, a semiconductor such as silicon, or a conductive Metal nitrides, eg, tantalum nitride, or titanium nitride. In this embodiment, photosensitive polyimide is used to form the mask material 105 with a thickness of 2000 to 10000 angstroms (FIG. 1(A)).

Then, boron (B) or phosphorus (P) ions are doped by plasma doping technology to form the doped region 106 . Generally, the acceleration energy of ions is set to match the thickness of the gate insulating film 104 . Typically, for a 1000 Angstrom thick gate insulating film, suitable acceleration energies are 50 to 65 KeV for boron and 60 to 80 KeV for phosphorus. A dose of 2 x 10 ¹⁴ cm ^-2 to 6 x 10 ¹⁵ cm ^-2 was found to be suitable, and it was also found that with lower doses, higher reliability devices could be obtained. The cross-section of the doped region shown in the figure is only to illustrate the effect, and it should be known that due to ion scattering and the like, the region actually extends more or less outside the cross-section shown. (Fig. 1(B)).

After the doping is completed, the polyimide mask material 105 is etched away. The etching is performed in an oxygen plasma atmosphere. As a result, as shown in FIG. 1(C), the figure shows the doped regions 106 and the active regions on both sides thereof. Under this condition, laser irradiation was performed in order to activate the doped region. The laser used is KrF excimer laser (wavelength 248 nm, pulse width 20 nsec), and the energy density of the laser is 250 to 450 mJ/cm ² . During laser irradiation, the substrate is kept at a temperature of 250 to 550°C for more efficient activation. Generally, for the phosphorus-doped region, the substrate temperature is 250°C, the laser energy is 330mJ/cm ² , and the sheet resistance is 500 to 1000Ω/□ at a dose of 1×10 ¹⁵ cm ^-2 . In addition, in this embodiment, since the boundary between the doped region and the active region is also irradiated with laser light, the manufacturing problem in the prior art that lowers reliability due to changes in the boundary portion is greatly alleviated.

Thereafter, patterning is performed to form a tantalum gate electrode (wiring) with a width of 0.2 μm narrower than the mask material 105, and then anodic oxidation is performed by applying current to the gate electrode to form an anodic oxide layer with a thickness of 1000 to 2500 angstroms. For anodic oxidation, the substrate is immersed in an ethylene glycol solution containing 1-5% citric acid, and all grid electrodes are connected to form a positive electrode, while platinum is used to form a negative electrode; Increase the applied voltage at a rate of 5 volts. Therefore, the formed gate electrode 107 is obviously in an offset state relative to the doped region. The anodic oxide layer fabricated on the gate electrode not only determines the amount of offset of the thin film transistor but also prevents short-circuiting with the upper wiring; therefore, the only requirement for the oxide layer is to have a thickness that can achieve this purpose, according to In specific cases, the formation of the above-mentioned anodized layer may not be necessary (FIG. 1(D)).

Finally, using, for example, TEOS as a raw material gas, a silicon oxide film 108 as an interlayer insulator is formed by plasma CVD with a thickness of 2000 to 1000 angstroms, and the film is opened into a pattern of openings through which each electrode is formed. 109, each electrode 109 is made of a multilayer metal film or other materials, for example, a multilayer film composed of tantalum nitride with a thickness of 200 angstroms and aluminum with a thickness of 5000 angstroms, and the above electrodes are used to connect the doped regions, The manufacture of the thin film transistor is thus completed (FIG. 1(E)).

Example 2

3 and 4 show the process of this embodiment. Fig. 3 is a cross-sectional view taken along the dashed-dotted line in Fig. 4 (top plan view). First, a silicon oxide underlayer film is formed on the substrate (Coning 7059) 301, and then an amorphous silicon film with a thickness of 1000 to 1500 angstroms is formed. Then, annealing is performed at 600° C. for 24 to 48 hours in a nitrogen or argon atmosphere to crystallize the patterned amorphous silicon. Thus, island-shaped crystal silicon 302 is formed. Further, a silicon oxide film 303 is deposited as a gate insulating film to a thickness of 1000 angstroms, and tantalum wirings (5000 angstroms thick) 304, 305 and 306 are formed thereon (FIG. 3(A)).

Next, a current is applied to the above-mentioned wirings 304 to 306, and on their surfaces, first anodized layers 307, 308 and 309 are formed to a thickness of 2000 to 2500 angstroms. Impurities are doped into the silicon film 302 by plasma doping using the above-mentioned processed wiring as a mask to form a doped region 310 (FIGS. 3(B) and 4(A)).

Next, the above-mentioned treated tantalum wiring and anodized layer are removed to expose the surface of the active region. The KrF excimer is irradiated with laser light under this condition to be activated (FIG. 3(C)).

Thereafter, the same patterns (wiring lines 311, 312, 313) as the aforementioned wiring lines 304 to 306 are formed using tantalum. Only at the portion of the wiring 313 where a contact hole is to be formed, a polyimide film 314 is formed to a thickness of 1 to 5 [mu]m. It is best to use photosensitive polyimide material for polyimide, because it is easy to carve into patterns (Figures 3(D) and 4(B)).

Under this condition, current is applied to the wirings 311 to 313 to form the second anodized layers 315, 316 and 317 with a thickness of 2000 to 2500 angstroms. However, the portion where polyimide was previously formed is not anodized, but becomes a contact hole 318 (FIG. 3(E)).

Finally, a silicon oxide film 319 is deposited to a thickness of 2000 to 5000 angstroms as an interlayer insulator, and contact holes are opened through this layer. The interlayer insulator deposited over a portion of the wiring 312 (the portion inside the dotted line 322 in FIG. 4(C)) is completely removed to expose the second anodized layer 316 underneath. Each of the wiring/electrodes 320 and 321 composed of a multilayer film of tantalum nitride (thickness 5000 angstroms) and aluminum (thickness 3500 angstroms) was then formed to complete the circuit. Thus, the wiring 321 and the wiring 312 next to the portion 322 constitute capacitance, and are connected to the wiring 313 through the contact hole 323 (FIGS. 3(F) and 4(C)).

Example 3

Fig. 5 shows the process of this embodiment. Fig. 5 is a cross-sectional view showing the sequence of steps in manufacturing a thin film transistor. First, a silicon oxide bottom film 502 is formed on a substrate (Coning 7059) 501, and then an island-shaped amorphous silicon film with a thickness of 1000 to 1500 angstroms is formed. Annealing is then performed at a temperature of 500 to 600° C. for 2 to 48 hours in a nitrogen or argon atmosphere to crystallize the amorphous silicon. Insular crystal silicon 503 is thus formed. In addition, a silicon oxide film 504 is deposited as a gate insulating film to a thickness of 1000 angstroms. Thereafter, by sputtering, an aluminum film containing 1 to 2% silicon (with a thickness of 5000 angstroms) is deposited, and a photoresist is also applied by spin coating. Next, patterning is performed using a known photolithography process. The photoresist 506 formed by this process is used as a mask, and anisotropic etching is performed by reactive ion etching (RIE) to form an aluminum gate electrode/wiring 505 (FIG. 5(A).

Then, the etching method is converted to a conventional plasma method for isotropic etching. As a result, the sides of the aluminum gate electrode/wiring are recessed. By adjusting the etching time, the concave size of the gate electrode is controlled to be 2000 to 3000 Angstroms. Next, by plasma doping, impurities are doped into the silicon film 503 to form a doped region 507 (FIG. 5(B)).

Next, the photoresist 506 is removed to expose the gate electrode/wiring, and under this condition, activation is performed by irradiating the laser light of the KrF excimer. In this irradiation step, the boundary between the doped region and the active region (indicated by X in FIG. 5(C)) is also exposed to laser irradiation (FIG. 5(C)).

Thereafter, the substrate is dipped in an ethylene glycol solution containing tartaric acid to anodize the gate wiring to form an anodized layer 508 of 2000 to 2500 angstroms on the surface thereof.

Finally, a silicon oxide film is deposited as an interlayer insulator 509 with a thickness of 2000 to 5000 angstroms, and then a contact hole is opened to expose the doped region. Then, each wiring/electrode 510 composed of a multilayer film of tantalum nitride (500 angstroms thick) and aluminum (3500 angstroms) was formed, thereby completing the manufacture of the thin film transistor (FIG. 5(E).

Example 4

Fig. 6 shows the process of this embodiment. Form a silicon oxide bottom film on the substrate (Coning7059), and then form an island-shaped amorphous silicon film with a thickness of 1000 to 1500 angstroms. Next, annealing is performed at a temperature of 500 to 600° C. for 2 to 48 hours in a nitrogen or argon atmosphere to crystallize the amorphous silicon. Thus, island-shaped crystal silicon 602 is formed. In addition, a silicon oxide film 603 was deposited as a gate insulating film to a thickness of 1000 angstroms, and aluminum wirings (5000 angstroms in thickness) 604, 605, and 606 were formed (FIG. 6(A)).

Next, on the surfaces of the wirings 604 to 606, anodized layers 607, 608, and 609 are formed, respectively. Next, using the above-mentioned processed wiring as a mask, impurities are doped into the silicon film 602 by plasma doping to form a doped region 610 (FIG. 6(B)).

Next, the aluminum interconnections 604 to 606 are etched away together with the anodic oxide layer to expose the surface of the semiconductor region 602 . Under this condition, activation was performed by irradiating the KrF excimer with laser light (FIG. 6(C)).

Thereafter, aluminum wirings 611, 612, and 613 are formed with the same pattern as the wirings 604 to 606 formed before. Then, a polyimide film is formed to a thickness of 1 to 5 µm, and the wiring 611 is covered with it. For polyimide, it is best to use photosensitive polyimide material because it can be easily patterned (Figure 6(D)).

Under this condition, current is applied to the wirings 611 to 613 to form anodized layers 615 and 616 with a thickness of 2000 to 2500 angstroms. However, the portion of the wire 611 covered with polyimide was not anodized (FIG. 6(E)).

Finally, a silicon oxide film 617 is deposited as an interlayer insulator with a thickness of 2000 to 5000 angstroms, and then a contact hole is opened to expose the doped region 610 . The interlayer insulator deposited over portion 620 of line 613 is completely removed, exposing anodized layer 616. Each of wiring/electrodes 618 and 619 composed of a multilayer film of tantalum nitride (500 angstroms thick) and aluminum (3500 angstroms thick) was formed to complete the circuit. In this case, the wiring 619 next to the portion 620 and the wiring 613 together form a capacitor with the anodized layer 616 as a dielectric (FIG. 6(F)).

Example 5

Fig. 7 shows the process of this embodiment. This embodiment relates to the fabrication of thin film transistors on insulating substrates. The substrate 701 shown is formed of glass; a non-alkali glass such as Coning 7059, or quartz or the like is used to form the substrate. In this embodiment, considering the cost, Coning7059 is used as the substrate. A silicon oxide film 702 is deposited on the substrate as an underlying oxide film. The silicon oxide film can be deposited using sputtering or chemical vapor deposition (CVD) techniques. In this embodiment, the deposition of the above film was performed by plasma CVD using tetraethoxysilane (TEOS) and oxygen as source gases. The substrate is heated to a temperature of 200 to 400°C. A silicon oxide base film is deposited to a thickness of 500 to 2000 Angstroms.

Next, an amorphous silicon film is deposited and an island shape is formed. The aforementioned amorphous silicon film is usually deposited by plasma CVD and low pressure CVD techniques. In this embodiment, amorphous silicon is deposited using monosilane (SiH4) as a source gas. An amorphous silicon film is deposited to a thickness of 200 to 700 angstroms. The film was irradiated with laser light (KrF laser light with a wavelength of 248 nm and a pulse width of 20 nsec). Before irradiating laser light, the substrate is heated in a vacuum at 300 to 500°C for 0.1 to 3 hours to extract hydrogen gas contained in the amorphous silicon. The energy density of the laser is 250 to 450 mJ/cm ² . During the laser irradiation, the substrate is kept at a temperature of 250 to 550°C. As a result, amorphous silicon is crystallized to form a crystalline silicon film 703 .

Next, a silicon oxide film 704 is formed as a gate insulating film to a thickness of 800 to 1200 angstroms. In this embodiment, the deposition of the above-mentioned film is carried out by the same method as that for forming the silicon oxide under film 702 . Then, the gate electrode 705 is formed using an anodizable material such as a metal nitride such as aluminum, tantalum, or titanium, a semiconductor such as silicon, or a conductive material such as tantalum nitride or titanium nitride. Metal. In this embodiment, aluminum is used to form the gate electrode 705 to a thickness of 2000 to 10000 angstroms. At this time, since aluminum is etched with phosphoric acid, aluminum is etched isotropically, resulting in a cross-sectional pattern as shown in the figure (FIG. 7(A)).

Thereafter, a current is applied to the gate wiring 705, and a metal film 706 is formed on the surface thereof to a thickness of 2000 to 2500 angstroms. The metal film is formed by a method similar to a so-called electroplating process. Copper, nickel, chromium, zinc, tin, gold, silver, platinum, palladium, rhodium, etc. can be used as the material of the metal film. For these metals, easily corroded materials are the preferred metals. The present embodiment selects chromium for use. First, chromic anhydride is dissolved in a 0.1%-0.2% sulfuric acid solution to produce a 1-30% solution. Then, the substrate is dipped in the solution, and the gate wires are connected to the cathodes. At the same time platinum is used as the opposite electrode (anode). Under this condition, a current of 100 to 4000 A/ ^m² is applied while maintaining the temperature at 45 to 55°C.

The doped region 707 is formed by doping boron (B) or phosphorus (P) ions after coating the surface of the gate wiring with a chromium film by using the above-mentioned process. Usually, the acceleration energy of the ions is set to match the thickness of the gate insulating film 704; typically, for a gate insulating film with a thickness of 1000 angstroms, the proper acceleration energy is 50 to 65 KeV for boron, and 60 to 80 KeV for phosphorus. A dose of 2 x 10 ¹⁴ cm ^-2 to 6 x 10 ¹⁵ cm ^-2 was found to be suitable, and it was also found that with lower doses, higher reliability devices could be obtained. Since impurities are doped with the chrome film coating formed as described above, an offset occurs between the gate electrode (aluminum) and the doped region. The cross-section of the doped region shown in the figure is only for illustrative effect, and it should be understood that due to ion scattering and the like, the region actually extends more or less outside the cross-section shown. (Fig. 7(B)).

After the doping is completed, only the chromium film formed during the electroplating step is etched away. Dip the substrate in an ethylene glycol solution containing 1-5% tartaric acid, connect the grid wire to the anode, and use the platinum electrode as the cathode; under this condition, apply current to oxidize and dissolve on the grid wire to form chrome coating. Since the chromium dissolved in the solution adheres to the platinum electrode, the regenerated chromium can be reused, thus achieving a closed device that does not release harmful chromium to the outside.

When the chromium in the gate wiring is completely removed, then the aluminum in the gate electrode is subjected to anodization, but the anodization can be suppressed by limiting the applied voltage. For example, anodic oxidation of aluminum rarely occurs when the applied voltage is limited to 10 volts or less.

In this way, only the chrome coating is etched away to expose the surface of the wiring. As a result, as shown in FIG. 7(C), a boundary (indicated by x) between the doped region 707 and the active region located at the side of the doped region is displayed. Under this condition, laser irradiation is performed to activate the doped region. The laser used is KrF excimer laser (wavelength 248nm, pulse width 20nsec), and the energy density of the laser is 250-450mJ/cm ² . During laser irradiation, the substrate is kept at 250 to 550°C for more efficient activation. Typically, for the phosphorus-doped region, with a dose of 1×10 ¹⁵ cm ^-2 , a substrate temperature of 250°C, and a laser energy of 300mJ/cm ² , a sheet resistance of 500-1000Ω/□ can be obtained. In addition, in this embodiment, since the boundary between the doped region and the active region is also exposed to laser radiation, the manufacturing problem of lower reliability due to the deterioration of the boundary portion in the prior art is greatly alleviated. up. In this process step, since the laser is directly irradiated to the exposed surface of the gate wiring, it is hoped that the surface of the wiring can fully reflect the laser or provide a very large thermal resistance for the wiring itself. In case a very large surface reflection cannot be provided, some precautions are required, for example, a heat-resistant material is placed on the upper surface (Fig. 7(C)).

Thereafter, the gate electrode is anodized to form an anodized layer 708 on its surface with a thickness of 1500 to 2500 angstroms. In order to achieve anodic oxidation, the substrate is immersed in an ethylene glycol solution containing 1-5% citric acid, and all grid electrodes are connected to form a positive electrode, while platinum is used to form a negative electrode; Volts increase the applied voltage at a rate. Since the anodic oxidation process makes the conductive surface concave, the anodic oxide layer 708 not only determines the offset of the thin film transistor, but also prevents short circuits with the upper layer wiring. Therefore, the oxidation is only required to have an acceptable thickness, and it may not be necessary to form the above-mentioned anodized layer (FIG. 7(D)) depending on the circumstances.

Finally, by plasma CVD, for example, using TEOS as a raw material gas, a silicon oxide film 709 is formed as an interlayer insulator with a thickness of 2000 to 1000 angstroms, and the film is opened into a window pattern to pass through the window to form a connection doped region. Electrode 710, this electrode is made of multilayer metal film or other materials, for example, is made of the multilayer film that the titanium nitride of 200 angstrom thickness and the aluminum of 5000 angstrom thickness are formed, thus finished the manufacture of thin film transistor (Fig. 7 (E) ).

Example 6

8 and 9 show the process carried out according to this embodiment. Fig. 8 is a sectional view taken along the dashed line in Fig. 9 (top view). Firstly, a silicon oxide base film is formed on the substrate (Coning7059) 801, and then amorphous silicon is formed with a thickness of 1000 to 1500 angstroms. Then, it is annealed at 600° C. for 24 to 48 hours in a nitrogen or argon atmosphere to crystallize the amorphous silicon. Thus, an island-shaped crystalline silicon 802 is formed. Further, a silicon oxide film 803 was deposited as a gate insulating film to a thickness of 1000 angstroms, and aluminum wirings (5000 angstroms in thickness) 804, 805 and 806 were formed thereon (FIG. 8(A)).

Then, by immersing the substrate in an electrolytic solution, current is applied to these wirings 804 to 806 to form chromium coatings 807, 808 and 809 with a thickness of 2000 to 2500 angstroms on their relevant surfaces. Using this processed wiring as a mask, impurities are doped into the silicon film 802 by plasma doping to form a doped region 810 (FIGS. 8(B) and 9(A)).

Next, only the chrome coatings 807 to 809 were etched away to expose the surface of the wiring, and under this condition, activation was performed by irradiating KrF excimer laser light (FIG. 8(C)).

Thereafter, a polyimide film 811 is formed to a thickness of 1 to 5 [mu]m only at the portion of the wiring 806 where a contact hole is to be formed. For polyimide, photosensitive polyimide material is preferred because it can be easily patterned (Figures 8(D) and 9(B)).

Under this condition, the substrate was immersed in an electrolytic solution, and a current was applied to the wirings 804 to 806 to form anodized layers 812, 813 and 814 with a thickness of 2000 to 2500 angstroms. However, the portion where polyimide was previously formed is not anodized, and becomes a contact hole 815 (FIG. 8(E)).

Finally, a silicon oxide film 816 is deposited to a thickness of 2000 to 5000 angstroms as an interlayer insulator, through which contact holes are opened. The interlayer insulator deposited over the portion of the wiring 805 (the portion within the dotted line in FIG. 9(C)) is completely removed, exposing the anodized layer 813 below. Then, each of wiring electrodes 817 and 818 composed of a multilayer film composed of tantalum nitride (thickness: 500 angstroms) and aluminum (3500 angstroms) was formed to complete the circuit. In this case, the wiring 818 next to the portion 819 forms a capacitor with the wiring 805, and is connected to the wiring 806 through the contact hole 820 (FIGS. 8(F) and 9(C)).

Example 7

Fig. 10 shows the process according to this embodiment. Form a silicon oxide bottom film on the substrate (Coning7059), and then form amorphous silicon with a thickness of 1000 to 1500 angstroms. Next, annealing is performed at 600° C. for 24 to 48 hours in a nitrogen or argon atmosphere to crystallize the amorphous silicon. Thus, island-shaped crystal silicon 902 is formed. In addition, a silicon oxide film 903 was deposited as a gate insulating film to a thickness of 1000 angstroms, and tantalum wirings (5000 angstroms in thickness) 904, 905, and 906 were formed (FIG. 10(A)).

Then, chrome plating layers 907, 908 and 909 are formed on these wirings by electroplating to a thickness of 500 to 1500 angstroms. Impurities are doped into the silicon film 902 by plasma doping using the processed wiring as a mask, thereby forming a doped region 910 (FIG. 10(B)).

Next, only the chromium plating films 907 to 909 are removed so as to expose the boundary between the doped region and the active region located on the side of the doped region. Under this condition, activation was performed by irradiating KrF excimer laser light (FIG. 10(C)).

Thereafter, a polyimide film 911 is formed to a thickness of 1 to 5 μm for covering the wiring 904 . For polyimide, photosensitive polyimide material is the preferred material because it can be easily patterned (Fig. 10(D)).

Under this condition, a current was applied to the wirings 904 to 906 immersed in the electrolytic solution to form anodized films 912 and 913 with a thickness of 2000 to 2500 angstroms. Then, the wiring portion covered with polyimide was not anodized (FIG. 10(E)).

Finally, an oxide film 914 is deposited as an interlayer insulator with a thickness of 2000 to 5000 Å, and a contact hole is opened to expose the doped region 910 . The interlayer insulator deposited over the portion of the wiring 906 is completely removed so that the anodized layer 913 is exposed. Then, respective wiring/electrodes 915 and 916 composed of a multilayer film of titanium nitride (thickness: 500 angstroms) and aluminum (thickness: 3500 angstroms) were formed to complete the circuit. In this case, the wire 916 next to the portion 917 and the wire 906 together form a capacitor, and the anodized layer 913 acts as a dielectric (FIG. 5(F)).

Thus, the present invention effectively enhances the reliability of MIS semiconductor devices manufactured by low-temperature processes as MOS transistors and thin film transistors. In a special example, the device is stored for more than 10 hours, and its state is that the source is grounded. Apply a voltage of 20V or more, or -20V or less, to the drain or gate or both. No significant effect on the characteristics of the transistor was observed.

The description of the embodiments focuses on thin film transistors, but it should be recognized that other MIS semiconductor devices fabricated on single crystal semiconductor substrates can also obtain the effects of the present invention. Furthermore, in addition to the use of silicon in the above embodiments, semiconductor materials such as silicon-germanium alloy, silicon carbide, germanium, cadmium selenide, cadmium sulfide, gallium arsenide, etc. may also be used in order to obtain the same effects as above.

Therefore, the present invention provides convenience for industrial application.

Claims (16)

1. method of making semiconductor device comprises:

On insulating surface, form semiconductor island;

On described semiconductor island, form gate insulating film;

On described gate insulating film, form conducting film;

Make pattern on described conducting film, to form gate electrode, wherein said gate electrode top is narrow and the bottom is wide;

Metallizing film on the surface of described gate electrode;

Utilize described gate electrode and described metal film foreign ion to be introduced in the each several part of described semiconductor island as mask, to form each impurity range that is inserted with channel formation region therebetween in described semiconductor island, wherein said metal film has the side surface of inclination;

After introducing described impurity, remove described metal film from the surface of described gate electrode; And

After removing described metal film, when covering described channel region with gate electrode, with described each impurity range of rayed to activate this impurity range.

2. the method for claim 1 is characterized in that, makes described semiconductor island crystallization with laser radiation.

3. the method for claim 1 is characterized in that, described impurity is selected from the one group of material that is made of boron and phosphorus.

4. the method for claim 1 is characterized in that, described conducting film comprises the material that is selected from in next group: aluminium, tantalum, titanium, silicon, titanium nitride and tantalum nitride.

5. the method for claim 1 is characterized in that, makes pattern in the isotropic etching mode on described conducting film.

6. method of making the MIS semiconductor device may further comprise the steps:

On the gate insulating film on the semiconductor layer that forms on the insulating surface, form mask;

According to described mask impurity is optionally introduced in the described semiconductor layer, to form impurity range;

After forming described impurity range, remove described mask;

After removing described mask, on the part of the described semiconductor layer between the described impurity range, forming gate electrode; And between described part and described gate electrode, be provided with dielectric film,

The width of wherein said mask on from a described impurity range to the direction of another described impurity range is greater than the width of described gate electrode.

7. want 6 described methods as right, it is characterized in that, described gate electrode comprises a kind of material that is selected from in next group: aluminium, titanium, tantalum, silicon, tungsten and molybdenum.

8. method as claimed in claim 6 is characterized in that, and is further comprising the steps of: anodic oxidation is carried out on the surface to described gate electrode.

9. method as claimed in claim 6 is characterized in that described semiconductor layer comprises crystalline silicon.

10. method of making the MIS semiconductor device may further comprise the steps:

On the gate insulating film on the semiconductor layer that forms on the insulating surface, form mask;

According to described mask impurity is optionally introduced in the described semiconductor layer, to form impurity range;

After forming described impurity range, remove described mask;

After removing described mask, on the part of the described semiconductor layer between the described impurity range, forming the gate electrode that contains molybdenum; And between described part and described gate electrode, be provided with dielectric film,

The width of wherein said mask on from a described impurity range to the direction of another described impurity range is greater than the width of described gate electrode.

11. method as claimed in claim 10 is characterized in that, described semiconductor layer comprises crystalline silicon.

12. a method of making the MIS semiconductor device may further comprise the steps:

On the gate insulating film on the semiconductor layer that forms on the insulating surface, form mask;

According to described mask impurity is optionally introduced in the described semiconductor layer, to form impurity range;

After forming described impurity range, remove described mask;

After removing described mask, on the part of the described semiconductor layer between the described impurity range, forming gate electrode; And between described part and described gate electrode, be provided with dielectric film;

After removing described mask, to described semiconductor layer irradiating laser, with the degree of crystallinity of the described at least impurity range of increase,

The width of wherein said mask on from a described impurity range to the direction of another described impurity range is greater than the width of described gate electrode.

13. method as claimed in claim 12 is characterized in that, described gate electrode comprises a kind of material that is selected from in next group: aluminium, titanium, tantalum, silicon, tungsten and molybdenum.

14. method as claimed in claim 12 is characterized in that, described semiconductor layer comprises crystalline silicon.

15. a method of making the MIS semiconductor device may further comprise the steps:

On the gate insulating film on the semiconductor layer that forms on the insulating surface, form mask;

According to described mask impurity is optionally introduced in the described semiconductor layer, to form impurity range;

After forming described impurity range, remove described mask;

After removing described mask, on the part of the described semiconductor layer between the described impurity range, forming the gate electrode that contains molybdenum; And between described part and described gate electrode, be provided with dielectric film;

After removing described mask, to described semiconductor layer irradiating laser, with the degree of crystallinity of the described at least impurity range of increase,

The width of wherein said mask on from a described impurity range to the direction of another described impurity range is greater than the width of described gate electrode.

16. method as claimed in claim 15 is characterized in that, described semiconductor layer comprises crystalline silicon.

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