JP3352973B2 - Method for manufacturing MIS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a metal (M) -insulator (I) -semiconductor (S) type semiconductor device, so-called MIS.
The present invention relates to a method for manufacturing a semiconductor device (also referred to as an insulating gate semiconductor device). MIS type semiconductor devices include, for example, M
OS transistors, thin film transistors, and the like are included.

[0002]

2. Description of the Related Art Conventionally, MIS type semiconductor devices have been manufactured using a self-alignment method (self-alignment method). According to this method, a gate wiring (electrode) is formed on a semiconductor substrate or a semiconductor film via a gate insulating film, and impurities are introduced into the semiconductor substrate or the semiconductor film using the gate wiring as a mask. As a means for introducing impurities, a thermal diffusion method, an ion implantation method, a plasma doping method, or a laser doping method is used. By such means, the end of the gate electrode almost coincides with the end of the impurity region (source, drain), and the gate electrode and the impurity region overlap with each other (a cause of parasitic capacitance), The offset state in which the impurity region is separated (the cause of the decrease in the effective mobility) can be eliminated.

However, in a conventional process, an impurity region and
The spatial variation of the carrier concentration in the active region (channel forming region) adjacent to and below the gate electrode is so large that an extremely large electric field is generated. In particular, the leakage current when a reverse bias voltage is applied to the gate electrode (OFF current) increases.

The present inventors have found that this problem can be improved by slightly offsetting the gate electrode and the impurity region, and furthermore, to realize this offset state, Was formed using an anodically oxidizable material, and as a result of the anodic oxidation, an impurity state was introduced using the anodic oxide film as a mask, thereby obtaining an offset state of 300 nm or less with good reproducibility.

Further, in a method of introducing impurities by irradiating a semiconductor substrate or a semiconductor film with high-speed ions such as an ion implantation method or a plasma doping method, the crystallinity of a portion of the semiconductor substrate or the semiconductor film into which ions have penetrated is reduced. To be impaired, it was necessary to improve the crystallinity (activation). Conventionally, the crystallinity was thermally improved mainly at a temperature of 600 ° C. or higher. However, in recent years, there has been a tendency to lower the temperature of the process, and the present inventors have developed a laser or intense light equivalent thereto. It was also shown that activation can be achieved by irradiation and that the mass productivity is excellent.

FIG. 2 shows a process for manufacturing a thin film transistor based on the above-described concept. First, a base insulating film 202 is deposited over a substrate 201, an island-shaped crystalline semiconductor region 203 is formed, and an insulating film 204 functioning as a gate insulating film is formed to cover the island-shaped crystalline semiconductor region 203. Then, a gate wiring 205 is formed using a material capable of being anodized.
(Fig. 2 (A))

Next, the gate wiring is anodically oxidized to a thickness of 300 nm or less, preferably 250 nm, on the surface of the gate wiring.
The following anodic oxide 206 is formed. Then, using the anodic oxide as a mask, impurities (for example,
Irradiation with phosphorus (P) is performed to form an impurity region 207.
(FIG. 2 (B))

After that, the region into which the impurities are introduced is activated by irradiating strong light such as laser light from the upper surface. (Fig. 2 (C))

Finally, an interlayer insulator 208 is deposited, a contact hole is formed in the impurity region, an electrode 209 connected to the contact hole is formed, and a thin film transistor is completed.
(FIG. 2 (D))

[0010]

However, in the method described above, the boundary between the impurity region and the active region (the semiconductor region immediately below the gate electrode and sandwiched between the impurity regions) (see FIG. 2C). , X) are unstable, and a problem such as an increase in leakage current occurs during a long-time use, and it has been clarified that reliability is reduced. That is, as apparent from the process, the active region is substantially
The crystallinity does not change from the beginning. On the other hand, the impurity region adjacent to the active region initially has the same crystallinity as the active region, but the crystallinity is destroyed in the process of introducing the impurity. The impurity region is recovered by a subsequent laser irradiation step,
It is difficult to reproduce the same state as the original crystallinity, and it is clear that especially in the impurity regions, which are in contact with the active region, are likely to be shadowed by laser irradiation, and sufficient activation can not be performed became. That is, the crystallinity of the impurity region and the active region is discontinuous, and thus a trap level or the like is likely to occur. In particular, when a method of irradiating high-speed ions is employed as a method of introducing impurities, the impurity ions are scattered below the gate electrode portion by scattering to destroy the crystallinity of the portion. The region under such a gate electrode portion cannot be activated by a laser or the like due to the shadow of the gate electrode portion.

One method of solving this problem is to perform irradiation by irradiating light such as a laser from the back surface to activate the device. In this method, since the gate wiring does not become a shadow, the boundary between the active region and the impurity region is sufficiently activated. However, in this case, the substrate material needs to transmit light, and it cannot be used naturally when a silicon wafer or the like is used. Further, since it is difficult for many glass substrates to transmit ultraviolet light of 300 nm or less, for example, a KrF excimer laser (wavelength: 248 nm) excellent in mass productivity cannot be used.

The present invention has been made in view of such a problem, and achieves a highly reliable MIS type semiconductor device, for example, a MOS transistor or a MOS transistor by achieving continuity of crystallinity between an active region and an impurity region. It is an object to obtain a thin film transistor.

[0013]

SUMMARY OF THE INVENTION According to the present invention, when irradiating light energy from a powerful light source such as a laser or a flash lamp to an impurity region from an upper surface to activate the impurity region, not only the impurity region but also the impurity region is activated. Part of the adjacent active region, particularly the boundary between the impurity region and the active region, is also irradiated with light energy, and in order to achieve such a purpose, it is necessary to remove a part of the material constituting the gate electrode portion. Features.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the structure of the present invention, an insulating film functioning as a gate insulating film is formed on a crystalline semiconductor substrate or a semiconductor film, and then a gate wiring (gate electrode) is formed with an appropriate material. Using this as an electrode, a step of electrochemically depositing a film of a conductive material or the like on the surface by an electrochemical action (for example, electroplating), and a gate electrode portion (gate) treated in this manner. A step of introducing impurities into the semiconductor substrate or the semiconductor film in a self-aligned manner using the electrode and a conductive material deposited on the surface as a mask, and removing part or all of the previously deposited material, Providing a state in which light energy can be irradiated to a boundary between the impurity region and the active region, and irradiating light energy in this state to perform activation.

If necessary, the gate electrode is made of a material that can be anodically oxidized, irradiated with light energy, and then anodized to cover the surface with anodic oxide having high insulating properties. It goes without saying that a structure may be provided to reduce the capacitive coupling with the upper wiring by providing an object or the like.

The anodizable materials preferably used in the present invention are aluminum, titanium, tantalum, silicon, tungsten and molybdenum. A single or alloy of these materials may be used as the gate electrode in a single-layer or multilayer structure. It goes without saying that trace amounts of other elements may be added to these materials.
Further, as the anodic oxidation method, a wet method in which oxidation is performed in an electrolytic solution is generally used, but it goes without saying that a known plasma anodic oxidation method (oxidation in a reduced-pressure plasma atmosphere) may be used. Nor. Further, it goes without saying that the wiring may be oxidized using not only the anodic oxidation but also another appropriate oxidizing method.

The source of light energy used in the present invention is a KrF laser (wavelength: 248 nm), a XeCl laser (308 nm), Ar
F laser (193nm), XeF laser (353n)
m) and other Nd: YAG lasers (1064 nm) and their second, third, and fourth harmonics;
Coherent light sources such as a carbon dioxide laser, an argon ion laser, and a copper vapor laser, and non-coherent light sources such as a xenon flash lamp and a krypton clamp are suitable.

When viewed from above, the MIS type semiconductor device obtained by such a process has a junction of an impurity region (source and drain) and a gate electrode portion (gate electrode or anodic oxide attached thereto). ) Have substantially the same shape (similar shape), and furthermore, the gate electrode (boundary to the conducting surface; excluding accompanying materials such as anodic oxide) and the impurity region are in an offset state. The feature is that it is.

When there is no oxide such as an anodic oxide, there is no oxide around the gate electrode, and the impurity region and the gate electrode are in an offset state. 1 to 0.5 μm is preferred.

In the present invention, for example, the thickness of an oxide such as an anodic oxide can be changed even on the same substrate by adjusting the applied voltage for each wiring. In this case, the thickness of the oxide of the gate electrode portion and the thickness of the oxide of the capacitor (or the portion where the wiring intersects) may be independently set so as to be suitable for each purpose. .

[0021]

[Embodiment 1] FIG. 1 shows this embodiment. In this embodiment, a thin film transistor is formed on an insulating substrate. The substrate 101 is a glass substrate, for example, a non-alkali glass substrate such as Corning 7059, a quartz substrate, or the like can be used. Considering the cost, here Corning 70
59 substrates were used. A silicon oxide film 102 was deposited thereon as an underlying oxide film. As a method for depositing the silicon oxide film, for example, a sputtering method or a chemical vapor deposition method (CVD method) can be used. Here, a film was formed by a plasma CVD method using TEOS (tetraethoxysilane) and oxygen as material gases. Substrate temperature is 200 to 400
° C. The thickness of the underlying silicon oxide film is 500 to 20
00 mm .

Next, an amorphous silicon film was deposited and patterned into an island shape. As a method of depositing an amorphous silicon film, a plasma CVD method or a low pressure CV
Method D is used. Here, monosilane (SiH ₄ )
Was used as a material gas to deposit an amorphous silicon film by a plasma CVD method. The thickness of the amorphous silicon film was 200 to 700 Å. This was irradiated with a laser beam (KrF laser, wavelength 248 nm, pulse width 20 nsec). Before the laser irradiation, the substrate was heated to 300 to 550 ° C. for 0.1 to 3 hours in a vacuum to release hydrogen contained in the amorphous silicon film. Laser energy density is 250-450
mJ / cm ² . At the time of laser irradiation, the substrate was heated to 250 to 550 ° C. As a result, the amorphous silicon film was crystallized to become a crystalline silicon film 103.

[0023] Then, to form a thickness of 800 to 1200 Å silicon oxide film 104 which functions as a gate insulating film. Here, the same manufacturing method as that of the base silicon oxide film 102 was employed. Further, the gate electrode 105 was formed using an anodizable material, for example, a metal such as aluminum, tantalum, and titanium, a semiconductor such as silicon, and a conductive metal nitride such as tantalum nitride and titanium nitride. Here, using the aluminum, its thickness was 2000 to 10000 Å. At this time, since aluminum was patterned by phosphoric acid, the aluminum film was isotropically etched, resulting in a cross-sectional shape as shown in the figure. (Fig. 1 (A))

Next, through the current to the gate wiring 105, a metal film 1 having a thickness of 2000-2500 Å on the surface thereof
06 was deposited. The formation of this metal film uses the same means as the so-called electroplating process, and the material of the metal film includes copper, nickel, chromium, zinc, tin, gold,
Silver, platinum, palladium, rhodium and the like can be used, and among them, those which can be easily etched are preferable. In this embodiment, chromium is used. First, add chromic anhydride to 0.1
Dissolve in ~ 2% sulfuric acid solution to make a 1-30% solution. Then, the substrate was immersed in this solution, and the gate wiring was connected to the cathode. On the other hand, a platinum electrode was used as a counter electrode (anode), and a current of 100 to 4000 A / m ² was passed at 45 to 55 ° C.

After the surface of the gate wiring was covered with a chromium film by the above steps, boron (B) or phosphorus (P) ions were irradiated to form impurity regions 107. The acceleration energy of the ions is changed depending on the thickness of the gate insulating film 104.
000 in the case of Å, in boron 50～65KeV, the phosphorus 60~80keV was suitable. Also, the dose amount is suitably 2 × 10 ¹⁴ cm ^{−2 to} 6 × 10 ¹⁵ cm ⁻² ,
It was found that the lower the dose, the higher the reliability of the device. As a result of the introduction of the impurities in the presence of the chromium film, the gate electrode (aluminum) and the impurity region were in an offset state. It should be noted that the range of the impurity region shown in the drawing is a nominal one, and it goes without saying that there is actually a wraparound due to ion scattering or the like. (FIG. 1 (B))

After the impurity doping was completed, only the chromium film formed in the previous plating step was etched. The substrate is immersed in an ethylene glycol solution of 1-5% tartaric acid, the gate wiring is connected to the anode, a platinum electrode is used as the cathode, and a current is passed through the chromium coating applied to the surface of the gate wiring. Was oxidized and dissolved. Since the chromium dissolved in the solution is deposited on the platinum electrode of the cathode, by reusing it, a closed system that does not discharge harmful chromium to the outside can be made. When all the chromium on the gate wiring is removed, the aluminum of the gate wiring is then anodized, but this can be suppressed by limiting the voltage. For example, when the applied voltage is set to 10 V or less, anodic oxidation of aluminum hardly proceeds.

Thus, only the chromium film was etched to expose the surface of the wiring. As a result, as shown in FIG. 1C, a boundary (designated by X) between the impurity region 107 and the active region sandwiched between the impurity regions 107 appeared. In such a state, the impurity region was activated by laser irradiation. The laser used is a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec), and the energy density of the laser is 250 to 450 m.
J / cm ² . Further, at the time of laser irradiation, the substrate could be more effectively activated by heating the substrate to 250 to 550 ° C. Typically, a sheet doped with phosphorus and having a dose of 1 × 10 ¹⁵ cm ⁻² , a substrate temperature of 250 ° C., and a laser energy of 300 mJ / cm ² has a sheet resistance of 500 to 1000 Ω / □. Further, in this embodiment, since the boundary between the impurity region and the active region (designated as x) is also irradiated by the laser, the decrease in reliability due to the deterioration of the boundary portion, which is a problem in the conventional manufacturing process, is significantly reduced. In addition,
In this step, since the exposed gate wiring is irradiated with laser light, it is desired that the wiring surface reflect the laser light sufficiently or that the wiring itself has sufficient heat resistance. When the reflectance of the surface is not good, it is desired to take measures such as providing a heat-resistant material on the upper surface. (Figure 1
(C))

[0028] Then, a gate electrode is anodized to form an anodic oxide 108 having a thickness of 1,500 to 2,500 Å on the surface thereof. In anodization, the substrate is immersed in an ethylene glycol solution of 1 to 5% citric acid, all the gate wirings are integrated, and this is used as a positive electrode, while platinum is used as a negative electrode, and the applied voltage is 1 to 5 V /. This was done by boosting in minutes. The anodized oxide 108 not only determines the magnitude of the offset of the thin film transistor due to the receding of the conductor surface in the anodizing step, but also has an effect of preventing a short circuit with the upper wiring. An appropriate thickness may be selected, and in some cases, such an anodic oxide may not be formed. (Fig. 1 (D))

Finally, a silicon oxide film 109 is used as an interlayer insulator.
Was formed by a thickness of 2,000 to Å, for example, a plasma CVD method using TEOS as a material gas, the material of the metal or the like pierced the contact hole to a thickness of, for instance, 200
The electrode 110 formed of a multilayer film of titanium nitride of Å and aluminum of 5,000 と was connected to the impurity region to complete a thin film transistor. (FIG. 1 (E))

Embodiment 2 FIGS. 3 and 4 show this embodiment. FIG. 3 is a sectional view taken along a dashed line in FIG. 4 (top view). First, the substrate to form a silicon oxide film of the base on the (Corning 7059) 301, further, and the amorphous silicon film to a thickness of 1000 to 1500 Å is formed. And
24 hours at 600 ° C in nitrogen or argon atmosphere
By annealing for ~ 48 hours, the amorphous silicon was crystallized. Thus, crystalline island-shaped silicon 302 was formed. Further, a silicon oxide film 303 having a thickness of 1000 機能 functioning as a gate insulating film is deposited,
Aluminum wiring (thickness 5000 Å ) 304, 30
5, 306 were formed. (FIG. 3 (A))

Then, the substrate is immersed in an electrolytic solution, an electric current is passed through these wirings 304 to 306, and a thickness of 2
000~2500 Å of chrome coating 307,308,30
9 was formed. Then, an impurity was introduced into the silicon film 302 by a plasma doping method using the wiring subjected to such processing as a mask to form an impurity region 310. (FIG. 3 (B) and FIG. 4 (A))

Next, only the chromium films 307 to 309 are etched to expose the surface of the wiring.
Activation was performed by irradiating an excimer laser beam. (FIG. 3 (C))

Thereafter, a polyimide coating 311 having a thickness of 1 to 5 μm was provided only on a portion of the wiring 306 where a contact hole was to be formed. As the polyimide, a photosensitive polyimide is easily used because of its ease of patterning. (FIG. 3
(D) and FIG. 4 (B))

Then, in this state, the substrate is immersed in an electrolytic solution, a current is passed through the wirings 304 to 306, and a thickness of 2000 to 2000 is applied.
2500 to form an anodic oxide 312, 313, 314 of Å. However, the portion where the polyimide is provided first is not anodized, and the contact hole 315 remains. (FIG. 3
(E))

Finally, a thickness of 2000 to 5 is used as an interlayer insulator.
000 is deposited a silicon oxide film 316 Å, to form contact holes. Further, in a part of the wiring 305 (a part 319 surrounded by a dotted line in FIG. 4C), all the interlayer insulator was removed to expose the anodic oxide 313. Then, tantalum nitride (thickness 500 Å ) and aluminum (thickness 3500)
Ii ) Wiring / electrodes 317 and 318 using the multilayer film were formed to complete the circuit. At this time, the wiring 318 is 319
Constitutes a capacitance with the wiring 305, and is further connected to the wiring 306 by a contact 320. (FIG. 3
(F) and FIG. 4 (C))

Embodiment 3 FIG. 5 shows this embodiment. A base silicon oxide film is formed on a substrate (Corning 7059) 501, and an amorphous silicon film is
00-1500 was Å formed. The amorphous silicon was crystallized by annealing at 600 ° C. for 24 to 48 hours in a nitrogen or argon atmosphere. Thus, crystalline island-shaped silicon 502 was formed. Furthermore, a thickness of 10 serving as a gate insulating film
A silicon oxide film 503 of 00 ° was deposited to form tantalum wirings (thickness 5000 ° ) 504, 505, and 506. (FIG. 5 (A))

[0037] Then, the thickness by electrolytic plating on the wiring surfaces 500 to 1500 Å of chrome coating 507 and 508,
509 was formed. Then, using the wiring thus processed as a mask, an impurity was introduced into the silicon film 502 by a plasma doping method to form an impurity region 510. (FIG. 5 (B))

Next, only the chromium films 507 to 509 were etched to expose the boundary between the impurity region 510 and the active region therebetween, and activation was performed by irradiating a KrF excimer laser beam in this state. (FIG. 5
(C))

After that, the wiring 504 is covered with a thickness of 1 to 5
A μm polyimide coating 511 was provided. As the polyimide, a photosensitive polyimide is easily used because of its ease of patterning. (FIG. 5 (D))

In this state, the wiring 50 is placed in an electrolytic solution.
4-506 through current, to form an anodic oxide 512 and 513 having a thickness of 2000-2500 Å. However, wiring 5
The part in which the polyimide was provided earlier in 04 was not anodized. (FIG. 5E)

Finally, an interlayer insulator having a thickness of 2000-5
A silicon oxide film 514 of 2,000 .ANG.
0, a contact hole was formed. Further, in a part of the wiring 506, all the interlayer insulator was removed to expose the anodic oxide 513. Then, a wiring electrode 515 and 516 using a multilayer film of titanium nitride (thickness 500 Å) and aluminum (thickness 3500 Å), thereby completing the circuit. At this time, the wiring 516 constitutes a capacitor using the wiring 506 and the anodic oxide 513 as dielectrics. (FIG. 5
(F))

[0042]

According to the present invention, the reliability of a MIS type semiconductor device such as a MOS transistor and a thin film transistor manufactured by a low temperature process can be improved. Specifically, the source is grounded, and +20 V or more or -2 is applied to one or both of the drain and the gate.
Even when left for 10 hours or more in a state where a potential of 0 V or less was applied, the characteristics of the transistor were not significantly affected.

Although the embodiment mainly focuses on a thin film transistor, the effect of the present invention can of course be similarly obtained in a MIS type semiconductor device manufactured on a single crystal semiconductor substrate. In addition to the silicon taken up in the examples, the same effects can be obtained in silicon-germanium alloy, silicon carbide, germanium, cadmium selenide, cadmium sulfide, gallium arsenide, and the like.

As described above, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. (Cross section)

FIG. 2 shows an embodiment of the prior art. (Cross section)

FIG. 3 shows an embodiment of the present invention. (Cross section)

FIG. 4 shows an embodiment of the present invention. (Top view)

FIG. 5 shows an embodiment of the present invention. (Cross section)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 ... Substrate 102 ... Base insulating film 103 ... Island-shaped semiconductor region 104 ... Gate insulating film 105 ... Gate electrode (gate wiring) 106 ... Plated film 107 ... Impurity Region 108: Anodized oxide 109: Interlayer insulator 110: Electrode (wiring)

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (6)

(57) [Claims] An insulating film is formed on a semiconductor, a wiring is formed on the insulating film , a metal film is formed on the wiring, and impurities are removed using the wiring and the metal film as a mask.
An impurity region introduced into the semiconductor, and the impurity region
Forming an active region in contact with the wiring, removing a part or all of the metal film, and performing annealing using a non-coherent light source from above the wiring.
The crystallinity of the impurity region and part of the active region.
A method for manufacturing a MIS semiconductor device, which is improved . 2. An insulating film is formed on a semiconductor, a wiring is formed on the insulating film , a metal film is formed on the wiring, and impurities are removed using the wiring and the metal film as a mask.
An impurity region introduced into the semiconductor, and the impurity region
Forming an active region in contact with the wiring, removing a part or all of the metal film, and performing annealing using a non-coherent light source from above the wiring.
The crystallinity of the impurity region and part of the active region.
A method of manufacturing a MIS type semiconductor device, wherein the method further comprises anodizing the wiring and covering the wiring with an anodic oxide film . 3. An insulating film is formed on a semiconductor, a wiring is formed on the insulating film , a metal film is formed on the wiring, and impurities are removed using the wiring and the metal film as a mask.
An impurity region introduced into the semiconductor, and the impurity region
Forming an active region in contact with the wiring, removing a part or all of the metal film, and performing annealing using a non-coherent light source from above the wiring.
The crystallinity of the impurity region and part of the active region.
And anodizing the wiring, and covering the wiring with an anodized film.
A manufacturing how the S-type semiconductor device, the thickness of the anodic oxide film, a method for manufacturing a MIS type semiconductor device, wherein a thinner than the thickness of the metal coating. Wherein any one smell of claims 1 to 3
The wiring is made of aluminum, titanium, tantalum, silicon, tungsten or molybdenum as a constituent element.
A method for manufacturing a MIS type semiconductor device, comprising a metal film or an alloy film containing the above constituent elements . 5. any one smell of claims 1 to 3
The metal coating is made of copper, nickel, chromium, zinc,
Made of tin, gold, silver, platinum, palladium or rhodium
Fabrication of MIS type semiconductor device characterized by being a film
Method. 6. any one smell of claims 1 to 3
The non-coherent light source may be a flash lamp or
Is one or more selected from Krypton clamps
Method of manufacturing MIS type semiconductor device characterized by being
Law.