JPH01205569A - Manufacture of mos-type semiconductor device - Google Patents

Abstract

PURPOSE:To form a side-face spacer of a self-matching gate to obviate a dry etching process by forming an electroless plating layer including at least a side of a gate electrode of a MOS-type semiconductor device. CONSTITUTION:A field SiO2 film 2 for separating elements is formed at a desired position of a substrate 1, after which the Si substrate 1 is oxidized to grow a gate SiO2 film 3. A gate electrode 4 is formed thereon, and a photoresist 5 is formed to the form of a pattern. The gate electrode film 4 is etched with a photoresist 5 as a mask to form a gate electrode 6. After this, an ion implantation layer 7 is formed with the gate electrode 6 as a mask. Next, a plating layer 8 is formed on the surface including the side of the gate electrode 6 by electroless plating. Impurity ion implantation using high-density phosphorus or arsenic is made to form a source 9 and a drain 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing MOS type semiconductor devices, and relates to a self-aligned process such as a high melting point metal gate.

[Conventional technology]

In the conventional self-alignment process, Japanese Patent Application Laid-Open No. 62-515
As shown in Fig. 06, after a gate is provided on a semiconductor substrate via a gate insulating film, an insulating film is deposited on the entire surface of the substrate, and an etching gas is applied almost perpendicularly to the substrate to remove the insulating film. A method has been used in which dry etching is performed to form an insulating film pattern such as ffl') on the side surface of the gate.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology requires a step of depositing an insulating film and a step of dry etching the insulating film, which both require expensive equipment and have the problem that the dry etching step is unnecessary. Ta.

The present invention eliminates the problems of the prior art and provides a method for forming side spacers of a self-aligned gate using an inexpensive device called electroless plating and a dry etching process, and also stabilizes the surface of the gate electrode. The purpose is to provide a method for converting

[Means to solve the problem]

In order to solve the above problems, the present invention is based on forming an electroless plating layer on the rJ surface including at least the side surfaces of the gate electrode of the MO3 type semiconductor device.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 shows the manufacturing process of an IAO8 type O8 effect transistor according to the present invention in the order of steps. As an example, N channels will be explained.

(σ) A field 5in2 film 2 for isolation between elements is formed at a desired position on an 81 substrate 1 having a P-type (100) plane by a well-known selective oxidation method.

After that, the 81 substrate 1 is oxidized again and the game is completed.

A film 6 is grown.

(h) On top of this, an electrode film 4 of tungsten or other gold I+4 film is formed by sputtering or chemical vapor deposition.
is formed into a pattern by photolithography.

(C) Gate electrode film 4 is etched using photon cyst 5 as a mask to form gate electrode 6. At this time, dry etching using Freon gas is used.

After this, the process may proceed to the next step, but here, an ion-implanted layer 7 of impurities of phosphorus or arsenic at a low concentration is formed to form a shallow diffusion layer using the gate electrode 6 as a mask.

(d) Next, a plating layer 8 made of a metal film such as nickel is formed on the surface including the side surfaces of the gate electrode film by electroless plating, and impurity ions of high concentration phosphorus or arsenic are implanted into the source 9. , and drain 10 are formed. (
If the shallow ion implantation layer 7 is not formed in step C), only the high concentration ion implantation in this step may be sufficient, and the low concentration diffusion region may also be formed by thermal diffusion.

FIG. 2 shows another embodiment of the invention.

(a) A photoresist 5 is formed into a pattern as shown in FIG. 1<h>, and ions of phosphorus or arsenic are implanted shallowly and at a low concentration while the photoresist remains to form an ion implantation layer 7.

This ion implantation is not necessarily safe, and in that case, it is possible to leave the source/drain formed in a subsequent process, or to improve this by thermal diffusion treatment from the source/drain.

(b) Next, plating layer 8 is electrolessly formed only on the side surfaces of the gate electrode film using photoresist 5 as a mask.

(C) The photoresist 5 is removed and a source 9 and a tunnel 10 are formed by high-concentration ion implantation of phosphorus or arsenic.

In the present invention, so-called LDD (Light),
y I explained about the Doped Drain structure, but D D D (DOufle Diffusion
Needless to say, it can be applied to a drain structure, etc., and the gate' electrode may be made of not only tungsten but also a high melting point metal such as molybdenum or polycrystalline 81, and the plating layer is
Needless to say, it may be made of not only nickel but also the same material as the gate electrode, or may be made of a single layer or multiple layers of high melting point metal such as copper, platinum, or palladium.

Furthermore, the present invention provides a gate electrode with 5iae Wa], I
Not limited to the formation of 5pacer, but also electrode wiring, such as At
It is not difficult to imagine that the present invention can be applied to electroless plating for anti-migration treatment of electrode wiring, or electroless plating for reducing contact resistance.

〔Effect of the invention〕

According to the present invention, L D D J! It-made or DDD
MO8 type semiconductor devices with structure and gate surface mj stabilization treatment can be formed at low cost and with fewer steps.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) show M according to an embodiment of the present invention.
Manufacturing process diagram of OS transistor, Figure 2 (a) to (C)
These are main part process diagrams of another example in which only 5ide wall 5pacer was formed. 1... S1 substrate 2... ・Field 5102 film 5...
...Gate 5i021 conversion 4...Gate electrode film 5...Photonist 6...Gate @ pole 7...Ion implantation layer 8.・・・・・・Plating layer 9・・・・・・・・・Source 10・・・・・・Drain and above Applicant Seiko Epson Co., Ltd. agent Patent attorney Mogamisuji (1 other person) q mouth

Claims (2)

[Claims] (1) After providing a gate made of tungsten, molybdenum, or silicon on a semiconductor substrate via a gate insulating film, the surface including at least the side surfaces of the gate is coated with tungsten, molybdenum, nickel, copper, platinum, palladium, etc. 1. A MOS type semiconductor device comprising: forming an electrolytic plating layer, and introducing impurities into the surface of the substrate using the gate and the electroless plating layer as a mask to form a source/drain. (2) Before forming the electroless plating layer, an impurity of the same conductivity type as the source/drain is introduced into the surface of the substrate using the gate as a mask to form a shallow impurity layer or an impurity layer with a lower concentration than the source/drain; A method of manufacturing a MOS type semiconductor device, characterized in that the source and drain are formed so as not to reach a region immediately below the gate.